Merge tag 'for-linville-20131001' of git://github.com/kvalo/ath

[~andy/linux] / drivers / gpu / drm / radeon / rv6xx_dpm.c

diff --git a/drivers/gpu/drm/radeon/rv6xx_dpm.c b/drivers/gpu/drm/radeon/rv6xx_dpm.c
index 363018c60412c1d7374ee60a176abe2f5c49dce7..5811d277a36a60ec845cbcadf9588326a01a488b 100644 (file)
--- a/drivers/gpu/drm/radeon/rv6xx_dpm.c
+++ b/drivers/gpu/drm/radeon/rv6xx_dpm.c
@@ -1758,8 +1758,6 @@ int rv6xx_dpm_set_power_state(struct radeon_device *rdev)
 
        rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
 
-       rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
-
        return 0;
 }
 
@@ -1918,6 +1916,7 @@ static int rv6xx_parse_power_table(struct radeon_device *rdev)
                         (power_state->v1.ucNonClockStateIndex *
                          power_info->pplib.ucNonClockSize));
                if (power_info->pplib.ucStateEntrySize - 1) {
+                       u8 *idx;
                        ps = kzalloc(sizeof(struct rv6xx_ps), GFP_KERNEL);
                        if (ps == NULL) {
                                kfree(rdev->pm.dpm.ps);
@@ -1926,12 +1925,12 @@ static int rv6xx_parse_power_table(struct radeon_device *rdev)
                        rdev->pm.dpm.ps[i].ps_priv = ps;
                        rv6xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
                                                         non_clock_info);
+                       idx = (u8 *)&power_state->v1.ucClockStateIndices[0];
                        for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
                                clock_info = (union pplib_clock_info *)
                                        (mode_info->atom_context->bios + data_offset +
                                         le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
-                                        (power_state->v1.ucClockStateIndices[j] *
-                                         power_info->pplib.ucClockInfoSize));
+                                        (idx[j] * power_info->pplib.ucClockInfoSize));
                                rv6xx_parse_pplib_clock_info(rdev,
                                                             &rdev->pm.dpm.ps[i], j,
                                                             clock_info);
@@ -1944,9 +1943,7 @@ static int rv6xx_parse_power_table(struct radeon_device *rdev)
 
 int rv6xx_dpm_init(struct radeon_device *rdev)
 {
-       int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
-       uint16_t data_offset, size;
-       uint8_t frev, crev;
+       struct radeon_atom_ss ss;
        struct atom_clock_dividers dividers;
        struct rv6xx_power_info *pi;
        int ret;
@@ -1989,16 +1986,18 @@ int rv6xx_dpm_init(struct radeon_device *rdev)
 
        pi->gfx_clock_gating = true;
 
-       if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
-                                   &frev, &crev, &data_offset)) {
-               pi->sclk_ss = true;
-               pi->mclk_ss = true;
+       pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
+                                                      ASIC_INTERNAL_ENGINE_SS, 0);
+       pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
+                                                      ASIC_INTERNAL_MEMORY_SS, 0);
+
+       /* Disable sclk ss, causes hangs on a lot of systems */
+       pi->sclk_ss = false;
+
+       if (pi->sclk_ss || pi->mclk_ss)
                pi->dynamic_ss = true;
-       } else {
-               pi->sclk_ss = false;
-               pi->mclk_ss = false;
+       else
                pi->dynamic_ss = false;
-       }
 
        pi->dynamic_pcie_gen2 = true;