drm/radeon: add rv740 drm support.

[~andy/linux] / drivers / gpu / drm / radeon / r600_cp.c

diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 9d14eee3ed092e52e82b7c05aa20c2e30502f237..aa4eee4b7f3a5adbd9185ec8785ff6144531149f 100644 (file)
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -388,17 +388,17 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
                DRM_INFO("Loading RS780 CP Microcode\n");
                for (i = 0; i < PM4_UCODE_SIZE; i++) {
                        RADEON_WRITE(R600_CP_ME_RAM_DATA,
-                                    RV670_cp_microcode[i][0]);
+                                    RS780_cp_microcode[i][0]);
                        RADEON_WRITE(R600_CP_ME_RAM_DATA,
-                                    RV670_cp_microcode[i][1]);
+                                    RS780_cp_microcode[i][1]);
                        RADEON_WRITE(R600_CP_ME_RAM_DATA,
-                                    RV670_cp_microcode[i][2]);
+                                    RS780_cp_microcode[i][2]);
                }
 
                RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
                DRM_INFO("Loading RS780 PFP Microcode\n");
                for (i = 0; i < PFP_UCODE_SIZE; i++)
-                       RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]);
+                       RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]);
        }
        RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
        RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
@@ -489,15 +489,16 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
                        RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]);
                RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 
-       } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730)) {
+       } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)) {
                RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-               DRM_INFO("Loading RV730 PFP Microcode\n");
+               DRM_INFO("Loading RV730/RV740 PFP Microcode\n");
                for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
                        RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]);
                RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 
                RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
-               DRM_INFO("Loading RV730 CP Microcode\n");
+               DRM_INFO("Loading RV730/RV740 CP Microcode\n");
                for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
                        RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]);
                RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
@@ -1324,6 +1325,10 @@ static void r700_gfx_init(struct drm_device *dev,
                dev_priv->r700_sc_prim_fifo_size = 0xf9;
                dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
                dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
+               if (dev_priv->r600_sx_max_export_pos_size > 16) {
+                       dev_priv->r600_sx_max_export_pos_size -= 16;
+                       dev_priv->r600_sx_max_export_smx_size += 16;
+               }
                break;
        case CHIP_RV710:
                dev_priv->r600_max_pipes = 2;
@@ -1345,6 +1350,31 @@ static void r700_gfx_init(struct drm_device *dev,
                dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
                dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
                break;
+       case CHIP_RV740:
+               dev_priv->r600_max_pipes = 4;
+               dev_priv->r600_max_tile_pipes = 4;
+               dev_priv->r600_max_simds = 8;
+               dev_priv->r600_max_backends = 4;
+               dev_priv->r600_max_gprs = 256;
+               dev_priv->r600_max_threads = 248;
+               dev_priv->r600_max_stack_entries = 512;
+               dev_priv->r600_max_hw_contexts = 8;
+               dev_priv->r600_max_gs_threads = 16 * 2;
+               dev_priv->r600_sx_max_export_size = 256;
+               dev_priv->r600_sx_max_export_pos_size = 32;
+               dev_priv->r600_sx_max_export_smx_size = 224;
+               dev_priv->r600_sq_num_cf_insts = 2;
+
+               dev_priv->r700_sx_num_of_sets = 7;
+               dev_priv->r700_sc_prim_fifo_size = 0x100;
+               dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
+               dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
+
+               if (dev_priv->r600_sx_max_export_pos_size > 16) {
+                       dev_priv->r600_sx_max_export_pos_size -= 16;
+                       dev_priv->r600_sx_max_export_smx_size += 16;
+               }
+               break;
        default:
                break;
        }
@@ -1493,6 +1523,7 @@ static void r700_gfx_init(struct drm_device *dev,
                break;
        case CHIP_RV730:
        case CHIP_RV710:
+       case CHIP_RV740:
        default:
                sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
                break;
@@ -1569,6 +1600,7 @@ static void r700_gfx_init(struct drm_device *dev,
        switch (dev_priv->flags & RADEON_FAMILY_MASK) {
        case CHIP_RV770:
        case CHIP_RV730:
+       case CHIP_RV740:
                gs_prim_buffer_depth = 384;
                break;
        case CHIP_RV710: