Merge branch 'kvm-updates/3.4' of git://git.kernel.org/pub/scm/virt/kvm/kvm

[~andy/linux] / drivers / gpu / drm / radeon / r600.c

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 17ca72ce30277332965fa7772884a93764c0664a..391bd2636a8054bb5e102388060e54a1b10f9c97 100644 (file)
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -49,6 +49,7 @@
 #define EVERGREEN_PM4_UCODE_SIZE 1376
 #define EVERGREEN_RLC_UCODE_SIZE 768
 #define CAYMAN_RLC_UCODE_SIZE 1024
+#define ARUBA_RLC_UCODE_SIZE 1536
 
 /* Firmware Names */
 MODULE_FIRMWARE("radeon/R600_pfp.bin");
@@ -2226,7 +2227,7 @@ int r600_cp_resume(struct radeon_device *rdev)
 
        r600_cp_start(rdev);
        ring->ready = true;
-       r = radeon_ring_test(rdev, ring);
+       r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
        if (r) {
                ring->ready = false;
                return r;
@@ -2452,7 +2453,7 @@ int r600_startup(struct radeon_device *rdev)
        r = r600_blit_init(rdev);
        if (r) {
                r600_blit_fini(rdev);
-               rdev->asic->copy = NULL;
+               rdev->asic->copy.copy = NULL;
                dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
        }
 
@@ -2493,7 +2494,7 @@ int r600_startup(struct radeon_device *rdev)
        if (r)
                return r;
 
-       r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
+       r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
        if (r) {
                DRM_ERROR("radeon: failed testing IB (%d).\n", r);
                rdev->accel_working = false;
@@ -2701,13 +2702,14 @@ void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
        radeon_ring_write(ring, ib->length_dw);
 }
 
-int r600_ib_test(struct radeon_device *rdev, int ring)
+int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
 {
        struct radeon_ib *ib;
        uint32_t scratch;
        uint32_t tmp = 0;
        unsigned i;
        int r;
+       int ring_index = radeon_ring_index(rdev, ring);
 
        r = radeon_scratch_get(rdev, &scratch);
        if (r) {
@@ -2715,7 +2717,7 @@ int r600_ib_test(struct radeon_device *rdev, int ring)
                return r;
        }
        WREG32(scratch, 0xCAFEDEAD);
-       r = radeon_ib_get(rdev, ring, &ib, 256);
+       r = radeon_ib_get(rdev, ring_index, &ib, 256);
        if (r) {
                DRM_ERROR("radeon: failed to get ib (%d).\n", r);
                return r;
@@ -2723,20 +2725,7 @@ int r600_ib_test(struct radeon_device *rdev, int ring)
        ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
        ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
        ib->ptr[2] = 0xDEADBEEF;
-       ib->ptr[3] = PACKET2(0);
-       ib->ptr[4] = PACKET2(0);
-       ib->ptr[5] = PACKET2(0);
-       ib->ptr[6] = PACKET2(0);
-       ib->ptr[7] = PACKET2(0);
-       ib->ptr[8] = PACKET2(0);
-       ib->ptr[9] = PACKET2(0);
-       ib->ptr[10] = PACKET2(0);
-       ib->ptr[11] = PACKET2(0);
-       ib->ptr[12] = PACKET2(0);
-       ib->ptr[13] = PACKET2(0);
-       ib->ptr[14] = PACKET2(0);
-       ib->ptr[15] = PACKET2(0);
-       ib->length_dw = 16;
+       ib->length_dw = 3;
        r = radeon_ib_schedule(rdev, ib);
        if (r) {
                radeon_scratch_free(rdev, scratch);
@@ -2790,7 +2779,7 @@ void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
        rdev->ih.rptr = 0;
 }
 
-static int r600_ih_ring_alloc(struct radeon_device *rdev)
+int r600_ih_ring_alloc(struct radeon_device *rdev)
 {
        int r;
 
@@ -2826,7 +2815,7 @@ static int r600_ih_ring_alloc(struct radeon_device *rdev)
        return 0;
 }
 
-static void r600_ih_ring_fini(struct radeon_device *rdev)
+void r600_ih_ring_fini(struct radeon_device *rdev)
 {
        int r;
        if (rdev->ih.ring_obj) {
@@ -2873,10 +2862,17 @@ static int r600_rlc_init(struct radeon_device *rdev)
 
        r600_rlc_stop(rdev);
 
-       WREG32(RLC_HB_BASE, 0);
        WREG32(RLC_HB_CNTL, 0);
-       WREG32(RLC_HB_RPTR, 0);
-       WREG32(RLC_HB_WPTR, 0);
+
+       if (rdev->family == CHIP_ARUBA) {
+               WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
+               WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
+       }
+       if (rdev->family <= CHIP_CAYMAN) {
+               WREG32(RLC_HB_BASE, 0);
+               WREG32(RLC_HB_RPTR, 0);
+               WREG32(RLC_HB_WPTR, 0);
+       }
        if (rdev->family <= CHIP_CAICOS) {
                WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
                WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
@@ -2885,7 +2881,12 @@ static int r600_rlc_init(struct radeon_device *rdev)
        WREG32(RLC_UCODE_CNTL, 0);
 
        fw_data = (const __be32 *)rdev->rlc_fw->data;
-       if (rdev->family >= CHIP_CAYMAN) {
+       if (rdev->family >= CHIP_ARUBA) {
+               for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
+                       WREG32(RLC_UCODE_ADDR, i);
+                       WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
+               }
+       } else if (rdev->family >= CHIP_CAYMAN) {
                for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
                        WREG32(RLC_UCODE_ADDR, i);
                        WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));