Merge branch 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

[~andy/linux] / drivers / gpu / drm / radeon / atombios_crtc.c

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index a22d5a3bca4ed63d695c7f433c4b343cd462a720..12ad512bd3d33ad316655400212626585126c6de 100644 (file)
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -44,10 +44,6 @@ static void atombios_overscan_setup(struct drm_crtc *crtc,
 
        memset(&args, 0, sizeof(args));
 
-       args.usOverscanRight = 0;
-       args.usOverscanLeft = 0;
-       args.usOverscanBottom = 0;
-       args.usOverscanTop = 0;
        args.ucCRTC = radeon_crtc->crtc_id;
 
        switch (radeon_crtc->rmx_type) {
@@ -56,7 +52,6 @@ static void atombios_overscan_setup(struct drm_crtc *crtc,
                args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
                args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
                args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
-               atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
                break;
        case RMX_ASPECT:
                a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
@@ -69,17 +64,16 @@ static void atombios_overscan_setup(struct drm_crtc *crtc,
                        args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
                        args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
                }
-               atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
                break;
        case RMX_FULL:
        default:
-               args.usOverscanRight = 0;
-               args.usOverscanLeft = 0;
-               args.usOverscanBottom = 0;
-               args.usOverscanTop = 0;
-               atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+               args.usOverscanRight = radeon_crtc->h_border;
+               args.usOverscanLeft = radeon_crtc->h_border;
+               args.usOverscanBottom = radeon_crtc->v_border;
+               args.usOverscanTop = radeon_crtc->v_border;
                break;
        }
+       atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 
 static void atombios_scaler_setup(struct drm_crtc *crtc)
@@ -282,22 +276,22 @@ atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
        u16 misc = 0;
 
        memset(&args, 0, sizeof(args));
-       args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
+       args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
        args.usH_Blanking_Time =
-               cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
-       args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
+               cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
+       args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
        args.usV_Blanking_Time =
-           cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
+               cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
        args.usH_SyncOffset =
-               cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
+               cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
        args.usH_SyncWidth =
                cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
        args.usV_SyncOffset =
-               cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
+               cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
        args.usV_SyncWidth =
                cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
-       /*args.ucH_Border = mode->hborder;*/
-       /*args.ucV_Border = mode->vborder;*/
+       args.ucH_Border = radeon_crtc->h_border;
+       args.ucV_Border = radeon_crtc->v_border;
 
        if (mode->flags & DRM_MODE_FLAG_NVSYNC)
                misc |= ATOM_VSYNC_POLARITY;
@@ -818,7 +812,7 @@ static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 
        /* no fb bound */
        if (!crtc->fb) {
-               DRM_DEBUG("No FB bound\n");
+               DRM_DEBUG_KMS("No FB bound\n");
                return 0;
        }
 
@@ -862,6 +856,11 @@ static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
                return -EINVAL;
        }
 
+       if (tiling_flags & RADEON_TILING_MACRO)
+               fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
+       else if (tiling_flags & RADEON_TILING_MICRO)
+               fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
+
        switch (radeon_crtc->crtc_id) {
        case 0:
                WREG32(AVIVO_D1VGA_CONTROL, 0);
@@ -952,7 +951,7 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 
        /* no fb bound */
        if (!crtc->fb) {
-               DRM_DEBUG("No FB bound\n");
+               DRM_DEBUG_KMS("No FB bound\n");
                return 0;
        }
 
@@ -1000,11 +999,18 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
                return -EINVAL;
        }
 
-       if (tiling_flags & RADEON_TILING_MACRO)
-               fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
+       if (rdev->family >= CHIP_R600) {
+               if (tiling_flags & RADEON_TILING_MACRO)
+                       fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
+               else if (tiling_flags & RADEON_TILING_MICRO)
+                       fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
+       } else {
+               if (tiling_flags & RADEON_TILING_MACRO)
+                       fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
 
-       if (tiling_flags & RADEON_TILING_MICRO)
-               fb_format |= AVIVO_D1GRPH_TILED;
+               if (tiling_flags & RADEON_TILING_MICRO)
+                       fb_format |= AVIVO_D1GRPH_TILED;
+       }
 
        if (radeon_crtc->crtc_id == 0)
                WREG32(AVIVO_D1VGA_CONTROL, 0);
@@ -1164,10 +1170,8 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
        atombios_crtc_set_pll(crtc, adjusted_mode);
        atombios_enable_ss(crtc);
 
-       if (ASIC_IS_DCE4(rdev))
+       if (ASIC_IS_AVIVO(rdev))
                atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
-       else if (ASIC_IS_AVIVO(rdev))
-               atombios_crtc_set_timing(crtc, adjusted_mode);
        else {
                atombios_crtc_set_timing(crtc, adjusted_mode);
                if (radeon_crtc->crtc_id == 0)