Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...

[~andy/linux] / drivers / gpu / drm / nouveau / nv04_fifo.c

diff --git a/drivers/gpu/drm/nouveau/nv04_fifo.c b/drivers/gpu/drm/nouveau/nv04_fifo.c
index 0c3cd53c73138142bf34e5f78b9ddfddf90bca7c..f31347b8c9b05da1977fcd00b5108c725434f689 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv04_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv04_fifo.c
@@ -71,6 +71,40 @@ nv04_fifo_reassign(struct drm_device *dev, bool enable)
        return (reassign == 1);
 }
 
+bool
+nv04_fifo_cache_flush(struct drm_device *dev)
+{
+       struct drm_nouveau_private *dev_priv = dev->dev_private;
+       struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
+       uint64_t start = ptimer->read(dev);
+
+       do {
+               if (nv_rd32(dev, NV03_PFIFO_CACHE1_GET) ==
+                   nv_rd32(dev, NV03_PFIFO_CACHE1_PUT))
+                       return true;
+
+       } while (ptimer->read(dev) - start < 100000000);
+
+       NV_ERROR(dev, "Timeout flushing the PFIFO cache.\n");
+
+       return false;
+}
+
+bool
+nv04_fifo_cache_pull(struct drm_device *dev, bool enable)
+{
+       uint32_t pull = nv_rd32(dev, NV04_PFIFO_CACHE1_PULL0);
+
+       if (enable) {
+               nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull | 1);
+       } else {
+               nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull & ~1);
+               nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
+       }
+
+       return !!(pull & 1);
+}
+
 int
 nv04_fifo_channel_id(struct drm_device *dev)
 {