* Roy Spliet <r.spliet@student.tudelft.nl>
*/
-
-#include "drmP.h"
-#include "drm.h"
-#include "drm_sarea.h"
-
-#include "nouveau_drv.h"
+#include "nouveau_drm.h"
#include "nouveau_pm.h"
-#include <core/mm.h>
-#include <engine/fifo.h>
-#include "nouveau_fence.h"
-
-/*
- * Cleanup everything
- */
-void
-nouveau_mem_vram_fini(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- ttm_bo_device_release(&dev_priv->ttm.bdev);
-
- nouveau_ttm_global_release(dev_priv);
-
- if (dev_priv->fb_mtrr >= 0) {
- drm_mtrr_del(dev_priv->fb_mtrr,
- pci_resource_start(dev->pdev, 1),
- pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
- dev_priv->fb_mtrr = -1;
- }
-}
-
-void
-nouveau_mem_gart_fini(struct drm_device *dev)
-{
- nouveau_sgdma_takedown(dev);
-}
-
-int
-nouveau_mem_vram_init(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
- int ret, dma_bits;
-
- dma_bits = 32;
- if (dev_priv->card_type >= NV_50) {
- if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
- dma_bits = 40;
- } else
- if (0 && pci_is_pcie(dev->pdev) &&
- dev_priv->chipset > 0x40 &&
- dev_priv->chipset != 0x45) {
- if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39)))
- dma_bits = 39;
- }
-
- ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
- if (ret)
- return ret;
- ret = pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
- if (ret) {
- /* Reset to default value. */
- pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(32));
- }
-
-
- ret = nouveau_ttm_global_init(dev_priv);
- if (ret)
- return ret;
-
- ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
- dev_priv->ttm.bo_global_ref.ref.object,
- &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
- dma_bits <= 32 ? true : false);
- if (ret) {
- NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
- return ret;
- }
-
- dev_priv->fb_available_size = nvfb_vram_size(dev);
- dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
- if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
- dev_priv->fb_mappable_pages = pci_resource_len(dev->pdev, 1);
- dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
-
- dev_priv->fb_available_size -= nvimem_reserved(dev);
- dev_priv->fb_aper_free = dev_priv->fb_available_size;
-
- /* mappable vram */
- ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
- dev_priv->fb_available_size >> PAGE_SHIFT);
- if (ret) {
- NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
- return ret;
- }
-
- if (dev_priv->card_type < NV_50) {
- ret = nouveau_bo_new(dev, 256*1024, 0, TTM_PL_FLAG_VRAM,
- 0, 0, NULL, &dev_priv->vga_ram);
- if (ret == 0)
- ret = nouveau_bo_pin(dev_priv->vga_ram,
- TTM_PL_FLAG_VRAM);
-
- if (ret) {
- NV_WARN(dev, "failed to reserve VGA memory\n");
- nouveau_bo_ref(NULL, &dev_priv->vga_ram);
- }
- }
-
- dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
- pci_resource_len(dev->pdev, 1),
- DRM_MTRR_WC);
- return 0;
-}
-
-int
-nouveau_mem_gart_init(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
- int ret;
-
- if (!nvdrm_gart_init(dev, &dev_priv->gart_info.aper_base,
- &dev_priv->gart_info.aper_size))
- dev_priv->gart_info.type = NOUVEAU_GART_AGP;
-
- if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
- ret = nouveau_sgdma_init(dev);
- if (ret) {
- NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
- return ret;
- }
- }
-
- NV_INFO(dev, "%d MiB GART (aperture)\n",
- (int)(dev_priv->gart_info.aper_size >> 20));
- dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
-
- ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
- dev_priv->gart_info.aper_size >> PAGE_SHIFT);
- if (ret) {
- NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
- return ret;
- }
-
- return 0;
-}
+#include <subdev/fb.h>
static int
nv40_mem_timing_calc(struct drm_device *dev, u32 freq,
struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
+ struct nouveau_drm *drm = nouveau_drm(dev);
+
t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
/* XXX: I don't trust the -1's and +1's... they must come
e->tRCDWR << 8 |
e->tRCDRD);
- NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", t->id,
+ NV_DEBUG(drm, "Entry %d: 220: %08x %08x %08x\n", t->id,
t->reg[0], t->reg[1], t->reg[2]);
return 0;
}
struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
+ struct nouveau_device *device = nouveau_dev(dev);
+ struct nouveau_fb *pfb = nouveau_fb(device);
+ struct nouveau_drm *drm = nouveau_drm(dev);
struct bit_entry P;
uint8_t unk18 = 1, unk20 = 0, unk21 = 0, tmp7_3;
t->reg[7] = 0x4000202 | (e->tCL - 1) << 16;
/* XXX: P.version == 1 only has DDR2 and GDDR3? */
- if (nvfb_vram_type(dev) == NV_MEM_TYPE_DDR2) {
+ if (pfb->ram.type == NV_MEM_TYPE_DDR2) {
t->reg[5] |= (e->tCL + 3) << 8;
t->reg[6] |= (t->tCWL - 2) << 8;
t->reg[8] |= (e->tCL - 4);
0x202;
}
- NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", t->id,
+ NV_DEBUG(drm, "Entry %d: 220: %08x %08x %08x %08x\n", t->id,
t->reg[0], t->reg[1], t->reg[2], t->reg[3]);
- NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n",
+ NV_DEBUG(drm, " 230: %08x %08x %08x %08x\n",
t->reg[4], t->reg[5], t->reg[6], t->reg[7]);
- NV_DEBUG(dev, " 240: %08x\n", t->reg[8]);
+ NV_DEBUG(drm, " 240: %08x\n", t->reg[8]);
return 0;
}
struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
+ struct nouveau_drm *drm = nouveau_drm(dev);
+
if (e->tCWL > 0)
t->tCWL = e->tCWL;
t->reg[4] = (boot->reg[4] & 0xfff00fff) |
(e->tRRD&0x1f) << 15;
- NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", t->id,
+ NV_DEBUG(drm, "Entry %d: 290: %08x %08x %08x %08x\n", t->id,
t->reg[0], t->reg[1], t->reg[2], t->reg[3]);
- NV_DEBUG(dev, " 2a0: %08x\n", t->reg[4]);
+ NV_DEBUG(drm, " 2a0: %08x\n", t->reg[4]);
return 0;
}
struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
+ struct nouveau_drm *drm = nouveau_drm(dev);
+
t->drive_strength = 0;
if (len < 15) {
t->odt = boot->odt;
}
if (e->tCL >= NV_MEM_CL_DDR2_MAX) {
- NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
+ NV_WARN(drm, "(%u) Invalid tCL: %u", t->id, e->tCL);
return -ERANGE;
}
if (e->tWR >= NV_MEM_WR_DDR2_MAX) {
- NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
+ NV_WARN(drm, "(%u) Invalid tWR: %u", t->id, e->tWR);
return -ERANGE;
}
if (t->odt > 3) {
- NV_WARN(dev, "(%u) Invalid odt value, assuming disabled: %x",
+ NV_WARN(drm, "(%u) Invalid odt value, assuming disabled: %x",
t->id, t->odt);
t->odt = 0;
}
(t->odt & 0x1) << 2 |
(t->odt & 0x2) << 5;
- NV_DEBUG(dev, "(%u) MR: %08x", t->id, t->mr[0]);
+ NV_DEBUG(drm, "(%u) MR: %08x", t->id, t->mr[0]);
return 0;
}
-uint8_t nv_mem_wr_lut_ddr3[NV_MEM_WR_DDR3_MAX] = {
+static const uint8_t nv_mem_wr_lut_ddr3[NV_MEM_WR_DDR3_MAX] = {
0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
static int
struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
+ struct nouveau_drm *drm = nouveau_drm(dev);
u8 cl = e->tCL - 4;
t->drive_strength = 0;
}
if (e->tCL >= NV_MEM_CL_DDR3_MAX || e->tCL < 4) {
- NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
+ NV_WARN(drm, "(%u) Invalid tCL: %u", t->id, e->tCL);
return -ERANGE;
}
if (e->tWR >= NV_MEM_WR_DDR3_MAX || e->tWR < 4) {
- NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
+ NV_WARN(drm, "(%u) Invalid tWR: %u", t->id, e->tWR);
return -ERANGE;
}
if (e->tCWL < 5) {
- NV_WARN(dev, "(%u) Invalid tCWL: %u", t->id, e->tCWL);
+ NV_WARN(drm, "(%u) Invalid tCWL: %u", t->id, e->tCWL);
return -ERANGE;
}
(t->odt & 0x4) << 7;
t->mr[2] = (boot->mr[2] & 0x20ffb7) | (e->tCWL - 5) << 3;
- NV_DEBUG(dev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[2]);
+ NV_DEBUG(drm, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[2]);
return 0;
}
-uint8_t nv_mem_cl_lut_gddr3[NV_MEM_CL_GDDR3_MAX] = {
+static const uint8_t nv_mem_cl_lut_gddr3[NV_MEM_CL_GDDR3_MAX] = {
0, 0, 0, 0, 4, 5, 6, 7, 0, 1, 2, 3, 8, 9, 10, 11};
-uint8_t nv_mem_wr_lut_gddr3[NV_MEM_WR_GDDR3_MAX] = {
+static const uint8_t nv_mem_wr_lut_gddr3[NV_MEM_WR_GDDR3_MAX] = {
0, 0, 0, 0, 0, 2, 3, 8, 9, 10, 11, 0, 0, 1, 1, 0, 3};
static int
struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
+ struct nouveau_drm *drm = nouveau_drm(dev);
+
if (len < 15) {
t->drive_strength = boot->drive_strength;
t->odt = boot->odt;
}
if (e->tCL >= NV_MEM_CL_GDDR3_MAX) {
- NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
+ NV_WARN(drm, "(%u) Invalid tCL: %u", t->id, e->tCL);
return -ERANGE;
}
if (e->tWR >= NV_MEM_WR_GDDR3_MAX) {
- NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
+ NV_WARN(drm, "(%u) Invalid tWR: %u", t->id, e->tWR);
return -ERANGE;
}
if (t->odt > 3) {
- NV_WARN(dev, "(%u) Invalid odt value, assuming autocal: %x",
+ NV_WARN(drm, "(%u) Invalid odt value, assuming autocal: %x",
t->id, t->odt);
t->odt = 0;
}
(nv_mem_wr_lut_gddr3[e->tWR] & 0xf) << 4;
t->mr[2] = boot->mr[2];
- NV_DEBUG(dev, "(%u) MR: %08x %08x %08x", t->id,
+ NV_DEBUG(drm, "(%u) MR: %08x %08x %08x", t->id,
t->mr[0], t->mr[1], t->mr[2]);
return 0;
}
struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
+ struct nouveau_drm *drm = nouveau_drm(dev);
+
if (len < 15) {
t->drive_strength = boot->drive_strength;
t->odt = boot->odt;
}
if (e->tCL >= NV_MEM_CL_GDDR5_MAX) {
- NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
+ NV_WARN(drm, "(%u) Invalid tCL: %u", t->id, e->tCL);
return -ERANGE;
}
if (e->tWR >= NV_MEM_WR_GDDR5_MAX) {
- NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
+ NV_WARN(drm, "(%u) Invalid tWR: %u", t->id, e->tWR);
return -ERANGE;
}
if (t->odt > 3) {
- NV_WARN(dev, "(%u) Invalid odt value, assuming autocal: %x",
+ NV_WARN(drm, "(%u) Invalid odt value, assuming autocal: %x",
t->id, t->odt);
t->odt = 0;
}
t->drive_strength |
(t->odt << 2);
- NV_DEBUG(dev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[1]);
+ NV_DEBUG(drm, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[1]);
return 0;
}
nouveau_mem_timing_calc(struct drm_device *dev, u32 freq,
struct nouveau_pm_memtiming *t)
{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
+ struct nouveau_device *device = nouveau_dev(dev);
+ struct nouveau_fb *pfb = nouveau_fb(device);
+ struct nouveau_pm *pm = nouveau_pm(dev);
struct nouveau_pm_memtiming *boot = &pm->boot.timing;
struct nouveau_pm_tbl_entry *e;
u8 ver, len, *ptr, *ramcfg;
t->tCWL = boot->tCWL;
- switch (dev_priv->card_type) {
+ switch (device->card_type) {
case NV_40:
ret = nv40_mem_timing_calc(dev, freq, e, len, boot, t);
break;
break;
}
- switch (nvfb_vram_type(dev) * !ret) {
+ switch (pfb->ram.type * !ret) {
case NV_MEM_TYPE_GDDR3:
ret = nouveau_mem_gddr3_mr(dev, freq, e, len, boot, t);
break;
else
dll_off = !!(ramcfg[2] & 0x40);
- switch (nvfb_vram_type(dev)) {
+ switch (pfb->ram.type) {
case NV_MEM_TYPE_GDDR3:
t->mr[1] &= ~0x00000040;
t->mr[1] |= 0x00000040 * dll_off;
void
nouveau_mem_timing_read(struct drm_device *dev, struct nouveau_pm_memtiming *t)
{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_device *device = nouveau_dev(dev);
+ struct nouveau_fb *pfb = nouveau_fb(device);
u32 timing_base, timing_regs, mr_base;
int i;
- if (dev_priv->card_type >= 0xC0) {
+ if (device->card_type >= 0xC0) {
timing_base = 0x10f290;
mr_base = 0x10f300;
} else {
t->id = -1;
- switch (dev_priv->card_type) {
+ switch (device->card_type) {
case NV_50:
timing_regs = 9;
break;
return;
}
for(i = 0; i < timing_regs; i++)
- t->reg[i] = nv_rd32(dev, timing_base + (0x04 * i));
+ t->reg[i] = nv_rd32(device, timing_base + (0x04 * i));
t->tCWL = 0;
- if (dev_priv->card_type < NV_C0) {
- t->tCWL = ((nv_rd32(dev, 0x100228) & 0x0f000000) >> 24) + 1;
- } else if (dev_priv->card_type <= NV_D0) {
- t->tCWL = ((nv_rd32(dev, 0x10f294) & 0x00000f80) >> 7);
+ if (device->card_type < NV_C0) {
+ t->tCWL = ((nv_rd32(device, 0x100228) & 0x0f000000) >> 24) + 1;
+ } else if (device->card_type <= NV_D0) {
+ t->tCWL = ((nv_rd32(device, 0x10f294) & 0x00000f80) >> 7);
}
- t->mr[0] = nv_rd32(dev, mr_base);
- t->mr[1] = nv_rd32(dev, mr_base + 0x04);
- t->mr[2] = nv_rd32(dev, mr_base + 0x20);
- t->mr[3] = nv_rd32(dev, mr_base + 0x24);
+ t->mr[0] = nv_rd32(device, mr_base);
+ t->mr[1] = nv_rd32(device, mr_base + 0x04);
+ t->mr[2] = nv_rd32(device, mr_base + 0x20);
+ t->mr[3] = nv_rd32(device, mr_base + 0x24);
t->odt = 0;
t->drive_strength = 0;
- switch (nvfb_vram_type(dev)) {
+ switch (pfb->ram.type) {
case NV_MEM_TYPE_DDR3:
t->odt |= (t->mr[1] & 0x200) >> 7;
case NV_MEM_TYPE_DDR2:
nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
struct nouveau_pm_level *perflvl)
{
- struct drm_nouveau_private *dev_priv = exec->dev->dev_private;
+ struct nouveau_drm *drm = nouveau_drm(exec->dev);
+ struct nouveau_device *device = nouveau_dev(exec->dev);
+ struct nouveau_fb *pfb = nouveau_fb(device);
struct nouveau_pm_memtiming *info = &perflvl->timing;
u32 tMRD = 1000, tCKSRE = 0, tCKSRX = 0, tXS = 0, tDLLK = 0;
u32 mr[3] = { info->mr[0], info->mr[1], info->mr[2] };
u32 mr1_dlloff;
- switch (nvfb_vram_type(dev_priv->dev)) {
+ switch (pfb->ram.type) {
case NV_MEM_TYPE_DDR2:
tDLLK = 2000;
mr1_dlloff = 0x00000001;
mr1_dlloff = 0x00000040;
break;
default:
- NV_ERROR(exec->dev, "cannot reclock unsupported memtype\n");
+ NV_ERROR(drm, "cannot reclock unsupported memtype\n");
return -ENODEV;
}
/* fetch current MRs */
- switch (nvfb_vram_type(dev_priv->dev)) {
+ switch (pfb->ram.type) {
case NV_MEM_TYPE_GDDR3:
case NV_MEM_TYPE_DDR3:
mr[2] = exec->mrg(exec, 2);
exec->mrs (exec, 0, info->mr[0] | 0x00000000);
exec->wait(exec, tMRD);
exec->wait(exec, tDLLK);
- if (nvfb_vram_type(dev_priv->dev) == NV_MEM_TYPE_GDDR3)
+ if (pfb->ram.type == NV_MEM_TYPE_GDDR3)
exec->precharge(exec);
}
return 0;
}
-
-int
-nouveau_mem_vbios_type(struct drm_device *dev)
-{
- struct bit_entry M;
- u8 ramcfg = (nv_rd32(dev, 0x101000) & 0x0000003c) >> 2;
- if (!bit_table(dev, 'M', &M) || M.version != 2 || M.length < 5) {
- u8 *table = ROMPTR(dev, M.data[3]);
- if (table && table[0] == 0x10 && ramcfg < table[3]) {
- u8 *entry = table + table[1] + (ramcfg * table[2]);
- switch (entry[0] & 0x0f) {
- case 0: return NV_MEM_TYPE_DDR2;
- case 1: return NV_MEM_TYPE_DDR3;
- case 2: return NV_MEM_TYPE_GDDR3;
- case 3: return NV_MEM_TYPE_GDDR5;
- default:
- break;
- }
-
- }
- }
- return NV_MEM_TYPE_UNKNOWN;
-}
projects / ~andy / linux / blobdiff