drm/i915: Force sync command ordering (Gen6+)

[~andy/linux] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b080cc82400153a68aed7cca1f3319de361a1f93..3ae2c7c00ef28767d6267f5c548498dd2623a021 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -442,6 +442,7 @@
 #define   INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
                                        will not assert AGPBUSY# and will only
                                        be delivered when out of C3. */
+#define   INSTPM_FORCE_ORDERING                                (1<<7) /* GEN6+ */
 #define ACTHD          0x020c8
 #define FW_BLC         0x020d8
 #define FW_BLC2                0x020dc
@@ -2321,6 +2322,7 @@
 #define   PIPECONF_PROGRESSIVE (0 << 21)
 #define   PIPECONF_INTERLACE_W_FIELD_INDICATION        (6 << 21)
 #define   PIPECONF_INTERLACE_FIELD_0_ONLY              (7 << 21)
+#define   PIPECONF_INTERLACE_MASK      (7 << 21)
 #define   PIPECONF_CXSR_DOWNCLOCK      (1<<16)
 #define   PIPECONF_BPP_MASK    (0x000000e0)
 #define   PIPECONF_BPP_8       (0<<5)
@@ -3303,10 +3305,10 @@
 /* or SDVOB */
 #define HDMIB   0xe1140
 #define  PORT_ENABLE    (1 << 31)
-#define  TRANSCODER_A   (0)
-#define  TRANSCODER_B   (1 << 30)
-#define  TRANSCODER(pipe)      ((pipe) << 30)
-#define  TRANSCODER_MASK   (1 << 30)
+#define  TRANSCODER(pipe)       ((pipe) << 30)
+#define  TRANSCODER_CPT(pipe)   ((pipe) << 29)
+#define  TRANSCODER_MASK        (1 << 30)
+#define  TRANSCODER_MASK_CPT    (3 << 29)
 #define  COLOR_FORMAT_8bpc      (0)
 #define  COLOR_FORMAT_12bpc     (3 << 26)
 #define  SDVOB_HOTPLUG_ENABLE   (1 << 23)
@@ -3447,8 +3449,30 @@
 #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B   (0x38<<22)
 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB       (0x3f<<22)
 
+/* IVB */
+#define EDP_LINK_TRAIN_400MV_0DB_IVB           (0x24 <<22)
+#define EDP_LINK_TRAIN_400MV_3_5DB_IVB         (0x2a <<22)
+#define EDP_LINK_TRAIN_400MV_6DB_IVB           (0x2f <<22)
+#define EDP_LINK_TRAIN_600MV_0DB_IVB           (0x30 <<22)
+#define EDP_LINK_TRAIN_600MV_3_5DB_IVB         (0x36 <<22)
+#define EDP_LINK_TRAIN_800MV_0DB_IVB           (0x38 <<22)
+#define EDP_LINK_TRAIN_800MV_3_5DB_IVB         (0x33 <<22)
+
+/* legacy values */
+#define EDP_LINK_TRAIN_500MV_0DB_IVB           (0x00 <<22)
+#define EDP_LINK_TRAIN_1000MV_0DB_IVB          (0x20 <<22)
+#define EDP_LINK_TRAIN_500MV_3_5DB_IVB         (0x02 <<22)
+#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB                (0x22 <<22)
+#define EDP_LINK_TRAIN_1000MV_6DB_IVB          (0x23 <<22)
+
+#define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB       (0x3f<<22)
+
 #define  FORCEWAKE                             0xA18C
 #define  FORCEWAKE_ACK                         0x130090
+#define  FORCEWAKE_MT                          0xa188 /* multi-threaded */
+#define  FORCEWAKE_MT_ACK                      0x130040
+#define  ECOBUS                                        0xa180
+#define    FORCEWAKE_MT_ENABLE                 (1<<5)
 
 #define  GT_FIFO_FREE_ENTRIES                  0x120008
 #define    GT_FIFO_NUM_RESERVED_ENTRIES                20
@@ -3547,17 +3571,17 @@
 #define G4X_ELD_ACK                    (1 << 4)
 #define G4X_HDMIW_HDMIEDID             0x6210C
 
-#define GEN5_HDMIW_HDMIEDID_A          0xE2050
-#define GEN5_AUD_CNTL_ST_A             0xE20B4
-#define GEN5_ELD_BUFFER_SIZE           (0x1f << 10)
-#define GEN5_ELD_ADDRESS               (0x1f << 5)
-#define GEN5_ELD_ACK                   (1 << 4)
-#define GEN5_AUD_CNTL_ST2              0xE20C0
-#define GEN5_ELD_VALIDB                        (1 << 0)
-#define GEN5_CP_READYB                 (1 << 1)
-
-#define GEN7_HDMIW_HDMIEDID_A          0xE5050
-#define GEN7_AUD_CNTRL_ST_A            0xE50B4
-#define GEN7_AUD_CNTRL_ST2             0xE50C0
+#define IBX_HDMIW_HDMIEDID_A           0xE2050
+#define IBX_AUD_CNTL_ST_A              0xE20B4
+#define IBX_ELD_BUFFER_SIZE            (0x1f << 10)
+#define IBX_ELD_ADDRESS                        (0x1f << 5)
+#define IBX_ELD_ACK                    (1 << 4)
+#define IBX_AUD_CNTL_ST2               0xE20C0
+#define IBX_ELD_VALIDB                 (1 << 0)
+#define IBX_CP_READYB                  (1 << 1)
+
+#define CPT_HDMIW_HDMIEDID_A           0xE5050
+#define CPT_AUD_CNTL_ST_A              0xE50B4
+#define CPT_AUD_CNTRL_ST2              0xE50C0
 
 #endif /* _I915_REG_H_ */