[media] solo6x10: reimplement SAA712x setup routine

[~andy/linux] / drivers / gpio / gpio-sch.c

diff --git a/drivers/gpio/gpio-sch.c b/drivers/gpio/gpio-sch.c
index edae963f4625ed146621f12fb04800c434e40d79..1e4de16ceb419e148c9c233aef0746143530efca 100644 (file)
--- a/drivers/gpio/gpio-sch.c
+++ b/drivers/gpio/gpio-sch.c
@@ -125,13 +125,17 @@ static int sch_gpio_resume_direction_in(struct gpio_chip *gc,
                                        unsigned gpio_num)
 {
        u8 curr_dirs;
+       unsigned short offset, bit;
 
        spin_lock(&gpio_lock);
 
-       curr_dirs = inb(gpio_ba + RGIO);
+       offset = RGIO + gpio_num / 8;
+       bit = gpio_num % 8;
+
+       curr_dirs = inb(gpio_ba + offset);
 
-       if (!(curr_dirs & (1 << gpio_num)))
-               outb(curr_dirs | (1 << gpio_num) , gpio_ba + RGIO);
+       if (!(curr_dirs & (1 << bit)))
+               outb(curr_dirs | (1 << bit), gpio_ba + offset);
 
        spin_unlock(&gpio_lock);
        return 0;
@@ -139,22 +143,31 @@ static int sch_gpio_resume_direction_in(struct gpio_chip *gc,
 
 static int sch_gpio_resume_get(struct gpio_chip *gc, unsigned gpio_num)
 {
-       return !!(inb(gpio_ba + RGLV) & (1 << gpio_num));
+       unsigned short offset, bit;
+
+       offset = RGLV + gpio_num / 8;
+       bit = gpio_num % 8;
+
+       return !!(inb(gpio_ba + offset) & (1 << bit));
 }
 
 static void sch_gpio_resume_set(struct gpio_chip *gc,
                                unsigned gpio_num, int val)
 {
        u8 curr_vals;
+       unsigned short offset, bit;
 
        spin_lock(&gpio_lock);
 
-       curr_vals = inb(gpio_ba + RGLV);
+       offset = RGLV + gpio_num / 8;
+       bit = gpio_num % 8;
+
+       curr_vals = inb(gpio_ba + offset);
 
        if (val)
-               outb(curr_vals | (1 << gpio_num), gpio_ba + RGLV);
+               outb(curr_vals | (1 << bit), gpio_ba + offset);
        else
-               outb((curr_vals & ~(1 << gpio_num)), gpio_ba + RGLV);
+               outb((curr_vals & ~(1 << bit)), gpio_ba + offset);
 
        spin_unlock(&gpio_lock);
 }
@@ -163,14 +176,18 @@ static int sch_gpio_resume_direction_out(struct gpio_chip *gc,
                                        unsigned gpio_num, int val)
 {
        u8 curr_dirs;
+       unsigned short offset, bit;
 
        sch_gpio_resume_set(gc, gpio_num, val);
 
+       offset = RGIO + gpio_num / 8;
+       bit = gpio_num % 8;
+
        spin_lock(&gpio_lock);
 
-       curr_dirs = inb(gpio_ba + RGIO);
-       if (curr_dirs & (1 << gpio_num))
-               outb(curr_dirs & ~(1 << gpio_num), gpio_ba + RGIO);
+       curr_dirs = inb(gpio_ba + offset);
+       if (curr_dirs & (1 << bit))
+               outb(curr_dirs & ~(1 << bit), gpio_ba + offset);
 
        spin_unlock(&gpio_lock);
        return 0;
@@ -204,45 +221,41 @@ static int sch_gpio_probe(struct platform_device *pdev)
        gpio_ba = res->start;
 
        switch (id) {
-               case PCI_DEVICE_ID_INTEL_SCH_LPC:
-                       sch_gpio_core.base = 0;
-                       sch_gpio_core.ngpio = 10;
-
-                       sch_gpio_resume.base = 10;
-                       sch_gpio_resume.ngpio = 4;
-
-                       /*
-                        * GPIO[6:0] enabled by default
-                        * GPIO7 is configured by the CMC as SLPIOVR
-                        * Enable GPIO[9:8] core powered gpios explicitly
-                        */
-                       outb(0x3, gpio_ba + CGEN + 1);
-                       /*
-                        * SUS_GPIO[2:0] enabled by default
-                        * Enable SUS_GPIO3 resume powered gpio explicitly
-                        */
-                       outb(0x8, gpio_ba + RGEN);
-                       break;
-
-               case PCI_DEVICE_ID_INTEL_ITC_LPC:
-                       sch_gpio_core.base = 0;
-                       sch_gpio_core.ngpio = 5;
-
-                       sch_gpio_resume.base = 5;
-                       sch_gpio_resume.ngpio = 9;
-                       break;
-
-               case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
-                       sch_gpio_core.base = 0;
-                       sch_gpio_core.ngpio = 21;
-
-                       sch_gpio_resume.base = 21;
-                       sch_gpio_resume.ngpio = 9;
-                       break;
-
-               default:
-                       err = -ENODEV;
-                       goto err_sch_gpio_core;
+       case PCI_DEVICE_ID_INTEL_SCH_LPC:
+               sch_gpio_core.base = 0;
+               sch_gpio_core.ngpio = 10;
+               sch_gpio_resume.base = 10;
+               sch_gpio_resume.ngpio = 4;
+               /*
+                * GPIO[6:0] enabled by default
+                * GPIO7 is configured by the CMC as SLPIOVR
+                * Enable GPIO[9:8] core powered gpios explicitly
+                */
+               outb(0x3, gpio_ba + CGEN + 1);
+               /*
+                * SUS_GPIO[2:0] enabled by default
+                * Enable SUS_GPIO3 resume powered gpio explicitly
+                */
+               outb(0x8, gpio_ba + RGEN);
+               break;
+
+       case PCI_DEVICE_ID_INTEL_ITC_LPC:
+               sch_gpio_core.base = 0;
+               sch_gpio_core.ngpio = 5;
+               sch_gpio_resume.base = 5;
+               sch_gpio_resume.ngpio = 9;
+               break;
+
+       case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
+               sch_gpio_core.base = 0;
+               sch_gpio_core.ngpio = 21;
+               sch_gpio_resume.base = 21;
+               sch_gpio_resume.ngpio = 9;
+               break;
+
+       default:
+               err = -ENODEV;
+               goto err_sch_gpio_core;
        }
 
        sch_gpio_core.dev = &pdev->dev;