Merge branch 'linux-next' of git://cavan.codon.org.uk/platform-drivers-x86

[~andy/linux] / drivers / crypto / caam / regs.h

diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index e9f7a70cdd5efa443a9bd4d3d928d0a562002a0d..3223fc6d647cd55c0367b5ee1f6b003bc8029080 100644 (file)
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -117,6 +117,12 @@ struct jr_outentry {
 #define CHA_NUM_DECONUM_SHIFT  56
 #define CHA_NUM_DECONUM_MASK   (0xfull << CHA_NUM_DECONUM_SHIFT)
 
+struct sec_vid {
+       u16 ip_id;
+       u8 maj_rev;
+       u8 min_rev;
+};
+
 struct caam_perfmon {
        /* Performance Monitor Registers                        f00-f9f */
        u64 req_dequeued;       /* PC_REQ_DEQ - Dequeued Requests            */
@@ -167,7 +173,7 @@ struct partid {
        u32 pidr;       /* partition ID, DECO */
 };
 
-/* RNG test mode (replicated twice in some configurations) */
+/* RNGB test mode (replicated twice in some configurations) */
 /* Padded out to 0x100 */
 struct rngtst {
        u32 mode;               /* RTSTMODEx - Test mode */
@@ -200,6 +206,31 @@ struct rngtst {
        u32 rsvd14[15];
 };
 
+/* RNG4 TRNG test registers */
+struct rng4tst {
+#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
+       u32 rtmctl;             /* misc. control register */
+       u32 rtscmisc;           /* statistical check misc. register */
+       u32 rtpkrrng;           /* poker range register */
+       union {
+               u32 rtpkrmax;   /* PRGM=1: poker max. limit register */
+               u32 rtpkrsq;    /* PRGM=0: poker square calc. result register */
+       };
+#define RTSDCTL_ENT_DLY_SHIFT 16
+#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
+       u32 rtsdctl;            /* seed control register */
+       union {
+               u32 rtsblim;    /* PRGM=1: sparse bit limit register */
+               u32 rttotsam;   /* PRGM=0: total samples register */
+       };
+       u32 rtfrqmin;           /* frequency count min. limit register */
+       union {
+               u32 rtfrqmax;   /* PRGM=1: freq. count max. limit register */
+               u32 rtfrqcnt;   /* PRGM=0: freq. count register */
+       };
+       u32 rsvd1[56];
+};
+
 /*
  * caam_ctrl - basic core configuration
  * starts base + 0x0000 padded out to 0x1000
@@ -249,7 +280,10 @@ struct caam_ctrl {
 
        /* RNG Test/Verification/Debug Access                   600-7ff */
        /* (Useful in Test/Debug modes only...)                         */
-       struct rngtst rtst[2];
+       union {
+               struct rngtst rtst[2];
+               struct rng4tst r4tst[2];
+       };
 
        u32 rsvd9[448];