Merge tag 'ext4_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso...

[~andy/linux] / drivers / clocksource / sun4i_timer.c

diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c
index 3217adc7457c8d3fd302797ad3e4b6ee590e0faa..8ead0258740a82dc71807bd323f5b1eb9d1535a5 100644 (file)
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -30,11 +30,15 @@
 #define TIMER_CTL_REG(val)     (0x10 * val + 0x10)
 #define TIMER_CTL_ENABLE               BIT(0)
 #define TIMER_CTL_RELOAD               BIT(1)
+#define TIMER_CTL_CLK_SRC(val)         (((val) & 0x3) << 2)
+#define TIMER_CTL_CLK_SRC_OSC24M               (1)
+#define TIMER_CTL_CLK_PRES(val)                (((val) & 0x7) << 4)
 #define TIMER_CTL_ONESHOT              BIT(7)
 #define TIMER_INTVAL_REG(val)  (0x10 * (val) + 0x14)
 #define TIMER_CNTVAL_REG(val)  (0x10 * (val) + 0x18)
 
 static void __iomem *timer_base;
+static u32 ticks_per_jiffy;
 
 /*
  * When we disable a timer, we need to wait at least for 2 cycles of
@@ -71,7 +75,8 @@ static void sun4i_clkevt_time_start(u8 timer, bool periodic)
        else
                val |= TIMER_CTL_ONESHOT;
 
-       writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
+       writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
+              timer_base + TIMER_CTL_REG(timer));
 }
 
 static void sun4i_clkevt_mode(enum clock_event_mode mode,
@@ -80,6 +85,7 @@ static void sun4i_clkevt_mode(enum clock_event_mode mode,
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
                sun4i_clkevt_time_stop(0);
+               sun4i_clkevt_time_setup(0, ticks_per_jiffy);
                sun4i_clkevt_time_start(0, true);
                break;
        case CLOCK_EVT_MODE_ONESHOT:
@@ -166,18 +172,10 @@ static void __init sun4i_timer_init(struct device_node *node)
        clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
                              rate, 300, 32, clocksource_mmio_readl_down);
 
-       writel(rate / HZ, timer_base + TIMER_INTVAL_REG(0));
+       ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
 
-       /* set clock source to HOSC, 16 pre-division */
-       val = readl(timer_base + TIMER_CTL_REG(0));
-       val &= ~(0x07 << 4);
-       val &= ~(0x03 << 2);
-       val |= (4 << 4) | (1 << 2);
-       writel(val, timer_base + TIMER_CTL_REG(0));
-
-       /* set mode to auto reload */
-       val = readl(timer_base + TIMER_CTL_REG(0));
-       writel(val | TIMER_CTL_RELOAD, timer_base + TIMER_CTL_REG(0));
+       writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
+              timer_base + TIMER_CTL_REG(0));
 
        ret = setup_irq(irq, &sun4i_timer_irq);
        if (ret)