Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux

[~andy/linux] / drivers / clk / zynq / clkc.c

diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index e05c9e3f1385d3f45bba676e5ae77244f4c44d50..cc40fe64f2dc681c44205151537a71222e8d4990 100644 (file)
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -71,6 +71,7 @@ static DEFINE_SPINLOCK(armpll_lock);
 static DEFINE_SPINLOCK(ddrpll_lock);
 static DEFINE_SPINLOCK(iopll_lock);
 static DEFINE_SPINLOCK(armclk_lock);
+static DEFINE_SPINLOCK(swdtclk_lock);
 static DEFINE_SPINLOCK(ddrclk_lock);
 static DEFINE_SPINLOCK(dciclk_lock);
 static DEFINE_SPINLOCK(gem0clk_lock);
@@ -296,7 +297,7 @@ static void __init zynq_clk_setup(struct device_node *np)
        clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
                        swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
                        CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
-                       &gem0clk_lock);
+                       &swdtclk_lock);
 
        /* DDR clocks */
        clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
@@ -369,7 +370,8 @@ static void __init zynq_clk_setup(struct device_node *np)
                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
                        &gem0clk_lock);
        clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
-                       CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0,
+                       CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+                       SLCR_GEM0_CLK_CTRL, 6, 1, 0,
                        &gem0clk_lock);
        clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
                        "gem0_emio_mux", CLK_SET_RATE_PARENT,
@@ -393,7 +395,8 @@ static void __init zynq_clk_setup(struct device_node *np)
                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
                        &gem1clk_lock);
        clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
-                       CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0,
+                       CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+                       SLCR_GEM1_CLK_CTRL, 6, 1, 0,
                        &gem1clk_lock);
        clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
                        "gem1_emio_mux", CLK_SET_RATE_PARENT,