Merge commit 'v3.5-rc3' into x86/debug

[~andy/linux] / arch / x86 / kernel / cpu / perf_event_intel.c

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 187c294bc6583424e8613df62a883740ab8fca1a..5073bf1c1d86903ccc715e86c52dcfeb7b456298 100644 (file)
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -5,6 +5,8 @@
  * among events on a single PMU.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/stddef.h>
 #include <linux/types.h>
 #include <linux/init.h>
@@ -1000,7 +1002,7 @@ static void intel_pmu_reset(void)
 
        local_irq_save(flags);
 
-       printk("clearing PMU state on CPU#%d\n", smp_processor_id());
+       pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
 
        for (idx = 0; idx < x86_pmu.num_counters; idx++) {
                checking_wrmsrl(x86_pmu_config_addr(idx), 0ull);
@@ -1707,14 +1709,14 @@ static __init void intel_clovertown_quirk(void)
         * But taken together it might just make sense to not enable PEBS on
         * these chips.
         */
-       printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
+       pr_warn("PEBS disabled due to CPU errata\n");
        x86_pmu.pebs = 0;
        x86_pmu.pebs_constraints = NULL;
 }
 
 static __init void intel_sandybridge_quirk(void)
 {
-       printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
+       pr_warn("PEBS disabled due to CPU errata\n");
        x86_pmu.pebs = 0;
        x86_pmu.pebs_constraints = NULL;
 }
@@ -1736,8 +1738,8 @@ static __init void intel_arch_events_quirk(void)
        /* disable event that reported as not presend by cpuid */
        for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
                intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
-               printk(KERN_WARNING "CPUID marked event: \'%s\' unavailable\n",
-                               intel_arch_events_map[bit].name);
+               pr_warn("CPUID marked event: \'%s\' unavailable\n",
+                       intel_arch_events_map[bit].name);
        }
 }
 
@@ -1756,7 +1758,7 @@ static __init void intel_nehalem_quirk(void)
                intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
                ebx.split.no_branch_misses_retired = 0;
                x86_pmu.events_maskl = ebx.full;
-               printk(KERN_INFO "CPU erratum AAJ80 worked around\n");
+               pr_info("CPU erratum AAJ80 worked around\n");
        }
 }