sh: Mass ctrl_in/outX to __raw_read/writeX conversion.

[~andy/linux] / arch / sh / kernel / cpu / sh4a / setup-sh7785.c

diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index f685b9b219997afec1021bb1b03055c5e84a2ecb..23448d8c6711d9c6c16f6290438afea72b76f7cf 100644 (file)
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -541,17 +541,17 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
 void __init plat_irq_setup(void)
 {
        /* disable IRQ3-0 + IRQ7-4 */
-       ctrl_outl(0xff000000, INTC_INTMSK0);
+       __raw_writel(0xff000000, INTC_INTMSK0);
 
        /* disable IRL3-0 + IRL7-4 */
-       ctrl_outl(0xc0000000, INTC_INTMSK1);
-       ctrl_outl(0xfffefffe, INTC_INTMSK2);
+       __raw_writel(0xc0000000, INTC_INTMSK1);
+       __raw_writel(0xfffefffe, INTC_INTMSK2);
 
        /* select IRL mode for IRL3-0 + IRL7-4 */
-       ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+       __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
        /* disable holding function, ie enable "SH-4 Mode" */
-       ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+       __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 
        register_intc_controller(&intc_desc);
 }
@@ -561,32 +561,32 @@ void __init plat_irq_setup_pins(int mode)
        switch (mode) {
        case IRQ_MODE_IRQ7654:
                /* select IRQ mode for IRL7-4 */
-               ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
+               __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
                register_intc_controller(&intc_desc_irq4567);
                break;
        case IRQ_MODE_IRQ3210:
                /* select IRQ mode for IRL3-0 */
-               ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
+               __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
                register_intc_controller(&intc_desc_irq0123);
                break;
        case IRQ_MODE_IRL7654:
                /* enable IRL7-4 but don't provide any masking */
-               ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-               ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+               __raw_writel(0x40000000, INTC_INTMSKCLR1);
+               __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                break;
        case IRQ_MODE_IRL3210:
                /* enable IRL0-3 but don't provide any masking */
-               ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-               ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+               __raw_writel(0x80000000, INTC_INTMSKCLR1);
+               __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                break;
        case IRQ_MODE_IRL7654_MASK:
                /* enable IRL7-4 and mask using cpu intc controller */
-               ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+               __raw_writel(0x40000000, INTC_INTMSKCLR1);
                register_intc_controller(&intc_desc_irl4567);
                break;
        case IRQ_MODE_IRL3210_MASK:
                /* enable IRL0-3 and mask using cpu intc controller */
-               ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+               __raw_writel(0x80000000, INTC_INTMSKCLR1);
                register_intc_controller(&intc_desc_irl0123);
                break;
        default: