Merge branch 'next' of git://git.kernel.org/pub/scm/virt/kvm/kvm

[~andy/linux] / arch / powerpc / include / asm / reg_booke.h

diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 8a97aa7289d36b155a1e01df4211a261a7a110e8..2d916c4982c5136a71b10f917606757aa743792f 100644 (file)
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -56,18 +56,30 @@
 #define SPRN_SPRG7W    0x117   /* Special Purpose Register General 7 Write */
 #define SPRN_EPCR      0x133   /* Embedded Processor Control Register */
 #define SPRN_DBCR2     0x136   /* Debug Control Register 2 */
+#define SPRN_MSRP      0x137   /* MSR Protect Register */
 #define SPRN_IAC3      0x13A   /* Instruction Address Compare 3 */
 #define SPRN_IAC4      0x13B   /* Instruction Address Compare 4 */
 #define SPRN_DVC1      0x13E   /* Data Value Compare Register 1 */
 #define SPRN_DVC2      0x13F   /* Data Value Compare Register 2 */
+#define SPRN_LPID      0x152   /* Logical Partition ID */
 #define SPRN_MAS8      0x155   /* MMU Assist Register 8 */
 #define SPRN_TLB0PS    0x158   /* TLB 0 Page Size Register */
 #define SPRN_TLB1PS    0x159   /* TLB 1 Page Size Register */
 #define SPRN_MAS5_MAS6 0x15c   /* MMU Assist Register 5 || 6 */
 #define SPRN_MAS8_MAS1 0x15d   /* MMU Assist Register 8 || 1 */
 #define SPRN_EPTCFG    0x15e   /* Embedded Page Table Config */
+#define SPRN_GSPRG0    0x170   /* Guest SPRG0 */
+#define SPRN_GSPRG1    0x171   /* Guest SPRG1 */
+#define SPRN_GSPRG2    0x172   /* Guest SPRG2 */
+#define SPRN_GSPRG3    0x173   /* Guest SPRG3 */
 #define SPRN_MAS7_MAS3 0x174   /* MMU Assist Register 7 || 3 */
 #define SPRN_MAS0_MAS1 0x175   /* MMU Assist Register 0 || 1 */
+#define SPRN_GSRR0     0x17A   /* Guest SRR0 */
+#define SPRN_GSRR1     0x17B   /* Guest SRR1 */
+#define SPRN_GEPR      0x17C   /* Guest EPR */
+#define SPRN_GDEAR     0x17D   /* Guest DEAR */
+#define SPRN_GPIR      0x17E   /* Guest PIR */
+#define SPRN_GESR      0x17F   /* Guest Exception Syndrome Register */
 #define SPRN_IVOR0     0x190   /* Interrupt Vector Offset Register 0 */
 #define SPRN_IVOR1     0x191   /* Interrupt Vector Offset Register 1 */
 #define SPRN_IVOR2     0x192   /* Interrupt Vector Offset Register 2 */
@@ -88,6 +100,13 @@
 #define SPRN_IVOR39    0x1B1   /* Interrupt Vector Offset Register 39 */
 #define SPRN_IVOR40    0x1B2   /* Interrupt Vector Offset Register 40 */
 #define SPRN_IVOR41    0x1B3   /* Interrupt Vector Offset Register 41 */
+#define SPRN_GIVOR2    0x1B8   /* Guest IVOR2 */
+#define SPRN_GIVOR3    0x1B9   /* Guest IVOR3 */
+#define SPRN_GIVOR4    0x1BA   /* Guest IVOR4 */
+#define SPRN_GIVOR8    0x1BB   /* Guest IVOR8 */
+#define SPRN_GIVOR13   0x1BC   /* Guest IVOR13 */
+#define SPRN_GIVOR14   0x1BD   /* Guest IVOR14 */
+#define SPRN_GIVPR     0x1BF   /* Guest IVPR */
 #define SPRN_SPEFSCR   0x200   /* SPE & Embedded FP Status & Control */
 #define SPRN_BBEAR     0x201   /* Branch Buffer Entry Address Register */
 #define SPRN_BBTAR     0x202   /* Branch Buffer Target Address Register */
@@ -240,6 +259,10 @@
 #define MCSR_LDG       0x00002000UL /* Guarded Load */
 #define MCSR_TLBSYNC   0x00000002UL /* Multiple tlbsyncs detected */
 #define MCSR_BSL2_ERR  0x00000001UL /* Backside L2 cache error */
+
+#define MSRP_UCLEP     0x04000000 /* Protect MSR[UCLE] */
+#define MSRP_DEP       0x00000200 /* Protect MSR[DE] */
+#define MSRP_PMMP      0x00000004 /* Protect MSR[PMM] */
 #endif
 
 #ifdef CONFIG_E200
@@ -594,6 +617,17 @@
 #define SPRN_EPCR_DMIUH                0x00400000      /* Disable MAS Interrupt updates
                                                 * for hypervisor */
 
+/* Bit definitions for EPLC/EPSC */
+#define EPC_EPR                0x80000000 /* 1 = user, 0 = kernel */
+#define EPC_EPR_SHIFT  31
+#define EPC_EAS                0x40000000 /* Address Space */
+#define EPC_EAS_SHIFT  30
+#define EPC_EGS                0x20000000 /* 1 = guest, 0 = hypervisor */
+#define EPC_EGS_SHIFT  29
+#define EPC_ELPID      0x00ff0000
+#define EPC_ELPID_SHIFT        16
+#define EPC_EPID       0x00003fff
+#define EPC_EPID_SHIFT 0
 
 /*
  * The IBM-403 is an even more odd special case, as it is much