]> Pileus Git - ~andy/linux/blobdiff - arch/mips/kernel/traps.c
Merge branch 'exynos/pwm-clocksource' into late/multiplatform
[~andy/linux] / arch / mips / kernel / traps.c
index a200b5bdbb870c0d5b7121503f9c1032f62c956a..c3abb88170fc01a6a4cfeeda10bd7c3f144707ec 100644 (file)
@@ -1571,7 +1571,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
 #ifdef CONFIG_64BIT
        status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
 #endif
-       if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
+       if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
                status_set |= ST0_XX;
        if (cpu_has_dsp)
                status_set |= ST0_MX;