]> Pileus Git - ~andy/linux/blobdiff - arch/i386/kernel/cpu/intel.c
PCI: Change all drivers to use pci_device->revision
[~andy/linux] / arch / i386 / kernel / cpu / intel.c
index 5a2e270924b13727f1411eb11dea7a0f114e7cce..dc4e08147b1f14b90541b94419cd129ab58ac9a7 100644 (file)
@@ -107,7 +107,7 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
         * Note that the workaround only should be initialized once...
         */
        c->f00f_bug = 0;
-       if ( c->x86 == 5 ) {
+       if (!paravirt_enabled() && c->x86 == 5) {
                static int f00f_workaround_enabled = 0;
 
                c->f00f_bug = 1;
@@ -188,17 +188,27 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
        }
 #endif
 
-       if (c->x86 == 15)
+       if (c->x86 == 15) {
                set_bit(X86_FEATURE_P4, c->x86_capability);
+               set_bit(X86_FEATURE_SYNC_RDTSC, c->x86_capability);
+       }
        if (c->x86 == 6) 
                set_bit(X86_FEATURE_P3, c->x86_capability);
        if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
                (c->x86 == 0x6 && c->x86_model >= 0x0e))
                set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
-}
 
+       if (cpu_has_ds) {
+               unsigned int l1;
+               rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
+               if (!(l1 & (1<<11)))
+                       set_bit(X86_FEATURE_BTS, c->x86_capability);
+               if (!(l1 & (1<<12)))
+                       set_bit(X86_FEATURE_PEBS, c->x86_capability);
+       }
+}
 
-static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
+static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
 {
        /* Intel PIII Tualatin. This comes in two flavours.
         * One has 256kb of cache, the other 512. We have no way
@@ -263,7 +273,6 @@ static struct cpu_dev intel_cpu_dev __cpuinitdata = {
                },
        },
        .c_init         = init_intel,
-       .c_identify     = generic_identify,
        .c_size_cache   = intel_size_cache,
 };