]> Pileus Git - ~andy/linux/blobdiff - arch/arm/mach-ux500/devices-db8500.c
Merge tag 'regmap-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[~andy/linux] / arch / arm / mach-ux500 / devices-db8500.c
index ddbdcda8306ac9a307d91afe05135caa77018e60..516a6f57d1598b2379c623c24cc88362389eea7f 100644 (file)
@@ -42,128 +42,7 @@ static struct resource dma40_resources[] = {
        }
 };
 
-/* Default configuration for physcial memcpy */
-struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
-       .mode = STEDMA40_MODE_PHYSICAL,
-       .dir = STEDMA40_MEM_TO_MEM,
-
-       .src_info.data_width = STEDMA40_BYTE_WIDTH,
-       .src_info.psize = STEDMA40_PSIZE_PHY_1,
-       .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-
-       .dst_info.data_width = STEDMA40_BYTE_WIDTH,
-       .dst_info.psize = STEDMA40_PSIZE_PHY_1,
-       .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-};
-/* Default configuration for logical memcpy */
-struct stedma40_chan_cfg dma40_memcpy_conf_log = {
-       .dir = STEDMA40_MEM_TO_MEM,
-
-       .src_info.data_width = STEDMA40_BYTE_WIDTH,
-       .src_info.psize = STEDMA40_PSIZE_LOG_1,
-       .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-
-       .dst_info.data_width = STEDMA40_BYTE_WIDTH,
-       .dst_info.psize = STEDMA40_PSIZE_LOG_1,
-       .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-};
-
-/*
- * Mapping between destination event lines and physical device address.
- * The event line is tied to a device and therefore the address is constant.
- * When the address comes from a primecell it will be configured in runtime
- * and we set the address to -1 as a placeholder.
- */
-static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
-       /* MUSB - these will be runtime-reconfigured */
-       [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
-       [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
-       [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
-       [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
-       [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
-       [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
-       [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
-       [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
-       /* PrimeCells - run-time configured */
-       [DB8500_DMA_DEV0_SPI0_TX] = -1,
-       [DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
-       [DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
-       [DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
-       [DB8500_DMA_DEV8_SSP0_TX] = -1,
-       [DB8500_DMA_DEV9_SSP1_TX] = -1,
-       [DB8500_DMA_DEV11_UART2_TX] = -1,
-       [DB8500_DMA_DEV12_UART1_TX] = -1,
-       [DB8500_DMA_DEV13_UART0_TX] = -1,
-       [DB8500_DMA_DEV28_SD_MM2_TX] = -1,
-       [DB8500_DMA_DEV29_SD_MM0_TX] = -1,
-       [DB8500_DMA_DEV32_SD_MM1_TX] = -1,
-       [DB8500_DMA_DEV33_SPI2_TX] = -1,
-       [DB8500_DMA_DEV35_SPI1_TX] = -1,
-       [DB8500_DMA_DEV40_SPI3_TX] = -1,
-       [DB8500_DMA_DEV41_SD_MM3_TX] = -1,
-       [DB8500_DMA_DEV42_SD_MM4_TX] = -1,
-       [DB8500_DMA_DEV43_SD_MM5_TX] = -1,
-       [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-       [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
-       [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-       [DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
-       [DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
-};
-
-/* Mapping between source event lines and physical device address */
-static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
-       /* MUSB - these will be runtime-reconfigured */
-       [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
-       [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
-       [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
-       [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
-       [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
-       [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
-       [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
-       [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
-       /* PrimeCells */
-       [DB8500_DMA_DEV0_SPI0_RX] = -1,
-       [DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
-       [DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
-       [DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
-       [DB8500_DMA_DEV8_SSP0_RX] = -1,
-       [DB8500_DMA_DEV9_SSP1_RX] = -1,
-       [DB8500_DMA_DEV11_UART2_RX] = -1,
-       [DB8500_DMA_DEV12_UART1_RX] = -1,
-       [DB8500_DMA_DEV13_UART0_RX] = -1,
-       [DB8500_DMA_DEV28_SD_MM2_RX] = -1,
-       [DB8500_DMA_DEV29_SD_MM0_RX] = -1,
-       [DB8500_DMA_DEV32_SD_MM1_RX] = -1,
-       [DB8500_DMA_DEV33_SPI2_RX] = -1,
-       [DB8500_DMA_DEV35_SPI1_RX] = -1,
-       [DB8500_DMA_DEV40_SPI3_RX] = -1,
-       [DB8500_DMA_DEV41_SD_MM3_RX] = -1,
-       [DB8500_DMA_DEV42_SD_MM4_RX] = -1,
-       [DB8500_DMA_DEV43_SD_MM5_RX] = -1,
-       [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-       [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
-       [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-       [DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
-};
-
-/* Reserved event lines for memcpy only */
-static int dma40_memcpy_event[] = {
-       DB8500_DMA_MEMCPY_TX_0,
-       DB8500_DMA_MEMCPY_TX_1,
-       DB8500_DMA_MEMCPY_TX_2,
-       DB8500_DMA_MEMCPY_TX_3,
-       DB8500_DMA_MEMCPY_TX_4,
-       DB8500_DMA_MEMCPY_TX_5,
-};
-
-static struct stedma40_platform_data dma40_plat_data = {
-       .dev_len = DB8500_DMA_NR_DEV,
-       .dev_rx = dma40_rx_map,
-       .dev_tx = dma40_tx_map,
-       .memcpy = dma40_memcpy_event,
-       .memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
-       .memcpy_conf_phy = &dma40_memcpy_conf_phy,
-       .memcpy_conf_log = &dma40_memcpy_conf_log,
+struct stedma40_platform_data dma40_plat_data = {
        .disabled_channels = {-1},
 };