Merge branch 'for-linus' of git://github.com/cmetcalf-tilera/linux-tile

[~andy/linux] / arch / arm / mach-ux500 / cache-l2x0.c

diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 9d09e4d013b9e8356fbf6416a7417363734a7127..122ddde00ba78deabf82db84273705598ffda34e 100644 (file)
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -50,7 +50,27 @@ static void ux500_l2x0_inv_all(void)
        ux500_cache_sync();
 }
 
-static int ux500_l2x0_init(void)
+static int __init ux500_l2x0_unlock(void)
+{
+       int i;
+
+       /*
+        * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
+        * apparently locks both caches before jumping to the kernel. The
+        * l2x0 core will not touch the unlock registers if the l2x0 is
+        * already enabled, so we do it right here instead. The PL310 has
+        * 8 sets of registers, one per possible CPU.
+        */
+       for (i = 0; i < 8; i++) {
+               writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
+                              i * L2X0_LOCKDOWN_STRIDE);
+               writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
+                              i * L2X0_LOCKDOWN_STRIDE);
+       }
+       return 0;
+}
+
+static int __init ux500_l2x0_init(void)
 {
        if (cpu_is_u5500())
                l2x0_base = __io_address(U5500_L2CC_BASE);
@@ -59,6 +79,9 @@ static int ux500_l2x0_init(void)
        else
                ux500_unknown_soc();
 
+       /* Unlock before init */
+       ux500_l2x0_unlock();
+
        /* 64KB way size, 8 way associativity, force WA */
        l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);