]> Pileus Git - ~andy/linux/blobdiff - arch/arm/mach-s3c24xx/common.c
Merge branch 'x86-asm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[~andy/linux] / arch / arm / mach-s3c24xx / common.c
index dc9927b13746dae7a5b8677f5238698cc6534e56..56cdd34cce41ee3200b111a05bbf0a196acd86c0 100644 (file)
@@ -41,6 +41,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
+#include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-serial.h>
 
@@ -52,6 +53,8 @@
 #include <plat/s3c2416.h>
 #include <plat/s3c244x.h>
 #include <plat/s3c2443.h>
+#include <plat/cpu-freq.h>
+#include <plat/pll.h>
 
 /* table of supported CPUs */
 
@@ -234,3 +237,67 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 
        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
+
+/* Serial port registrations */
+
+static struct resource s3c2410_uart0_resource[] = {
+       [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
+       [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
+                       IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
+                       NULL, IORESOURCE_IRQ)
+};
+
+static struct resource s3c2410_uart1_resource[] = {
+       [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
+       [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
+                       IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
+                       NULL, IORESOURCE_IRQ)
+};
+
+static struct resource s3c2410_uart2_resource[] = {
+       [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
+       [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
+                       IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
+                       NULL, IORESOURCE_IRQ)
+};
+
+static struct resource s3c2410_uart3_resource[] = {
+       [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
+       [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
+                       IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
+                       NULL, IORESOURCE_IRQ)
+};
+
+struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
+       [0] = {
+               .resources      = s3c2410_uart0_resource,
+               .nr_resources   = ARRAY_SIZE(s3c2410_uart0_resource),
+       },
+       [1] = {
+               .resources      = s3c2410_uart1_resource,
+               .nr_resources   = ARRAY_SIZE(s3c2410_uart1_resource),
+       },
+       [2] = {
+               .resources      = s3c2410_uart2_resource,
+               .nr_resources   = ARRAY_SIZE(s3c2410_uart2_resource),
+       },
+       [3] = {
+               .resources      = s3c2410_uart3_resource,
+               .nr_resources   = ARRAY_SIZE(s3c2410_uart3_resource),
+       },
+};
+
+/* initialise all the clocks */
+
+void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
+                                          unsigned long hclk,
+                                          unsigned long pclk)
+{
+       clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
+                                       clk_xtal.rate);
+
+       clk_mpll.rate = fclk;
+       clk_h.rate = hclk;
+       clk_p.rate = pclk;
+       clk_f.rate = fclk;
+}