Merge tags 'omap-cleanup-for-v3.6', 'omap-devel-dmtimer-for-v3.6' and 'omap-devel...

[~andy/linux] / arch / arm / mach-omap2 / control.h

diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index fcc98f822d9d3e932c03521ab9c8a107c960b0c8..5baf305386e97eb457bca89470f37abfbc41ae84 100644 (file)
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -21,6 +21,8 @@
 #include <mach/ctrl_module_pad_core_44xx.h>
 #include <mach/ctrl_module_pad_wkup_44xx.h>
 
+#include <plat/am33xx.h>
+
 #ifndef __ASSEMBLY__
 #define OMAP242X_CTRL_REGADDR(reg)                                     \
                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -28,6 +30,8 @@
                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)                                     \
                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define AM33XX_CTRL_REGADDR(reg)                                       \
+               AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
 #else
 #define OMAP242X_CTRL_REGADDR(reg)                                     \
                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -35,6 +39,8 @@
                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)                                     \
                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define AM33XX_CTRL_REGADDR(reg)                                       \
+               AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
 #endif /* __ASSEMBLY__ */
 
 /*
@@ -312,15 +318,15 @@
                                                OMAP343X_SCRATCHPAD + reg)
 
 /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
-#define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
-#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT   1
-#define AM35XX_VPFE_VBUSP_CLK_SHIFT     2
-#define AM35XX_HECC_VBUSP_CLK_SHIFT     3
-#define AM35XX_USBOTG_FCLK_SHIFT        8
-#define AM35XX_CPGMAC_FCLK_SHIFT        9
-#define AM35XX_VPFE_FCLK_SHIFT          10
-
-/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
+#define AM35XX_USBOTG_VBUSP_CLK_SHIFT  0
+#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT  1
+#define AM35XX_VPFE_VBUSP_CLK_SHIFT    2
+#define AM35XX_HECC_VBUSP_CLK_SHIFT    3
+#define AM35XX_USBOTG_FCLK_SHIFT       8
+#define AM35XX_CPGMAC_FCLK_SHIFT       9
+#define AM35XX_VPFE_FCLK_SHIFT         10
+
+/* AM35XX CONTROL_LVL_INTR_CLEAR bits */
 #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR        BIT(0)
 #define AM35XX_CPGMAC_C0_RX_PULSE_CLR  BIT(1)
 #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
@@ -330,21 +336,22 @@
 #define AM35XX_VPFE_CCDC_VD1_INT_CLR   BIT(6)
 #define AM35XX_VPFE_CCDC_VD2_INT_CLR   BIT(7)
 
-/*AM35XX CONTROL_IP_SW_RESET bits*/
+/* AM35XX CONTROL_IP_SW_RESET bits */
 #define AM35XX_USBOTGSS_SW_RST         BIT(0)
 #define AM35XX_CPGMACSS_SW_RST         BIT(1)
 #define AM35XX_VPFE_VBUSP_SW_RST       BIT(2)
 #define AM35XX_HECC_SW_RST             BIT(3)
 #define AM35XX_VPFE_PCLK_SW_RST                BIT(4)
 
-/*
- * CONTROL AM33XX STATUS register
- */
+/* AM33XX CONTROL_STATUS register */
 #define AM33XX_CONTROL_STATUS          0x040
+#define AM33XX_CONTROL_SEC_CLK_CTRL    0x1bc
 
-/*
- * CONTROL OMAP STATUS register to identify OMAP3 features
- */
+/* AM33XX CONTROL_STATUS bitfields (partial) */
+#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT           22
+#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK            (0x3 << 22)
+
+/* CONTROL OMAP STATUS register to identify OMAP3 features */
 #define OMAP3_CONTROL_OMAP_STATUS      0x044c
 
 #define OMAP3_SGX_SHIFT                        13