Merge tags 'omap-cleanup-for-v3.6', 'omap-devel-dmtimer-for-v3.6' and 'omap-devel...

[~andy/linux] / arch / arm / mach-omap2 / clock44xx_data.c

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 2172f660384889535c6d812dae30dacf56b18eec..de53b7014b80894fde68fdc8d81c3477bd55a47d 100644 (file)
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -84,6 +84,7 @@ static struct clk slimbus_clk = {
 
 static struct clk sys_32k_ck = {
        .name           = "sys_32k_ck",
+       .clkdm_name     = "prm_clkdm",
        .rate           = 32768,
        .ops            = &clkops_null,
 };
@@ -512,6 +513,7 @@ static struct clk ddrphy_ck = {
        .name           = "ddrphy_ck",
        .parent         = &dpll_core_m2_ck,
        .ops            = &clkops_null,
+       .clkdm_name     = "l3_emif_clkdm",
        .fixed_div      = 2,
        .recalc         = &omap_fixed_divisor_recalc,
 };
@@ -769,6 +771,7 @@ static const struct clksel dpll_mpu_m2_div[] = {
 static struct clk dpll_mpu_m2_ck = {
        .name           = "dpll_mpu_m2_ck",
        .parent         = &dpll_mpu_ck,
+       .clkdm_name     = "cm_clkdm",
        .clksel         = dpll_mpu_m2_div,
        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
@@ -1149,6 +1152,7 @@ static const struct clksel l3_div_div[] = {
 static struct clk l3_div_ck = {
        .name           = "l3_div_ck",
        .parent         = &div_core_ck,
+       .clkdm_name     = "cm_clkdm",
        .clksel         = l3_div_div,
        .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
        .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
@@ -2824,6 +2828,7 @@ static const struct clksel trace_clk_div_div[] = {
 static struct clk trace_clk_div_ck = {
        .name           = "trace_clk_div_ck",
        .parent         = &pmd_trace_clk_mux_ck,
+       .clkdm_name     = "emu_sys_clkdm",
        .clksel         = trace_clk_div_div,
        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
        .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
@@ -3380,28 +3385,18 @@ static struct omap_clk omap44xx_clks[] = {
        CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
        CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
        CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
-       CLK("omap_timer.1",     "32k_ck",       &sys_32k_ck,    CK_443X),
-       CLK("omap_timer.2",     "32k_ck",       &sys_32k_ck,    CK_443X),
-       CLK("omap_timer.3",     "32k_ck",       &sys_32k_ck,    CK_443X),
-       CLK("omap_timer.4",     "32k_ck",       &sys_32k_ck,    CK_443X),
-       CLK("omap_timer.5",     "32k_ck",       &sys_32k_ck,    CK_443X),
-       CLK("omap_timer.6",     "32k_ck",       &sys_32k_ck,    CK_443X),
-       CLK("omap_timer.7",     "32k_ck",       &sys_32k_ck,    CK_443X),
-       CLK("omap_timer.8",     "32k_ck",       &sys_32k_ck,    CK_443X),
-       CLK("omap_timer.9",     "32k_ck",       &sys_32k_ck,    CK_443X),
-       CLK("omap_timer.10",    "32k_ck",       &sys_32k_ck,    CK_443X),
-       CLK("omap_timer.11",    "32k_ck",       &sys_32k_ck,    CK_443X),
-       CLK("omap_timer.1",     "sys_ck",       &sys_clkin_ck,  CK_443X),
-       CLK("omap_timer.2",     "sys_ck",       &sys_clkin_ck,  CK_443X),
-       CLK("omap_timer.3",     "sys_ck",       &sys_clkin_ck,  CK_443X),
-       CLK("omap_timer.4",     "sys_ck",       &sys_clkin_ck,  CK_443X),
-       CLK("omap_timer.9",     "sys_ck",       &sys_clkin_ck,  CK_443X),
-       CLK("omap_timer.10",    "sys_ck",       &sys_clkin_ck,  CK_443X),
-       CLK("omap_timer.11",    "sys_ck",       &sys_clkin_ck,  CK_443X),
-       CLK("omap_timer.5",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
-       CLK("omap_timer.6",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
-       CLK("omap_timer.7",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
-       CLK("omap_timer.8",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
+       CLK(NULL,       "timer_32k_ck", &sys_32k_ck,    CK_443X),
+       CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+       CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+       CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+       CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+       CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+       CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+       CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+       CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+       CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+       CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+       CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
 };
 
 int __init omap4xxx_clk_init(void)
@@ -3412,9 +3407,12 @@ int __init omap4xxx_clk_init(void)
        if (cpu_is_omap443x()) {
                cpu_mask = RATE_IN_4430;
                cpu_clkflg = CK_443X;
-       } else if (cpu_is_omap446x()) {
+       } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
                cpu_mask = RATE_IN_4460 | RATE_IN_4430;
                cpu_clkflg = CK_446X | CK_443X;
+
+               if (cpu_is_omap447x())
+                       pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
        } else {
                return 0;
        }