ARM: OMAP4: PM: Add init api for DPLL nodes

[~andy/linux] / arch / arm / mach-omap2 / clock44xx_data.c

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 9ae526ee0dafb5d8fa6b876f96976fb52829b068..2210e227d78a2b93fdd9ccba0d84f94a26cbb0bd 100644 (file)
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -278,6 +278,7 @@ static struct clk dpll_abe_ck = {
        .name           = "dpll_abe_ck",
        .parent         = &abe_dpll_refclk_mux_ck,
        .dpll_data      = &dpll_abe_dd,
+       .init           = &omap2_init_dpll_parent,
        .ops            = &clkops_noncore_dpll_ops,
        .recalc         = &omap3_dpll_recalc,
        .round_rate     = &omap2_dpll_round_rate,
@@ -439,6 +440,7 @@ static struct clk dpll_core_ck = {
        .name           = "dpll_core_ck",
        .parent         = &dpll_sys_ref_clk,
        .dpll_data      = &dpll_core_dd,
+       .init           = &omap2_init_dpll_parent,
        .ops            = &clkops_null,
        .recalc         = &omap3_dpll_recalc,
        .flags          = CLOCK_IN_OMAP4430,
@@ -665,6 +667,7 @@ static struct clk dpll_iva_ck = {
        .name           = "dpll_iva_ck",
        .parent         = &dpll_sys_ref_clk,
        .dpll_data      = &dpll_iva_dd,
+       .init           = &omap2_init_dpll_parent,
        .ops            = &clkops_noncore_dpll_ops,
        .recalc         = &omap3_dpll_recalc,
        .round_rate     = &omap2_dpll_round_rate,
@@ -727,6 +730,7 @@ static struct clk dpll_mpu_ck = {
        .name           = "dpll_mpu_ck",
        .parent         = &dpll_sys_ref_clk,
        .dpll_data      = &dpll_mpu_dd,
+       .init           = &omap2_init_dpll_parent,
        .ops            = &clkops_noncore_dpll_ops,
        .recalc         = &omap3_dpll_recalc,
        .round_rate     = &omap2_dpll_round_rate,
@@ -802,6 +806,7 @@ static struct clk dpll_per_ck = {
        .name           = "dpll_per_ck",
        .parent         = &dpll_sys_ref_clk,
        .dpll_data      = &dpll_per_dd,
+       .init           = &omap2_init_dpll_parent,
        .ops            = &clkops_noncore_dpll_ops,
        .recalc         = &omap3_dpll_recalc,
        .round_rate     = &omap2_dpll_round_rate,
@@ -924,6 +929,7 @@ static struct clk dpll_unipro_ck = {
        .name           = "dpll_unipro_ck",
        .parent         = &dpll_sys_ref_clk,
        .dpll_data      = &dpll_unipro_dd,
+       .init           = &omap2_init_dpll_parent,
        .ops            = &clkops_noncore_dpll_ops,
        .recalc         = &omap3_dpll_recalc,
        .round_rate     = &omap2_dpll_round_rate,
@@ -981,6 +987,7 @@ static struct clk dpll_usb_ck = {
        .name           = "dpll_usb_ck",
        .parent         = &dpll_sys_ref_clk,
        .dpll_data      = &dpll_usb_dd,
+       .init           = &omap2_init_dpll_parent,
        .ops            = &clkops_noncore_dpll_ops,
        .recalc         = &omap3_dpll_recalc,
        .round_rate     = &omap2_dpll_round_rate,