Merge branch 'exynos/pwm-clocksource' into late/multiplatform

[~andy/linux] / arch / arm / mach-exynos / include / mach / irqs.h

diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 1f4dc35cd4b9b88479e4b16496a7f62a05c58a46..c72f59d91fcebcfc89a2857b050a653c5db660bc 100644 (file)
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -30,8 +30,6 @@
 
 /* For EXYNOS4 and EXYNOS5 */
 
-#define EXYNOS_IRQ_MCT_LOCALTIMER      IRQ_PPI(12)
-
 #define EXYNOS_IRQ_EINT16_31           IRQ_SPI(32)
 
 /* For EXYNOS4 SoCs */
@@ -128,7 +126,7 @@
 #define EXYNOS4_IRQ_ADC1               IRQ_SPI(107)
 #define EXYNOS4_IRQ_PEN1               IRQ_SPI(108)
 #define EXYNOS4_IRQ_KEYPAD             IRQ_SPI(109)
-#define EXYNOS4_IRQ_PMU                        IRQ_SPI(110)
+#define EXYNOS4_IRQ_POWER_PMU          IRQ_SPI(110)
 #define EXYNOS4_IRQ_GPS                        IRQ_SPI(111)
 #define EXYNOS4_IRQ_INTFEEDCTRL_SSS    IRQ_SPI(112)
 #define EXYNOS4_IRQ_SLIMBUS            IRQ_SPI(113)
@@ -136,6 +134,11 @@
 #define EXYNOS4_IRQ_TSI                        IRQ_SPI(115)
 #define EXYNOS4_IRQ_SATA               IRQ_SPI(116)
 
+#define EXYNOS4_IRQ_PMU                        COMBINER_IRQ(2, 2)
+#define EXYNOS4_IRQ_PMU_CPU1           COMBINER_IRQ(3, 2)
+#define EXYNOS4_IRQ_PMU_CPU2           COMBINER_IRQ(18, 2)
+#define EXYNOS4_IRQ_PMU_CPU3           COMBINER_IRQ(19, 2)
+
 #define EXYNOS4_IRQ_TMU_TRIG0          COMBINER_IRQ(2, 4)
 #define EXYNOS4_IRQ_TMU_TRIG1          COMBINER_IRQ(3, 4)
 
@@ -168,7 +171,10 @@
 #define EXYNOS4_IRQ_FIMD0_VSYNC                COMBINER_IRQ(11, 1)
 #define EXYNOS4_IRQ_FIMD0_SYSTEM       COMBINER_IRQ(11, 2)
 
-#define EXYNOS4_MAX_COMBINER_NR                16
+#define EXYNOS4210_MAX_COMBINER_NR     16
+#define EXYNOS4212_MAX_COMBINER_NR     18
+#define EXYNOS4412_MAX_COMBINER_NR     20
+#define EXYNOS4_MAX_COMBINER_NR                EXYNOS4412_MAX_COMBINER_NR
 
 #define EXYNOS4_IRQ_GPIO1_NR_GROUPS    16
 #define EXYNOS4_IRQ_GPIO2_NR_GROUPS    9
@@ -233,7 +239,6 @@
 #define IRQ_TC                         EXYNOS4_IRQ_PEN0
 
 #define IRQ_KEYPAD                     EXYNOS4_IRQ_KEYPAD
-#define IRQ_PMU                                EXYNOS4_IRQ_PMU
 
 #define IRQ_FIMD0_FIFO                 EXYNOS4_IRQ_FIMD0_FIFO
 #define IRQ_FIMD0_VSYNC                        EXYNOS4_IRQ_FIMD0_VSYNC
@@ -323,8 +328,6 @@
 #define EXYNOS5_IRQ_CEC                        IRQ_SPI(114)
 #define EXYNOS5_IRQ_SATA               IRQ_SPI(115)
 
-#define EXYNOS5_IRQ_MCT_L0             IRQ_SPI(120)
-#define EXYNOS5_IRQ_MCT_L1             IRQ_SPI(121)
 #define EXYNOS5_IRQ_MMC44              IRQ_SPI(123)
 #define EXYNOS5_IRQ_MDMA1              IRQ_SPI(124)
 #define EXYNOS5_IRQ_FIMC_LITE0         IRQ_SPI(125)
@@ -419,8 +422,6 @@
 #define EXYNOS5_IRQ_PMU_CPU1           COMBINER_IRQ(22, 4)
 
 #define EXYNOS5_IRQ_EINT0              COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_G0             COMBINER_IRQ(23, 3)
-#define EXYNOS5_IRQ_MCT_G1             COMBINER_IRQ(23, 4)
 
 #define EXYNOS5_IRQ_EINT1              COMBINER_IRQ(24, 0)
 #define EXYNOS5_IRQ_SYSMMU_LITE1_0     COMBINER_IRQ(24, 1)
@@ -466,7 +467,10 @@
 #define IRQ_TIMER_BASE                 (IRQ_GPIO_END + 64)
 
 /* Set the default NR_IRQS */
+#define EXYNOS_NR_IRQS                 (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
 
-#define NR_IRQS                                (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+#ifndef CONFIG_SPARSE_IRQ
+#define NR_IRQS                                EXYNOS_NR_IRQS
+#endif
 
 #endif /* __ASM_ARCH_IRQS_H */