Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux...

[~andy/linux] / arch / arm / kernel / sleep.S

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 987dcf33415c420f70dc08852da45bd654a21ea2..db1536b8b30b497fe11923dfe9f67a72f86f7954 100644 (file)
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -6,6 +6,49 @@
 #include <asm/glue-proc.h>
        .text
 
+/*
+ * Implementation of MPIDR hash algorithm through shifting
+ * and OR'ing.
+ *
+ * @dst: register containing hash result
+ * @rs0: register containing affinity level 0 bit shift
+ * @rs1: register containing affinity level 1 bit shift
+ * @rs2: register containing affinity level 2 bit shift
+ * @mpidr: register containing MPIDR value
+ * @mask: register containing MPIDR mask
+ *
+ * Pseudo C-code:
+ *
+ *u32 dst;
+ *
+ *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
+ *     u32 aff0, aff1, aff2;
+ *     u32 mpidr_masked = mpidr & mask;
+ *     aff0 = mpidr_masked & 0xff;
+ *     aff1 = mpidr_masked & 0xff00;
+ *     aff2 = mpidr_masked & 0xff0000;
+ *     dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2);
+ *}
+ * Input registers: rs0, rs1, rs2, mpidr, mask
+ * Output register: dst
+ * Note: input and output registers must be disjoint register sets
+         (eg: a macro instance with mpidr = r1 and dst = r1 is invalid)
+ */
+       .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
+       and     \mpidr, \mpidr, \mask                   @ mask out MPIDR bits
+       and     \dst, \mpidr, #0xff                     @ mask=aff0
+ ARM(  mov     \dst, \dst, lsr \rs0            )       @ dst=aff0>>rs0
+ THUMB(        lsr     \dst, \dst, \rs0                )
+       and     \mask, \mpidr, #0xff00                  @ mask = aff1
+ ARM(  orr     \dst, \dst, \mask, lsr \rs1     )       @ dst|=(aff1>>rs1)
+ THUMB(        lsr     \mask, \mask, \rs1              )
+ THUMB(        orr     \dst, \dst, \mask               )
+       and     \mask, \mpidr, #0xff0000                @ mask = aff2
+ ARM(  orr     \dst, \dst, \mask, lsr \rs2     )       @ dst|=(aff2>>rs2)
+ THUMB(        lsr     \mask, \mask, \rs2              )
+ THUMB(        orr     \dst, \dst, \mask               )
+       .endm
+
 /*
  * Save CPU state for a suspend.  This saves the CPU general purpose
  * registers, and allocates space on the kernel stack to save the CPU
@@ -29,12 +72,18 @@ ENTRY(__cpu_suspend)
        mov     r1, r4                  @ size of save block
        mov     r2, r5                  @ virtual SP
        ldr     r3, =sleep_save_sp
-#ifdef CONFIG_SMP
-       ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
-       ALT_UP(mov lr, #0)
-       and     lr, lr, #15
+       ldr     r3, [r3, #SLEEP_SAVE_SP_VIRT]
+       ALT_SMP(mrc p15, 0, r9, c0, c0, 5)
+        ALT_UP_B(1f)
+       ldr     r8, =mpidr_hash
+       /*
+        * This ldmia relies on the memory layout of the mpidr_hash
+        * struct mpidr_hash.
+        */
+       ldmia   r8, {r4-r7}     @ r4 = mpidr mask (r5,r6,r7) = l[0,1,2] shifts
+       compute_mpidr_hash      lr, r5, r6, r7, r9, r4
        add     r3, r3, lr, lsl #2
-#endif
+1:
        bl      __cpu_suspend_save
        adr     lr, BSYM(cpu_suspend_abort)
        ldmfd   sp!, {r0, pc}           @ call suspend fn
@@ -81,15 +130,23 @@ ENDPROC(cpu_resume_after_mmu)
        .data
        .align
 ENTRY(cpu_resume)
-#ifdef CONFIG_SMP
-       adr     r0, sleep_save_sp
-       ALT_SMP(mrc p15, 0, r1, c0, c0, 5)
-       ALT_UP(mov r1, #0)
-       and     r1, r1, #15
-       ldr     r0, [r0, r1, lsl #2]    @ stack phys addr
-#else
-       ldr     r0, sleep_save_sp       @ stack phys addr
-#endif
+       mov     r1, #0
+       ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
+       ALT_UP_B(1f)
+       adr     r2, mpidr_hash_ptr
+       ldr     r3, [r2]
+       add     r2, r2, r3              @ r2 = struct mpidr_hash phys address
+       /*
+        * This ldmia relies on the memory layout of the mpidr_hash
+        * struct mpidr_hash.
+        */
+       ldmia   r2, { r3-r6 }   @ r3 = mpidr mask (r4,r5,r6) = l[0,1,2] shifts
+       compute_mpidr_hash      r1, r4, r5, r6, r0, r3
+1:
+       adr     r0, _sleep_save_sp
+       ldr     r0, [r0, #SLEEP_SAVE_SP_PHYS]
+       ldr     r0, [r0, r1, lsl #2]
+
        setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1  @ set SVC, irqs off
        @ load phys pgd, stack, resume fn
   ARM( ldmia   r0!, {r1, sp, pc}       )
@@ -98,7 +155,11 @@ THUMB(      mov     sp, r2                  )
 THUMB( bx      r3                      )
 ENDPROC(cpu_resume)
 
-sleep_save_sp:
-       .rept   CONFIG_NR_CPUS
-       .long   0                               @ preserve stack phys ptr here
-       .endr
+       .align 2
+mpidr_hash_ptr:
+       .long   mpidr_hash - .                  @ mpidr_hash struct offset
+
+       .type   sleep_save_sp, #object
+ENTRY(sleep_save_sp)
+_sleep_save_sp:
+       .space  SLEEP_SAVE_SP_SZ                @ struct sleep_save_sp