Merge branch 'nfsd-next' of git://linux-nfs.org/~bfields/linux

[~andy/linux] / arch / arm / boot / dts / sun5i-a13.dtsi

diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index ce8ef2a45be098a35521db6d7fa41c472cd0b85a..c463fd730c9155d8c9a491cf176a7320831e29fd 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -67,6 +67,29 @@
                        clocks = <&osc24M>;
                };
 
+               pll4: pll4@01c20018 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-pll1-clk";
+                       reg = <0x01c20018 0x4>;
+                       clocks = <&osc24M>;
+               };
+
+               pll5: pll5@01c20020 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-pll5-clk";
+                       reg = <0x01c20020 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll5_ddr", "pll5_other";
+               };
+
+               pll6: pll6@01c20028 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-pll6-clk";
+                       reg = <0x01c20028 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
+               };
+
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
@@ -125,12 +148,11 @@
                        clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
                };
 
-               /* dummy is pll6 */
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
-                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                };
 
                apb1: apb1@01c20058 {
@@ -148,6 +170,102 @@
                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
                                "apb1_i2c2", "apb1_uart1", "apb1_uart3";
                };
+
+               nand_clk: clk@01c20080 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c20080 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "nand";
+               };
+
+               ms_clk: clk@01c20084 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c20084 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "ms";
+               };
+
+               mmc0_clk: clk@01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "mmc0";
+               };
+
+               mmc1_clk: clk@01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "mmc1";
+               };
+
+               mmc2_clk: clk@01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "mmc2";
+               };
+
+               ts_clk: clk@01c20098 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c20098 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "ts";
+               };
+
+               ss_clk: clk@01c2009c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c2009c 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "ss";
+               };
+
+               spi0_clk: clk@01c200a0 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200a0 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "spi0";
+               };
+
+               spi1_clk: clk@01c200a4 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200a4 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "spi1";
+               };
+
+               spi2_clk: clk@01c200a8 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200a8 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "spi2";
+               };
+
+               ir0_clk: clk@01c200b0 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200b0 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "ir0";
+               };
+
+               mbus_clk: clk@01c2015c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c2015c 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "mbus";
+               };
        };
 
        soc@01c00000 {
@@ -227,6 +345,12 @@
                        reg = <0x01c23800 0x10>;
                };
 
+               rtp: rtp@01c25000 {
+                       compatible = "allwinner,sun4i-a10-ts";
+                       reg = <0x01c25000 0x100>;
+                       interrupts = <29>;
+               };
+
                uart1: serial@01c28400 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c28400 0x400>;
@@ -273,5 +397,12 @@
                        clock-frequency = <100000>;
                        status = "disabled";
                };
+
+               timer@01c60000 {
+                       compatible = "allwinner,sun5i-a13-hstimer";
+                       reg = <0x01c60000 0x1000>;
+                       interrupts = <82>, <83>;
+                       clocks = <&ahb_gates 28>;
+               };
        };
 };