arm: mvebu: armada-xp-db: ensure PCIe range is specified

[~andy/linux] / arch / arm / boot / dts / armada-xp-db.dts

diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 54cc5bb705fb0e1fcb38bbd2d82340ec28473533..e28e68ff864dbd40c2aca2a00d25e74cc0f70137 100644 (file)
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -26,132 +26,168 @@
 
        memory {
                device_type = "memory";
-               reg = <0x00000000 0x80000000>; /* 2 GB */
+               reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
        };
 
        soc {
-               serial@d0012000 {
-                       clock-frequency = <250000000>;
-                       status = "okay";
-               };
-               serial@d0012100 {
-                       clock-frequency = <250000000>;
-                       status = "okay";
-               };
-               serial@d0012200 {
-                       clock-frequency = <250000000>;
-                       status = "okay";
-               };
-               serial@d0012300 {
-                       clock-frequency = <250000000>;
-                       status = "okay";
-               };
-
-               sata@d00a0000 {
-                       nr-ports = <2>;
-                       status = "okay";
-               };
+               ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
+                         0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
+                         0xf0000000 0 0xf0000000 0x1000000>;   /* Device Bus, NOR 16MiB   */
 
-               mdio {
-                       phy0: ethernet-phy@0 {
-                               reg = <0>;
+               internal-regs {
+                       serial@12000 {
+                               clock-frequency = <250000000>;
+                               status = "okay";
                        };
-
-                       phy1: ethernet-phy@1 {
-                               reg = <1>;
+                       serial@12100 {
+                               clock-frequency = <250000000>;
+                               status = "okay";
                        };
-
-                       phy2: ethernet-phy@2 {
-                               reg = <25>;
+                       serial@12200 {
+                               clock-frequency = <250000000>;
+                               status = "okay";
+                       };
+                       serial@12300 {
+                               clock-frequency = <250000000>;
+                               status = "okay";
                        };
 
-                       phy3: ethernet-phy@3 {
-                               reg = <27>;
+                       sata@a0000 {
+                               nr-ports = <2>;
+                               status = "okay";
                        };
-               };
 
-               ethernet@d0070000 {
-                       status = "okay";
-                       phy = <&phy0>;
-                       phy-mode = "rgmii-id";
-               };
-               ethernet@d0074000 {
-                       status = "okay";
-                       phy = <&phy1>;
-                       phy-mode = "rgmii-id";
-               };
-               ethernet@d0030000 {
-                       status = "okay";
-                       phy = <&phy2>;
-                       phy-mode = "sgmii";
-               };
-               ethernet@d0034000 {
-                       status = "okay";
-                       phy = <&phy3>;
-                       phy-mode = "sgmii";
-               };
+                       mdio {
+                               phy0: ethernet-phy@0 {
+                                       reg = <0>;
+                               };
 
-               mvsdio@d00d4000 {
-                       pinctrl-0 = <&sdio_pins>;
-                       pinctrl-names = "default";
-                       status = "okay";
-                       /* No CD or WP GPIOs */
-               };
+                               phy1: ethernet-phy@1 {
+                                       reg = <1>;
+                               };
 
-               usb@d0050000 {
-                       status = "okay";
-               };
+                               phy2: ethernet-phy@2 {
+                                       reg = <25>;
+                               };
 
-               usb@d0051000 {
-                       status = "okay";
-               };
-
-               usb@d0052000 {
-                       status = "okay";
-               };
-
-               spi0: spi@d0010600 {
-                       status = "okay";
+                               phy3: ethernet-phy@3 {
+                                       reg = <27>;
+                               };
+                       };
 
-                       spi-flash@0 {
-                               #address-cells = <1>;
-                               #size-cells = <1>;
-                               compatible = "m25p64";
-                               reg = <0>; /* Chip select 0 */
-                               spi-max-frequency = <20000000>;
+                       ethernet@70000 {
+                               status = "okay";
+                               phy = <&phy0>;
+                               phy-mode = "rgmii-id";
+                       };
+                       ethernet@74000 {
+                               status = "okay";
+                               phy = <&phy1>;
+                               phy-mode = "rgmii-id";
+                       };
+                       ethernet@30000 {
+                               status = "okay";
+                               phy = <&phy2>;
+                               phy-mode = "sgmii";
+                       };
+                       ethernet@34000 {
+                               status = "okay";
+                               phy = <&phy3>;
+                               phy-mode = "sgmii";
                        };
-               };
 
-               pcie-controller {
-                       status = "okay";
+                       mvsdio@d4000 {
+                               pinctrl-0 = <&sdio_pins>;
+                               pinctrl-names = "default";
+                               status = "okay";
+                               /* No CD or WP GPIOs */
+                               broken-cd;
+                       };
 
-                       /*
-                        * All 6 slots are physically present as
-                        * standard PCIe slots on the board.
-                        */
-                       pcie@1,0 {
-                               /* Port 0, Lane 0 */
+                       usb@50000 {
                                status = "okay";
                        };
-                       pcie@2,0 {
-                               /* Port 0, Lane 1 */
+
+                       usb@51000 {
                                status = "okay";
                        };
-                       pcie@3,0 {
-                               /* Port 0, Lane 2 */
+
+                       usb@52000 {
                                status = "okay";
                        };
-                       pcie@4,0 {
-                               /* Port 0, Lane 3 */
+
+                       spi0: spi@10600 {
                                status = "okay";
+
+                               spi-flash@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <1>;
+                                       compatible = "m25p64";
+                                       reg = <0>; /* Chip select 0 */
+                                       spi-max-frequency = <20000000>;
+                               };
                        };
-                       pcie@9,0 {
-                               /* Port 2, Lane 0 */
+
+                       pcie-controller {
                                status = "okay";
+
+                               /*
+                                * All 6 slots are physically present as
+                                * standard PCIe slots on the board.
+                                */
+                               pcie@1,0 {
+                                       /* Port 0, Lane 0 */
+                                       status = "okay";
+                               };
+                               pcie@2,0 {
+                                       /* Port 0, Lane 1 */
+                                       status = "okay";
+                               };
+                               pcie@3,0 {
+                                       /* Port 0, Lane 2 */
+                                       status = "okay";
+                               };
+                               pcie@4,0 {
+                                       /* Port 0, Lane 3 */
+                                       status = "okay";
+                               };
+                               pcie@9,0 {
+                                       /* Port 2, Lane 0 */
+                                       status = "okay";
+                               };
+                               pcie@10,0 {
+                                       /* Port 3, Lane 0 */
+                                       status = "okay";
+                               };
                        };
-                       pcie@10,0 {
-                               /* Port 3, Lane 0 */
+
+                       devbus-bootcs@10400 {
                                status = "okay";
+                               ranges = <0 0xf0000000 0x1000000>;
+
+                               /* Device Bus parameters are required */
+
+                               /* Read parameters */
+                               devbus,bus-width    = <8>;
+                               devbus,turn-off-ps  = <60000>;
+                               devbus,badr-skew-ps = <0>;
+                               devbus,acc-first-ps = <124000>;
+                               devbus,acc-next-ps  = <248000>;
+                               devbus,rd-setup-ps  = <0>;
+                               devbus,rd-hold-ps   = <0>;
+
+                               /* Write parameters */
+                               devbus,sync-enable = <0>;
+                               devbus,wr-high-ps  = <60000>;
+                               devbus,wr-low-ps   = <60000>;
+                               devbus,ale-wr-ps   = <60000>;
+
+                               /* NOR 16 MiB */
+                               nor@0 {
+                                       compatible = "cfi-flash";
+                                       reg = <0 0x1000000>;
+                                       bank-width = <2>;
+                               };
                        };
                };
        };