ARC: MMUv4 preps/2 - Reshuffle PTE bits

[~andy/linux] / arch / arc / mm / tlbex.S

diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index ec382e59d6815ead8e648ea05e56171a476fa479..50e83ca96b96a6f0f1ef3f068b21e33a9bcb4b0c 100644 (file)
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -229,9 +229,6 @@ ex_saved_reg1:
        sr  r3, [ARC_REG_TLBPD1]        ; these go in PD1
 
        and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb
-#if (CONFIG_ARC_MMU_VER <= 2)   /* Neednot be done with v3 onwards */
-       lsr r2, r2                  ; shift PTE flags to match layout in PD0
-#endif
 
        lr  r3,[ARC_REG_TLBPD0]     ; MMU prepares PD0 with vaddr and asid