Pileus Git - ~andy/linux/blob - virt/kvm/ioapic.c

   1 /*
   2  *  Copyright (C) 2001  MandrakeSoft S.A.
   3  *  Copyright 2010 Red Hat, Inc. and/or its affiliates.
   4  *
   5  *    MandrakeSoft S.A.
   6  *    43, rue d'Aboukir
   7  *    75002 Paris - France
   8  *    http://www.linux-mandrake.com/
   9  *    http://www.mandrakesoft.com/
  10  *
  11  *  This library is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU Lesser General Public
  13  *  License as published by the Free Software Foundation; either
  14  *  version 2 of the License, or (at your option) any later version.
  15  *
  16  *  This library is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  *  Lesser General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU Lesser General Public
  22  *  License along with this library; if not, write to the Free Software
  23  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  24  *
  25  *  Yunhong Jiang <yunhong.jiang@intel.com>
  26  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
  27  *  Based on Xen 3.1 code.
  28  */
  29
  30 #include <linux/kvm_host.h>
  31 #include <linux/kvm.h>
  32 #include <linux/mm.h>
  33 #include <linux/highmem.h>
  34 #include <linux/smp.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <asm/processor.h>
  39 #include <asm/page.h>
  40 #include <asm/current.h>
  41 #include <trace/events/kvm.h>
  42
  43 #include "ioapic.h"
  44 #include "lapic.h"
  45 #include "irq.h"
  46
  47 #if 0
  48 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
  49 #else
  50 #define ioapic_debug(fmt, arg...)
  51 #endif
  52 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
  53
  54 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
  55                                           unsigned long addr,
  56                                           unsigned long length)
  57 {
  58         unsigned long result = 0;
  59
  60         switch (ioapic->ioregsel) {
  61         case IOAPIC_REG_VERSION:
  62                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
  63                           | (IOAPIC_VERSION_ID & 0xff));
  64                 break;
  65
  66         case IOAPIC_REG_APIC_ID:
  67         case IOAPIC_REG_ARB_ID:
  68                 result = ((ioapic->id & 0xf) << 24);
  69                 break;
  70
  71         default:
  72                 {
  73                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
  74                         u64 redir_content;
  75
  76                         ASSERT(redir_index < IOAPIC_NUM_PINS);
  77
  78                         redir_content = ioapic->redirtbl[redir_index].bits;
  79                         result = (ioapic->ioregsel & 0x1) ?
  80                             (redir_content >> 32) & 0xffffffff :
  81                             redir_content & 0xffffffff;
  82                         break;
  83                 }
  84         }
  85
  86         return result;
  87 }
  88
  89 static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
  90 {
  91         union kvm_ioapic_redirect_entry *pent;
  92         int injected = -1;
  93
  94         pent = &ioapic->redirtbl[idx];
  95
  96         if (!pent->fields.mask) {
  97                 injected = ioapic_deliver(ioapic, idx);
  98                 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
  99                         pent->fields.remote_irr = 1;
 100         }
 101
 102         return injected;
 103 }
 104
 105 static void update_handled_vectors(struct kvm_ioapic *ioapic)
 106 {
 107         DECLARE_BITMAP(handled_vectors, 256);
 108         int i;
 109
 110         memset(handled_vectors, 0, sizeof(handled_vectors));
 111         for (i = 0; i < IOAPIC_NUM_PINS; ++i)
 112                 __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
 113         memcpy(ioapic->handled_vectors, handled_vectors,
 114                sizeof(handled_vectors));
 115         smp_wmb();
 116 }
 117
 118 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
 119 {
 120         unsigned index;
 121         bool mask_before, mask_after;
 122         union kvm_ioapic_redirect_entry *e;
 123
 124         switch (ioapic->ioregsel) {
 125         case IOAPIC_REG_VERSION:
 126                 /* Writes are ignored. */
 127                 break;
 128
 129         case IOAPIC_REG_APIC_ID:
 130                 ioapic->id = (val >> 24) & 0xf;
 131                 break;
 132
 133         case IOAPIC_REG_ARB_ID:
 134                 break;
 135
 136         default:
 137                 index = (ioapic->ioregsel - 0x10) >> 1;
 138
 139                 ioapic_debug("change redir index %x val %x\n", index, val);
 140                 if (index >= IOAPIC_NUM_PINS)
 141                         return;
 142                 e = &ioapic->redirtbl[index];
 143                 mask_before = e->fields.mask;
 144                 if (ioapic->ioregsel & 1) {
 145                         e->bits &= 0xffffffff;
 146                         e->bits |= (u64) val << 32;
 147                 } else {
 148                         e->bits &= ~0xffffffffULL;
 149                         e->bits |= (u32) val;
 150                         e->fields.remote_irr = 0;
 151                 }
 152                 update_handled_vectors(ioapic);
 153                 mask_after = e->fields.mask;
 154                 if (mask_before != mask_after)
 155                         kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
 156                 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
 157                     && ioapic->irr & (1 << index))
 158                         ioapic_service(ioapic, index);
 159                 break;
 160         }
 161 }
 162
 163 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
 164 {
 165         union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
 166         struct kvm_lapic_irq irqe;
 167
 168         ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
 169                      "vector=%x trig_mode=%x\n",
 170                      entry->fields.dest_id, entry->fields.dest_mode,
 171                      entry->fields.delivery_mode, entry->fields.vector,
 172                      entry->fields.trig_mode);
 173
 174         irqe.dest_id = entry->fields.dest_id;
 175         irqe.vector = entry->fields.vector;
 176         irqe.dest_mode = entry->fields.dest_mode;
 177         irqe.trig_mode = entry->fields.trig_mode;
 178         irqe.delivery_mode = entry->fields.delivery_mode << 8;
 179         irqe.level = 1;
 180         irqe.shorthand = 0;
 181
 182         return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
 183 }
 184
 185 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
 186                        int level)
 187 {
 188         u32 old_irr;
 189         u32 mask = 1 << irq;
 190         union kvm_ioapic_redirect_entry entry;
 191         int ret, irq_level;
 192
 193         BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);
 194
 195         spin_lock(&ioapic->lock);
 196         old_irr = ioapic->irr;
 197         irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
 198                                          irq_source_id, level);
 199         entry = ioapic->redirtbl[irq];
 200         irq_level ^= entry.fields.polarity;
 201         if (!irq_level) {
 202                 ioapic->irr &= ~mask;
 203                 ret = 1;
 204         } else {
 205                 int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
 206                 ioapic->irr |= mask;
 207                 if ((edge && old_irr != ioapic->irr) ||
 208                     (!edge && !entry.fields.remote_irr))
 209                         ret = ioapic_service(ioapic, irq);
 210                 else
 211                         ret = 0; /* report coalesced interrupt */
 212         }
 213         trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
 214         spin_unlock(&ioapic->lock);
 215
 216         return ret;
 217 }
 218
 219 void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
 220 {
 221         int i;
 222
 223         spin_lock(&ioapic->lock);
 224         for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
 225                 __clear_bit(irq_source_id, &ioapic->irq_states[i]);
 226         spin_unlock(&ioapic->lock);
 227 }
 228
 229 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
 230                                      int trigger_mode)
 231 {
 232         int i;
 233
 234         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 235                 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
 236
 237                 if (ent->fields.vector != vector)
 238                         continue;
 239
 240                 /*
 241                  * We are dropping lock while calling ack notifiers because ack
 242                  * notifier callbacks for assigned devices call into IOAPIC
 243                  * recursively. Since remote_irr is cleared only after call
 244                  * to notifiers if the same vector will be delivered while lock
 245                  * is dropped it will be put into irr and will be delivered
 246                  * after ack notifier returns.
 247                  */
 248                 spin_unlock(&ioapic->lock);
 249                 kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
 250                 spin_lock(&ioapic->lock);
 251
 252                 if (trigger_mode != IOAPIC_LEVEL_TRIG)
 253                         continue;
 254
 255                 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
 256                 ent->fields.remote_irr = 0;
 257                 if (!ent->fields.mask && (ioapic->irr & (1 << i)))
 258                         ioapic_service(ioapic, i);
 259         }
 260 }
 261
 262 bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector)
 263 {
 264         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 265         smp_rmb();
 266         return test_bit(vector, ioapic->handled_vectors);
 267 }
 268
 269 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
 270 {
 271         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 272
 273         spin_lock(&ioapic->lock);
 274         __kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
 275         spin_unlock(&ioapic->lock);
 276 }
 277
 278 static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
 279 {
 280         return container_of(dev, struct kvm_ioapic, dev);
 281 }
 282
 283 static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
 284 {
 285         return ((addr >= ioapic->base_address &&
 286                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
 287 }
 288
 289 static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
 290                             void *val)
 291 {
 292         struct kvm_ioapic *ioapic = to_ioapic(this);
 293         u32 result;
 294         if (!ioapic_in_range(ioapic, addr))
 295                 return -EOPNOTSUPP;
 296
 297         ioapic_debug("addr %lx\n", (unsigned long)addr);
 298         ASSERT(!(addr & 0xf));  /* check alignment */
 299
 300         addr &= 0xff;
 301         spin_lock(&ioapic->lock);
 302         switch (addr) {
 303         case IOAPIC_REG_SELECT:
 304                 result = ioapic->ioregsel;
 305                 break;
 306
 307         case IOAPIC_REG_WINDOW:
 308                 result = ioapic_read_indirect(ioapic, addr, len);
 309                 break;
 310
 311         default:
 312                 result = 0;
 313                 break;
 314         }
 315         spin_unlock(&ioapic->lock);
 316
 317         switch (len) {
 318         case 8:
 319                 *(u64 *) val = result;
 320                 break;
 321         case 1:
 322         case 2:
 323         case 4:
 324                 memcpy(val, (char *)&result, len);
 325                 break;
 326         default:
 327                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
 328         }
 329         return 0;
 330 }
 331
 332 static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
 333                              const void *val)
 334 {
 335         struct kvm_ioapic *ioapic = to_ioapic(this);
 336         u32 data;
 337         if (!ioapic_in_range(ioapic, addr))
 338                 return -EOPNOTSUPP;
 339
 340         ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
 341                      (void*)addr, len, val);
 342         ASSERT(!(addr & 0xf));  /* check alignment */
 343
 344         switch (len) {
 345         case 8:
 346         case 4:
 347                 data = *(u32 *) val;
 348                 break;
 349         case 2:
 350                 data = *(u16 *) val;
 351                 break;
 352         case 1:
 353                 data = *(u8  *) val;
 354                 break;
 355         default:
 356                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
 357                 return 0;
 358         }
 359
 360         addr &= 0xff;
 361         spin_lock(&ioapic->lock);
 362         switch (addr) {
 363         case IOAPIC_REG_SELECT:
 364                 ioapic->ioregsel = data & 0xFF; /* 8-bit register */
 365                 break;
 366
 367         case IOAPIC_REG_WINDOW:
 368                 ioapic_write_indirect(ioapic, data);
 369                 break;
 370 #ifdef  CONFIG_IA64
 371         case IOAPIC_REG_EOI:
 372                 __kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
 373                 break;
 374 #endif
 375
 376         default:
 377                 break;
 378         }
 379         spin_unlock(&ioapic->lock);
 380         return 0;
 381 }
 382
 383 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
 384 {
 385         int i;
 386
 387         for (i = 0; i < IOAPIC_NUM_PINS; i++)
 388                 ioapic->redirtbl[i].fields.mask = 1;
 389         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
 390         ioapic->ioregsel = 0;
 391         ioapic->irr = 0;
 392         ioapic->id = 0;
 393         update_handled_vectors(ioapic);
 394 }
 395
 396 static const struct kvm_io_device_ops ioapic_mmio_ops = {
 397         .read     = ioapic_mmio_read,
 398         .write    = ioapic_mmio_write,
 399 };
 400
 401 int kvm_ioapic_init(struct kvm *kvm)
 402 {
 403         struct kvm_ioapic *ioapic;
 404         int ret;
 405
 406         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
 407         if (!ioapic)
 408                 return -ENOMEM;
 409         spin_lock_init(&ioapic->lock);
 410         kvm->arch.vioapic = ioapic;
 411         kvm_ioapic_reset(ioapic);
 412         kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
 413         ioapic->kvm = kvm;
 414         mutex_lock(&kvm->slots_lock);
 415         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
 416                                       IOAPIC_MEM_LENGTH, &ioapic->dev);
 417         mutex_unlock(&kvm->slots_lock);
 418         if (ret < 0) {
 419                 kvm->arch.vioapic = NULL;
 420                 kfree(ioapic);
 421         }
 422
 423         return ret;
 424 }
 425
 426 void kvm_ioapic_destroy(struct kvm *kvm)
 427 {
 428         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 429
 430         if (ioapic) {
 431                 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
 432                 kvm->arch.vioapic = NULL;
 433                 kfree(ioapic);
 434         }
 435 }
 436
 437 int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
 438 {
 439         struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
 440         if (!ioapic)
 441                 return -EINVAL;
 442
 443         spin_lock(&ioapic->lock);
 444         memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
 445         spin_unlock(&ioapic->lock);
 446         return 0;
 447 }
 448
 449 int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
 450 {
 451         struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
 452         if (!ioapic)
 453                 return -EINVAL;
 454
 455         spin_lock(&ioapic->lock);
 456         memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
 457         update_handled_vectors(ioapic);
 458         spin_unlock(&ioapic->lock);
 459         return 0;
 460 }