2 * Copyright (C) 2001 MandrakeSoft S.A.
3 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 * http://www.linux-mandrake.com/
9 * http://www.mandrakesoft.com/
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or (at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this library; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * Yunhong Jiang <yunhong.jiang@intel.com>
26 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
27 * Based on Xen 3.1 code.
30 #include <linux/kvm_host.h>
31 #include <linux/kvm.h>
33 #include <linux/highmem.h>
34 #include <linux/smp.h>
35 #include <linux/hrtimer.h>
37 #include <linux/slab.h>
38 #include <linux/export.h>
39 #include <asm/processor.h>
41 #include <asm/current.h>
42 #include <trace/events/kvm.h>
49 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
51 #define ioapic_debug(fmt, arg...)
53 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
55 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
59 unsigned long result = 0;
61 switch (ioapic->ioregsel) {
62 case IOAPIC_REG_VERSION:
63 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
64 | (IOAPIC_VERSION_ID & 0xff));
67 case IOAPIC_REG_APIC_ID:
68 case IOAPIC_REG_ARB_ID:
69 result = ((ioapic->id & 0xf) << 24);
74 u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
77 ASSERT(redir_index < IOAPIC_NUM_PINS);
79 redir_content = ioapic->redirtbl[redir_index].bits;
80 result = (ioapic->ioregsel & 0x1) ?
81 (redir_content >> 32) & 0xffffffff :
82 redir_content & 0xffffffff;
90 static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
92 union kvm_ioapic_redirect_entry *pent;
95 pent = &ioapic->redirtbl[idx];
97 if (!pent->fields.mask) {
98 injected = ioapic_deliver(ioapic, idx);
99 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
100 pent->fields.remote_irr = 1;
106 static void update_handled_vectors(struct kvm_ioapic *ioapic)
108 DECLARE_BITMAP(handled_vectors, 256);
111 memset(handled_vectors, 0, sizeof(handled_vectors));
112 for (i = 0; i < IOAPIC_NUM_PINS; ++i)
113 __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
114 memcpy(ioapic->handled_vectors, handled_vectors,
115 sizeof(handled_vectors));
119 void kvm_ioapic_calculate_eoi_exitmap(struct kvm_vcpu *vcpu,
120 u64 *eoi_exit_bitmap)
122 struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
123 union kvm_ioapic_redirect_entry *e;
124 struct kvm_lapic_irq irqe;
127 spin_lock(&ioapic->lock);
128 /* traverse ioapic entry to set eoi exit bitmap*/
129 for (index = 0; index < IOAPIC_NUM_PINS; index++) {
130 e = &ioapic->redirtbl[index];
131 if (!e->fields.mask &&
132 (e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
133 kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC,
135 irqe.dest_id = e->fields.dest_id;
136 irqe.vector = e->fields.vector;
137 irqe.dest_mode = e->fields.dest_mode;
138 irqe.delivery_mode = e->fields.delivery_mode << 8;
139 kvm_calculate_eoi_exitmap(vcpu, &irqe, eoi_exit_bitmap);
142 spin_unlock(&ioapic->lock);
144 EXPORT_SYMBOL_GPL(kvm_ioapic_calculate_eoi_exitmap);
146 void kvm_ioapic_make_eoibitmap_request(struct kvm *kvm)
148 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
150 if (!kvm_apic_vid_enabled(kvm) || !ioapic)
152 kvm_make_update_eoibitmap_request(kvm);
155 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
158 bool mask_before, mask_after;
159 union kvm_ioapic_redirect_entry *e;
161 switch (ioapic->ioregsel) {
162 case IOAPIC_REG_VERSION:
163 /* Writes are ignored. */
166 case IOAPIC_REG_APIC_ID:
167 ioapic->id = (val >> 24) & 0xf;
170 case IOAPIC_REG_ARB_ID:
174 index = (ioapic->ioregsel - 0x10) >> 1;
176 ioapic_debug("change redir index %x val %x\n", index, val);
177 if (index >= IOAPIC_NUM_PINS)
179 e = &ioapic->redirtbl[index];
180 mask_before = e->fields.mask;
181 if (ioapic->ioregsel & 1) {
182 e->bits &= 0xffffffff;
183 e->bits |= (u64) val << 32;
185 e->bits &= ~0xffffffffULL;
186 e->bits |= (u32) val;
187 e->fields.remote_irr = 0;
189 update_handled_vectors(ioapic);
190 mask_after = e->fields.mask;
191 if (mask_before != mask_after)
192 kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
193 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
194 && ioapic->irr & (1 << index))
195 ioapic_service(ioapic, index);
196 kvm_ioapic_make_eoibitmap_request(ioapic->kvm);
201 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
203 union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
204 struct kvm_lapic_irq irqe;
206 ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
207 "vector=%x trig_mode=%x\n",
208 entry->fields.dest_id, entry->fields.dest_mode,
209 entry->fields.delivery_mode, entry->fields.vector,
210 entry->fields.trig_mode);
212 irqe.dest_id = entry->fields.dest_id;
213 irqe.vector = entry->fields.vector;
214 irqe.dest_mode = entry->fields.dest_mode;
215 irqe.trig_mode = entry->fields.trig_mode;
216 irqe.delivery_mode = entry->fields.delivery_mode << 8;
220 return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
223 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
228 union kvm_ioapic_redirect_entry entry;
231 BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);
233 spin_lock(&ioapic->lock);
234 old_irr = ioapic->irr;
235 irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
236 irq_source_id, level);
237 entry = ioapic->redirtbl[irq];
238 irq_level ^= entry.fields.polarity;
240 ioapic->irr &= ~mask;
243 int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
245 if ((edge && old_irr != ioapic->irr) ||
246 (!edge && !entry.fields.remote_irr))
247 ret = ioapic_service(ioapic, irq);
249 ret = 0; /* report coalesced interrupt */
251 trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
252 spin_unlock(&ioapic->lock);
257 void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
261 spin_lock(&ioapic->lock);
262 for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
263 __clear_bit(irq_source_id, &ioapic->irq_states[i]);
264 spin_unlock(&ioapic->lock);
267 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
272 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
273 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
275 if (ent->fields.vector != vector)
279 * We are dropping lock while calling ack notifiers because ack
280 * notifier callbacks for assigned devices call into IOAPIC
281 * recursively. Since remote_irr is cleared only after call
282 * to notifiers if the same vector will be delivered while lock
283 * is dropped it will be put into irr and will be delivered
284 * after ack notifier returns.
286 spin_unlock(&ioapic->lock);
287 kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
288 spin_lock(&ioapic->lock);
290 if (trigger_mode != IOAPIC_LEVEL_TRIG)
293 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
294 ent->fields.remote_irr = 0;
295 if (!ent->fields.mask && (ioapic->irr & (1 << i)))
296 ioapic_service(ioapic, i);
300 bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector)
302 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
304 return test_bit(vector, ioapic->handled_vectors);
307 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
309 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
311 spin_lock(&ioapic->lock);
312 __kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
313 spin_unlock(&ioapic->lock);
316 static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
318 return container_of(dev, struct kvm_ioapic, dev);
321 static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
323 return ((addr >= ioapic->base_address &&
324 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
327 static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
330 struct kvm_ioapic *ioapic = to_ioapic(this);
332 if (!ioapic_in_range(ioapic, addr))
335 ioapic_debug("addr %lx\n", (unsigned long)addr);
336 ASSERT(!(addr & 0xf)); /* check alignment */
339 spin_lock(&ioapic->lock);
341 case IOAPIC_REG_SELECT:
342 result = ioapic->ioregsel;
345 case IOAPIC_REG_WINDOW:
346 result = ioapic_read_indirect(ioapic, addr, len);
353 spin_unlock(&ioapic->lock);
357 *(u64 *) val = result;
362 memcpy(val, (char *)&result, len);
365 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
370 static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
373 struct kvm_ioapic *ioapic = to_ioapic(this);
375 if (!ioapic_in_range(ioapic, addr))
378 ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
379 (void*)addr, len, val);
380 ASSERT(!(addr & 0xf)); /* check alignment */
394 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
399 spin_lock(&ioapic->lock);
401 case IOAPIC_REG_SELECT:
402 ioapic->ioregsel = data & 0xFF; /* 8-bit register */
405 case IOAPIC_REG_WINDOW:
406 ioapic_write_indirect(ioapic, data);
410 __kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
417 spin_unlock(&ioapic->lock);
421 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
425 for (i = 0; i < IOAPIC_NUM_PINS; i++)
426 ioapic->redirtbl[i].fields.mask = 1;
427 ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
428 ioapic->ioregsel = 0;
431 update_handled_vectors(ioapic);
434 static const struct kvm_io_device_ops ioapic_mmio_ops = {
435 .read = ioapic_mmio_read,
436 .write = ioapic_mmio_write,
439 int kvm_ioapic_init(struct kvm *kvm)
441 struct kvm_ioapic *ioapic;
444 ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
447 spin_lock_init(&ioapic->lock);
448 kvm->arch.vioapic = ioapic;
449 kvm_ioapic_reset(ioapic);
450 kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
452 mutex_lock(&kvm->slots_lock);
453 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
454 IOAPIC_MEM_LENGTH, &ioapic->dev);
455 mutex_unlock(&kvm->slots_lock);
457 kvm->arch.vioapic = NULL;
464 void kvm_ioapic_destroy(struct kvm *kvm)
466 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
469 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
470 kvm->arch.vioapic = NULL;
475 int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
477 struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
481 spin_lock(&ioapic->lock);
482 memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
483 spin_unlock(&ioapic->lock);
487 int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
489 struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
493 spin_lock(&ioapic->lock);
494 memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
495 update_handled_vectors(ioapic);
496 kvm_ioapic_make_eoibitmap_request(kvm);
497 spin_unlock(&ioapic->lock);