2 * Helper routines for R-Car sound ADG.
4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/sh_clk.h>
20 struct clk *clk[CLKMAX];
22 int rate_of_441khz_div_6;
23 int rate_of_48khz_div_6;
27 #define for_each_rsnd_clk(pos, adg, i) \
28 for (i = 0, (pos) = adg->clk[i]; \
30 i++, (pos) = adg->clk[i])
31 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
33 static enum rsnd_reg rsnd_adg_ssi_reg_get(int id)
38 * SSI 8 is not connected to ADG.
44 if (0 <= id && id <= 3)
45 reg = RSND_REG_AUDIO_CLK_SEL0;
46 else if (4 <= id && id <= 7)
47 reg = RSND_REG_AUDIO_CLK_SEL1;
49 reg = RSND_REG_AUDIO_CLK_SEL2;
54 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
56 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
62 * we can get "ssi id" from mod
64 id = rsnd_mod_id(mod);
65 reg = rsnd_adg_ssi_reg_get(id);
67 rsnd_write(priv, mod, reg, 0);
72 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
74 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
75 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
76 struct device *dev = rsnd_priv_to_dev(priv);
88 dev_dbg(dev, "request clock = %d\n", rate);
91 * find suitable clock from
92 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
95 for_each_rsnd_clk(clk, adg, i) {
96 if (rate == clk_get_rate(clk)) {
103 * find 1/6 clock from BRGA/BRGB
105 if (rate == adg->rate_of_441khz_div_6) {
110 if (rate == adg->rate_of_48khz_div_6) {
119 /* see rsnd_adg_ssi_clk_init() */
120 rsnd_mod_bset(mod, SSICKR, 0x00FF0000, adg->ckr);
121 rsnd_mod_write(mod, BRRA, 0x00000002); /* 1/6 */
122 rsnd_mod_write(mod, BRRB, 0x00000002); /* 1/6 */
125 * This "mod" = "ssi" here.
126 * we can get "ssi id" from mod
128 id = rsnd_mod_id(mod);
129 reg = rsnd_adg_ssi_reg_get(id);
131 dev_dbg(dev, "ADG: ssi%d selects clk%d = %d", id, i, rate);
136 shift = (id % 4) * 8;
138 rsnd_bset(priv, mod, reg,
145 static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
159 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
160 * have 44.1kHz or 48kHz base clocks for now.
162 * SSI itself can divide parent clock by 1/1 - 1/16
163 * So, BRGA outputs 44.1kHz base parent clock 1/32,
164 * and, BRGB outputs 48.0kHz base parent clock 1/32 here.
166 * rsnd_adg_ssi_clk_try_start()
169 adg->rate_of_441khz_div_6 = 0;
170 adg->rate_of_48khz_div_6 = 0;
171 for_each_rsnd_clk(clk, adg, i) {
172 rate = clk_get_rate(clk);
174 if (0 == rate) /* not used */
178 if (!adg->rate_of_441khz_div_6 && (0 == rate % 44100)) {
179 adg->rate_of_441khz_div_6 = rate / 6;
180 ckr |= brg_table[i] << 20;
184 if (!adg->rate_of_48khz_div_6 && (0 == rate % 48000)) {
185 adg->rate_of_48khz_div_6 = rate / 6;
186 ckr |= brg_table[i] << 16;
193 int rsnd_adg_probe(struct platform_device *pdev,
194 struct rcar_snd_info *info,
195 struct rsnd_priv *priv)
197 struct rsnd_adg *adg;
198 struct device *dev = rsnd_priv_to_dev(priv);
202 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
204 dev_err(dev, "ADG allocate failed\n");
208 adg->clk[CLKA] = clk_get(NULL, "audio_clk_a");
209 adg->clk[CLKB] = clk_get(NULL, "audio_clk_b");
210 adg->clk[CLKC] = clk_get(NULL, "audio_clk_c");
211 adg->clk[CLKI] = clk_get(NULL, "audio_clk_internal");
212 for_each_rsnd_clk(clk, adg, i) {
214 dev_err(dev, "Audio clock failed\n");
219 rsnd_adg_ssi_clk_init(priv, adg);
223 dev_dbg(dev, "adg probed\n");
228 void rsnd_adg_remove(struct platform_device *pdev,
229 struct rsnd_priv *priv)
231 struct rsnd_adg *adg = priv->adg;
235 for_each_rsnd_clk(clk, adg, i)