Pileus Git - ~andy/linux/blob - sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   7  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <sound/core.h>
  32 #include <sound/pcm.h>
  33 #include <sound/pcm_params.h>
  34 #include <sound/initval.h>
  35 #include <sound/soc.h>
  36
  37 #include <plat/dma.h>
  38 #include <plat/mcbsp.h>
  39 #include "mcbsp.h"
  40 #include "omap-mcbsp.h"
  41 #include "omap-pcm.h"
  42
  43 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  44
  45 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
  46         xhandler_get, xhandler_put) \
  47 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  48         .info = omap_mcbsp_st_info_volsw, \
  49         .get = xhandler_get, .put = xhandler_put, \
  50         .private_value = (unsigned long) &(struct soc_mixer_control) \
  51         {.min = xmin, .max = xmax} }
  52
  53 enum {
  54         OMAP_MCBSP_WORD_8 = 0,
  55         OMAP_MCBSP_WORD_12,
  56         OMAP_MCBSP_WORD_16,
  57         OMAP_MCBSP_WORD_20,
  58         OMAP_MCBSP_WORD_24,
  59         OMAP_MCBSP_WORD_32,
  60 };
  61
  62 /*
  63  * Stream DMA parameters. DMA request line and port address are set runtime
  64  * since they are different between OMAP1 and later OMAPs
  65  */
  66 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
  67 {
  68         struct snd_soc_pcm_runtime *rtd = substream->private_data;
  69         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  70         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  71         struct omap_pcm_dma_data *dma_data;
  72         int words;
  73
  74         dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
  75
  76         /*
  77          * Configure McBSP threshold based on either:
  78          * packet_size, when the sDMA is in packet mode, or based on the
  79          * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
  80          * for mono streams.
  81          */
  82         if (dma_data->packet_size)
  83                 words = dma_data->packet_size;
  84         else
  85                 words = 1;
  86
  87         /* Configure McBSP internal buffer usage */
  88         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  89                 omap_mcbsp_set_tx_threshold(mcbsp, words);
  90         else
  91                 omap_mcbsp_set_rx_threshold(mcbsp, words);
  92 }
  93
  94 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
  95                                     struct snd_pcm_hw_rule *rule)
  96 {
  97         struct snd_interval *buffer_size = hw_param_interval(params,
  98                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
  99         struct snd_interval *channels = hw_param_interval(params,
 100                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 101         struct omap_mcbsp *mcbsp = rule->private;
 102         struct snd_interval frames;
 103         int size;
 104
 105         snd_interval_any(&frames);
 106         size = mcbsp->pdata->buffer_size;
 107
 108         frames.min = size / channels->min;
 109         frames.integer = 1;
 110         return snd_interval_refine(buffer_size, &frames);
 111 }
 112
 113 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 114                                   struct snd_soc_dai *cpu_dai)
 115 {
 116         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 117         int err = 0;
 118
 119         if (!cpu_dai->active)
 120                 err = omap_mcbsp_request(mcbsp);
 121
 122         /*
 123          * OMAP3 McBSP FIFO is word structured.
 124          * McBSP2 has 1024 + 256 = 1280 word long buffer,
 125          * McBSP1,3,4,5 has 128 word long buffer
 126          * This means that the size of the FIFO depends on the sample format.
 127          * For example on McBSP3:
 128          * 16bit samples: size is 128 * 2 = 256 bytes
 129          * 32bit samples: size is 128 * 4 = 512 bytes
 130          * It is simpler to place constraint for buffer and period based on
 131          * channels.
 132          * McBSP3 as example again (16 or 32 bit samples):
 133          * 1 channel (mono): size is 128 frames (128 words)
 134          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 135          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 136          */
 137         if (mcbsp->pdata->buffer_size) {
 138                 /*
 139                 * Rule for the buffer size. We should not allow
 140                 * smaller buffer than the FIFO size to avoid underruns.
 141                 * This applies only for the playback stream.
 142                 */
 143                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 144                         snd_pcm_hw_rule_add(substream->runtime, 0,
 145                                             SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 146                                             omap_mcbsp_hwrule_min_buffersize,
 147                                             mcbsp,
 148                                             SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 149
 150                 /* Make sure, that the period size is always even */
 151                 snd_pcm_hw_constraint_step(substream->runtime, 0,
 152                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
 153         }
 154
 155         return err;
 156 }
 157
 158 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 159                                     struct snd_soc_dai *cpu_dai)
 160 {
 161         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 162
 163         if (!cpu_dai->active) {
 164                 omap_mcbsp_free(mcbsp);
 165                 mcbsp->configured = 0;
 166         }
 167 }
 168
 169 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 170                                   struct snd_soc_dai *cpu_dai)
 171 {
 172         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 173         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 174
 175         switch (cmd) {
 176         case SNDRV_PCM_TRIGGER_START:
 177         case SNDRV_PCM_TRIGGER_RESUME:
 178         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 179                 mcbsp->active++;
 180                 omap_mcbsp_start(mcbsp, play, !play);
 181                 break;
 182
 183         case SNDRV_PCM_TRIGGER_STOP:
 184         case SNDRV_PCM_TRIGGER_SUSPEND:
 185         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 186                 omap_mcbsp_stop(mcbsp, play, !play);
 187                 mcbsp->active--;
 188                 break;
 189         default:
 190                 err = -EINVAL;
 191         }
 192
 193         return err;
 194 }
 195
 196 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 197                         struct snd_pcm_substream *substream,
 198                         struct snd_soc_dai *dai)
 199 {
 200         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 201         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 202         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 203         u16 fifo_use;
 204         snd_pcm_sframes_t delay;
 205
 206         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 207                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
 208         else
 209                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
 210
 211         /*
 212          * Divide the used locations with the channel count to get the
 213          * FIFO usage in samples (don't care about partial samples in the
 214          * buffer).
 215          */
 216         delay = fifo_use / substream->runtime->channels;
 217
 218         return delay;
 219 }
 220
 221 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 222                                     struct snd_pcm_hw_params *params,
 223                                     struct snd_soc_dai *cpu_dai)
 224 {
 225         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 226         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 227         struct omap_pcm_dma_data *dma_data;
 228         int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
 229         int pkt_size = 0;
 230         unsigned int format, div, framesize, master;
 231
 232         dma_data = &mcbsp->dma_data[substream->stream];
 233         channels = params_channels(params);
 234
 235         switch (params_format(params)) {
 236         case SNDRV_PCM_FORMAT_S16_LE:
 237                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
 238                 wlen = 16;
 239                 break;
 240         case SNDRV_PCM_FORMAT_S32_LE:
 241                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
 242                 wlen = 32;
 243                 break;
 244         default:
 245                 return -EINVAL;
 246         }
 247         if (mcbsp->pdata->buffer_size) {
 248                 dma_data->set_threshold = omap_mcbsp_set_threshold;
 249                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 250                         int period_words, max_thrsh;
 251                         int divider = 0;
 252
 253                         period_words = params_period_bytes(params) / (wlen / 8);
 254                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 255                                 max_thrsh = mcbsp->max_tx_thres;
 256                         else
 257                                 max_thrsh = mcbsp->max_rx_thres;
 258                         /*
 259                          * Use sDMA packet mode if McBSP is in threshold mode:
 260                          * If period words less than the FIFO size the packet
 261                          * size is set to the number of period words, otherwise
 262                          * Look for the biggest threshold value which divides
 263                          * the period size evenly.
 264                          */
 265                         divider = period_words / max_thrsh;
 266                         if (period_words % max_thrsh)
 267                                 divider++;
 268                         while (period_words % divider &&
 269                                 divider < period_words)
 270                                 divider++;
 271                         if (divider == period_words)
 272                                 return -EINVAL;
 273
 274                         pkt_size = period_words / divider;
 275                         sync_mode = OMAP_DMA_SYNC_PACKET;
 276                 } else if (channels > 1) {
 277                         /* Use packet mode for non mono streams */
 278                         pkt_size = channels;
 279                         sync_mode = OMAP_DMA_SYNC_PACKET;
 280                 }
 281         }
 282
 283         dma_data->sync_mode = sync_mode;
 284         dma_data->packet_size = pkt_size;
 285
 286         snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
 287
 288         if (mcbsp->configured) {
 289                 /* McBSP already configured by another stream */
 290                 return 0;
 291         }
 292
 293         regs->rcr2      &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
 294         regs->xcr2      &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
 295         regs->rcr1      &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
 296         regs->xcr1      &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
 297         format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 298         wpf = channels;
 299         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
 300                               format == SND_SOC_DAIFMT_LEFT_J)) {
 301                 /* Use dual-phase frames */
 302                 regs->rcr2      |= RPHASE;
 303                 regs->xcr2      |= XPHASE;
 304                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 305                 wpf--;
 306                 regs->rcr2      |= RFRLEN2(wpf - 1);
 307                 regs->xcr2      |= XFRLEN2(wpf - 1);
 308         }
 309
 310         regs->rcr1      |= RFRLEN1(wpf - 1);
 311         regs->xcr1      |= XFRLEN1(wpf - 1);
 312
 313         switch (params_format(params)) {
 314         case SNDRV_PCM_FORMAT_S16_LE:
 315                 /* Set word lengths */
 316                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 317                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 318                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 319                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 320                 break;
 321         case SNDRV_PCM_FORMAT_S32_LE:
 322                 /* Set word lengths */
 323                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
 324                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
 325                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
 326                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
 327                 break;
 328         default:
 329                 /* Unsupported PCM format */
 330                 return -EINVAL;
 331         }
 332
 333         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
 334          * by _counting_ BCLKs. Calculate frame size in BCLKs */
 335         master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 336         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
 337                 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
 338                 framesize = (mcbsp->in_freq / div) / params_rate(params);
 339
 340                 if (framesize < wlen * channels) {
 341                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
 342                                         "channels\n", __func__);
 343                         return -EINVAL;
 344                 }
 345         } else
 346                 framesize = wlen * channels;
 347
 348         /* Set FS period and length in terms of bit clock periods */
 349         regs->srgr2     &= ~FPER(0xfff);
 350         regs->srgr1     &= ~FWID(0xff);
 351         switch (format) {
 352         case SND_SOC_DAIFMT_I2S:
 353         case SND_SOC_DAIFMT_LEFT_J:
 354                 regs->srgr2     |= FPER(framesize - 1);
 355                 regs->srgr1     |= FWID((framesize >> 1) - 1);
 356                 break;
 357         case SND_SOC_DAIFMT_DSP_A:
 358         case SND_SOC_DAIFMT_DSP_B:
 359                 regs->srgr2     |= FPER(framesize - 1);
 360                 regs->srgr1     |= FWID(0);
 361                 break;
 362         }
 363
 364         omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
 365         mcbsp->wlen = wlen;
 366         mcbsp->configured = 1;
 367
 368         return 0;
 369 }
 370
 371 /*
 372  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 373  * cache is initialized here
 374  */
 375 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 376                                       unsigned int fmt)
 377 {
 378         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 379         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 380         bool inv_fs = false;
 381
 382         if (mcbsp->configured)
 383                 return 0;
 384
 385         mcbsp->fmt = fmt;
 386         memset(regs, 0, sizeof(*regs));
 387         /* Generic McBSP register settings */
 388         regs->spcr2     |= XINTM(3) | FREE;
 389         regs->spcr1     |= RINTM(3);
 390         /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
 391         if (!mcbsp->pdata->has_ccr) {
 392                 regs->rcr2      |= RFIG;
 393                 regs->xcr2      |= XFIG;
 394         }
 395
 396         /* Configure XCCR/RCCR only for revisions which have ccr registers */
 397         if (mcbsp->pdata->has_ccr) {
 398                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 399                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 400         }
 401
 402         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 403         case SND_SOC_DAIFMT_I2S:
 404                 /* 1-bit data delay */
 405                 regs->rcr2      |= RDATDLY(1);
 406                 regs->xcr2      |= XDATDLY(1);
 407                 break;
 408         case SND_SOC_DAIFMT_LEFT_J:
 409                 /* 0-bit data delay */
 410                 regs->rcr2      |= RDATDLY(0);
 411                 regs->xcr2      |= XDATDLY(0);
 412                 regs->spcr1     |= RJUST(2);
 413                 /* Invert FS polarity configuration */
 414                 inv_fs = true;
 415                 break;
 416         case SND_SOC_DAIFMT_DSP_A:
 417                 /* 1-bit data delay */
 418                 regs->rcr2      |= RDATDLY(1);
 419                 regs->xcr2      |= XDATDLY(1);
 420                 /* Invert FS polarity configuration */
 421                 inv_fs = true;
 422                 break;
 423         case SND_SOC_DAIFMT_DSP_B:
 424                 /* 0-bit data delay */
 425                 regs->rcr2      |= RDATDLY(0);
 426                 regs->xcr2      |= XDATDLY(0);
 427                 /* Invert FS polarity configuration */
 428                 inv_fs = true;
 429                 break;
 430         default:
 431                 /* Unsupported data format */
 432                 return -EINVAL;
 433         }
 434
 435         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 436         case SND_SOC_DAIFMT_CBS_CFS:
 437                 /* McBSP master. Set FS and bit clocks as outputs */
 438                 regs->pcr0      |= FSXM | FSRM |
 439                                    CLKXM | CLKRM;
 440                 /* Sample rate generator drives the FS */
 441                 regs->srgr2     |= FSGM;
 442                 break;
 443         case SND_SOC_DAIFMT_CBM_CFM:
 444                 /* McBSP slave */
 445                 break;
 446         default:
 447                 /* Unsupported master/slave configuration */
 448                 return -EINVAL;
 449         }
 450
 451         /* Set bit clock (CLKX/CLKR) and FS polarities */
 452         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 453         case SND_SOC_DAIFMT_NB_NF:
 454                 /*
 455                  * Normal BCLK + FS.
 456                  * FS active low. TX data driven on falling edge of bit clock
 457                  * and RX data sampled on rising edge of bit clock.
 458                  */
 459                 regs->pcr0      |= FSXP | FSRP |
 460                                    CLKXP | CLKRP;
 461                 break;
 462         case SND_SOC_DAIFMT_NB_IF:
 463                 regs->pcr0      |= CLKXP | CLKRP;
 464                 break;
 465         case SND_SOC_DAIFMT_IB_NF:
 466                 regs->pcr0      |= FSXP | FSRP;
 467                 break;
 468         case SND_SOC_DAIFMT_IB_IF:
 469                 break;
 470         default:
 471                 return -EINVAL;
 472         }
 473         if (inv_fs == true)
 474                 regs->pcr0 ^= FSXP | FSRP;
 475
 476         return 0;
 477 }
 478
 479 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 480                                      int div_id, int div)
 481 {
 482         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 483         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 484
 485         if (div_id != OMAP_MCBSP_CLKGDV)
 486                 return -ENODEV;
 487
 488         mcbsp->clk_div = div;
 489         regs->srgr1     &= ~CLKGDV(0xff);
 490         regs->srgr1     |= CLKGDV(div - 1);
 491
 492         return 0;
 493 }
 494
 495 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 496                                          int clk_id, unsigned int freq,
 497                                          int dir)
 498 {
 499         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 500         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 501         int err = 0;
 502
 503         if (mcbsp->active) {
 504                 if (freq == mcbsp->in_freq)
 505                         return 0;
 506                 else
 507                         return -EBUSY;
 508         }
 509
 510         mcbsp->in_freq = freq;
 511         regs->srgr2 &= ~CLKSM;
 512         regs->pcr0 &= ~SCLKME;
 513
 514         switch (clk_id) {
 515         case OMAP_MCBSP_SYSCLK_CLK:
 516                 regs->srgr2     |= CLKSM;
 517                 break;
 518         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 519                 if (cpu_class_is_omap1()) {
 520                         err = -EINVAL;
 521                         break;
 522                 }
 523                 err = omap2_mcbsp_set_clks_src(mcbsp,
 524                                                MCBSP_CLKS_PRCM_SRC);
 525                 break;
 526         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 527                 if (cpu_class_is_omap1()) {
 528                         err = 0;
 529                         break;
 530                 }
 531                 err = omap2_mcbsp_set_clks_src(mcbsp,
 532                                                MCBSP_CLKS_PAD_SRC);
 533                 break;
 534
 535         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 536                 regs->srgr2     |= CLKSM;
 537         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 538                 regs->pcr0      |= SCLKME;
 539                 break;
 540         default:
 541                 err = -ENODEV;
 542         }
 543
 544         return err;
 545 }
 546
 547 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
 548         .startup        = omap_mcbsp_dai_startup,
 549         .shutdown       = omap_mcbsp_dai_shutdown,
 550         .trigger        = omap_mcbsp_dai_trigger,
 551         .delay          = omap_mcbsp_dai_delay,
 552         .hw_params      = omap_mcbsp_dai_hw_params,
 553         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 554         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 555         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 556 };
 557
 558 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
 559 {
 560         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
 561
 562         pm_runtime_enable(mcbsp->dev);
 563
 564         return 0;
 565 }
 566
 567 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
 568 {
 569         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
 570
 571         pm_runtime_disable(mcbsp->dev);
 572
 573         return 0;
 574 }
 575
 576 static struct snd_soc_dai_driver omap_mcbsp_dai = {
 577         .probe = omap_mcbsp_probe,
 578         .remove = omap_mcbsp_remove,
 579         .playback = {
 580                 .channels_min = 1,
 581                 .channels_max = 16,
 582                 .rates = OMAP_MCBSP_RATES,
 583                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 584         },
 585         .capture = {
 586                 .channels_min = 1,
 587                 .channels_max = 16,
 588                 .rates = OMAP_MCBSP_RATES,
 589                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 590         },
 591         .ops = &mcbsp_dai_ops,
 592 };
 593
 594 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
 595                         struct snd_ctl_elem_info *uinfo)
 596 {
 597         struct soc_mixer_control *mc =
 598                 (struct soc_mixer_control *)kcontrol->private_value;
 599         int max = mc->max;
 600         int min = mc->min;
 601
 602         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 603         uinfo->count = 1;
 604         uinfo->value.integer.min = min;
 605         uinfo->value.integer.max = max;
 606         return 0;
 607 }
 608
 609 #define OMAP_MCBSP_ST_CHANNEL_VOLUME(channel)                           \
 610 static int                                                              \
 611 omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc,         \
 612                                         struct snd_ctl_elem_value *uc)  \
 613 {                                                                       \
 614         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
 615         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
 616         struct soc_mixer_control *mc =                                  \
 617                 (struct soc_mixer_control *)kc->private_value;          \
 618         int max = mc->max;                                              \
 619         int min = mc->min;                                              \
 620         int val = uc->value.integer.value[0];                           \
 621                                                                         \
 622         if (val < min || val > max)                                     \
 623                 return -EINVAL;                                         \
 624                                                                         \
 625         /* OMAP McBSP implementation uses index values 0..4 */          \
 626         return omap_st_set_chgain(mcbsp, channel, val);                 \
 627 }                                                                       \
 628                                                                         \
 629 static int                                                              \
 630 omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc,         \
 631                                         struct snd_ctl_elem_value *uc)  \
 632 {                                                                       \
 633         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
 634         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
 635         s16 chgain;                                                     \
 636                                                                         \
 637         if (omap_st_get_chgain(mcbsp, channel, &chgain))                \
 638                 return -EAGAIN;                                         \
 639                                                                         \
 640         uc->value.integer.value[0] = chgain;                            \
 641         return 0;                                                       \
 642 }
 643
 644 OMAP_MCBSP_ST_CHANNEL_VOLUME(0)
 645 OMAP_MCBSP_ST_CHANNEL_VOLUME(1)
 646
 647 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
 648                                 struct snd_ctl_elem_value *ucontrol)
 649 {
 650         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 651         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 652         u8 value = ucontrol->value.integer.value[0];
 653
 654         if (value == omap_st_is_enabled(mcbsp))
 655                 return 0;
 656
 657         if (value)
 658                 omap_st_enable(mcbsp);
 659         else
 660                 omap_st_disable(mcbsp);
 661
 662         return 1;
 663 }
 664
 665 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
 666                                 struct snd_ctl_elem_value *ucontrol)
 667 {
 668         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 669         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 670
 671         ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp);
 672         return 0;
 673 }
 674
 675 #define OMAP_MCBSP_ST_CONTROLS(port)                                      \
 676 static const struct snd_kcontrol_new omap_mcbsp##port##_st_controls[] = { \
 677 SOC_SINGLE_EXT("McBSP" #port " Sidetone Switch", 1, 0, 1, 0,              \
 678                omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),           \
 679 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 0 Volume", \
 680                               -32768, 32767,                              \
 681                               omap_mcbsp_get_st_ch0_volume,               \
 682                               omap_mcbsp_set_st_ch0_volume),              \
 683 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 1 Volume", \
 684                               -32768, 32767,                              \
 685                               omap_mcbsp_get_st_ch1_volume,               \
 686                               omap_mcbsp_set_st_ch1_volume),              \
 687 }
 688
 689 OMAP_MCBSP_ST_CONTROLS(2);
 690 OMAP_MCBSP_ST_CONTROLS(3);
 691
 692 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd)
 693 {
 694         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 695         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 696
 697         if (!mcbsp->st_data) {
 698                 dev_warn(mcbsp->dev, "No sidetone data for port\n");
 699                 return 0;
 700         }
 701
 702         switch (mcbsp->id) {
 703         case 2: /* McBSP 2 */
 704                 return snd_soc_add_dai_controls(cpu_dai,
 705                                         omap_mcbsp2_st_controls,
 706                                         ARRAY_SIZE(omap_mcbsp2_st_controls));
 707         case 3: /* McBSP 3 */
 708                 return snd_soc_add_dai_controls(cpu_dai,
 709                                         omap_mcbsp3_st_controls,
 710                                         ARRAY_SIZE(omap_mcbsp3_st_controls));
 711         default:
 712                 break;
 713         }
 714
 715         return -EINVAL;
 716 }
 717 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 718
 719 static struct omap_mcbsp_platform_data omap2420_pdata = {
 720         .reg_step = 4,
 721         .reg_size = 2,
 722 };
 723
 724 static struct omap_mcbsp_platform_data omap2430_pdata = {
 725         .reg_step = 4,
 726         .reg_size = 4,
 727         .has_ccr = true,
 728 };
 729
 730 static struct omap_mcbsp_platform_data omap3_pdata = {
 731         .reg_step = 4,
 732         .reg_size = 4,
 733         .has_ccr = true,
 734         .has_wakeup = true,
 735 };
 736
 737 static struct omap_mcbsp_platform_data omap4_pdata = {
 738         .reg_step = 4,
 739         .reg_size = 4,
 740         .has_ccr = true,
 741         .has_wakeup = true,
 742 };
 743
 744 static const struct of_device_id omap_mcbsp_of_match[] = {
 745         {
 746                 .compatible = "ti,omap2420-mcbsp",
 747                 .data = &omap2420_pdata,
 748         },
 749         {
 750                 .compatible = "ti,omap2430-mcbsp",
 751                 .data = &omap2430_pdata,
 752         },
 753         {
 754                 .compatible = "ti,omap3-mcbsp",
 755                 .data = &omap3_pdata,
 756         },
 757         {
 758                 .compatible = "ti,omap4-mcbsp",
 759                 .data = &omap4_pdata,
 760         },
 761         { },
 762 };
 763 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
 764
 765 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
 766 {
 767         struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
 768         struct omap_mcbsp *mcbsp;
 769         const struct of_device_id *match;
 770         int ret;
 771
 772         match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
 773         if (match) {
 774                 struct device_node *node = pdev->dev.of_node;
 775                 int buffer_size;
 776
 777                 pdata = devm_kzalloc(&pdev->dev,
 778                                      sizeof(struct omap_mcbsp_platform_data),
 779                                      GFP_KERNEL);
 780                 if (!pdata)
 781                         return -ENOMEM;
 782
 783                 memcpy(pdata, match->data, sizeof(*pdata));
 784                 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
 785                         pdata->buffer_size = buffer_size;
 786         } else if (!pdata) {
 787                 dev_err(&pdev->dev, "missing platform data.\n");
 788                 return -EINVAL;
 789         }
 790         mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
 791         if (!mcbsp)
 792                 return -ENOMEM;
 793
 794         mcbsp->id = pdev->id;
 795         mcbsp->pdata = pdata;
 796         mcbsp->dev = &pdev->dev;
 797         platform_set_drvdata(pdev, mcbsp);
 798
 799         ret = omap_mcbsp_init(pdev);
 800         if (!ret)
 801                 return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai);
 802
 803         return ret;
 804 }
 805
 806 static int __devexit asoc_mcbsp_remove(struct platform_device *pdev)
 807 {
 808         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 809
 810         snd_soc_unregister_dai(&pdev->dev);
 811
 812         if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 813                 mcbsp->pdata->ops->free(mcbsp->id);
 814
 815         omap_mcbsp_sysfs_remove(mcbsp);
 816
 817         clk_put(mcbsp->fclk);
 818
 819         platform_set_drvdata(pdev, NULL);
 820
 821         return 0;
 822 }
 823
 824 static struct platform_driver asoc_mcbsp_driver = {
 825         .driver = {
 826                         .name = "omap-mcbsp",
 827                         .owner = THIS_MODULE,
 828                         .of_match_table = omap_mcbsp_of_match,
 829         },
 830
 831         .probe = asoc_mcbsp_probe,
 832         .remove = __devexit_p(asoc_mcbsp_remove),
 833 };
 834
 835 module_platform_driver(asoc_mcbsp_driver);
 836
 837 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
 838 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 839 MODULE_LICENSE("GPL");
 840 MODULE_ALIAS("platform:omap-mcbsp");