2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/of_address.h>
42 #include <linux/of_irq.h>
43 #include <linux/of_platform.h>
45 #include <sound/core.h>
46 #include <sound/pcm.h>
47 #include <sound/pcm_params.h>
48 #include <sound/initval.h>
49 #include <sound/soc.h>
50 #include <sound/dmaengine_pcm.h>
56 #define read_ssi(addr) in_be32(addr)
57 #define write_ssi(val, addr) out_be32(addr, val)
58 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
60 #define read_ssi(addr) readl(addr)
61 #define write_ssi(val, addr) writel(val, addr)
63 * FIXME: Proper locking should be added at write_ssi_mask caller level
64 * to ensure this register read/modify/write sequence is race free.
66 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
68 u32 val = readl(addr);
69 val = (val & ~clear) | set;
75 * FSLSSI_I2S_RATES: sample rates supported by the I2S
77 * This driver currently only supports the SSI running in I2S slave mode,
78 * which means the codec determines the sample rate. Therefore, we tell
79 * ALSA that we support all rates and let the codec driver decide what rates
80 * are really supported.
82 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
85 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
87 * This driver currently only supports the SSI running in I2S slave mode.
89 * The SSI has a limitation in that the samples must be in the same byte
90 * order as the host CPU. This is because when multiple bytes are written
91 * to the STX register, the bytes and bits must be written in the same
92 * order. The STX is a shift register, so all the bits need to be aligned
93 * (bit-endianness must match byte-endianness). Processors typically write
94 * the bits within a byte in the same order that the bytes of a word are
95 * written in. So if the host CPU is big-endian, then only big-endian
96 * samples will be written to STX properly.
99 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
100 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
101 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
103 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
104 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
105 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
108 /* SIER bitflag of interrupts to enable */
109 #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \
110 CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \
111 CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \
112 CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \
113 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)
116 * fsl_ssi_private: per-SSI private data
118 * @ssi: pointer to the SSI's registers
119 * @ssi_phys: physical address of the SSI registers
120 * @irq: IRQ of this SSI
121 * @first_stream: pointer to the stream that was opened first
122 * @second_stream: pointer to second stream
123 * @playback: the number of playback streams opened
124 * @capture: the number of capture streams opened
125 * @cpu_dai: the CPU DAI for this device
126 * @dev_attr: the sysfs device attribute structure
127 * @stats: SSI statistics
128 * @name: name for this device
130 struct fsl_ssi_private {
131 struct ccsr_ssi __iomem *ssi;
134 struct snd_pcm_substream *first_stream;
135 struct snd_pcm_substream *second_stream;
136 unsigned int fifo_depth;
137 struct snd_soc_dai_driver cpu_dai_drv;
138 struct device_attribute dev_attr;
139 struct platform_device *pdev;
146 struct snd_dmaengine_dai_dma_data dma_params_tx;
147 struct snd_dmaengine_dai_dma_data dma_params_rx;
148 struct imx_dma_data filter_data_tx;
149 struct imx_dma_data filter_data_rx;
150 struct imx_pcm_fiq_params fiq_params;
180 * fsl_ssi_isr: SSI interrupt handler
182 * Although it's possible to use the interrupt handler to send and receive
183 * data to/from the SSI, we use the DMA instead. Programming is more
184 * complicated, but the performance is much better.
186 * This interrupt handler is used only to gather statistics.
188 * @irq: IRQ of the SSI device
189 * @dev_id: pointer to the ssi_private structure for this SSI device
191 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
193 struct fsl_ssi_private *ssi_private = dev_id;
194 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
195 irqreturn_t ret = IRQ_NONE;
199 /* We got an interrupt, so read the status register to see what we
200 were interrupted for. We mask it with the Interrupt Enable register
201 so that we only check for events that we're interested in.
203 sisr = read_ssi(&ssi->sisr) & SIER_FLAGS;
205 if (sisr & CCSR_SSI_SISR_RFRC) {
206 ssi_private->stats.rfrc++;
207 sisr2 |= CCSR_SSI_SISR_RFRC;
211 if (sisr & CCSR_SSI_SISR_TFRC) {
212 ssi_private->stats.tfrc++;
213 sisr2 |= CCSR_SSI_SISR_TFRC;
217 if (sisr & CCSR_SSI_SISR_CMDAU) {
218 ssi_private->stats.cmdau++;
222 if (sisr & CCSR_SSI_SISR_CMDDU) {
223 ssi_private->stats.cmddu++;
227 if (sisr & CCSR_SSI_SISR_RXT) {
228 ssi_private->stats.rxt++;
232 if (sisr & CCSR_SSI_SISR_RDR1) {
233 ssi_private->stats.rdr1++;
237 if (sisr & CCSR_SSI_SISR_RDR0) {
238 ssi_private->stats.rdr0++;
242 if (sisr & CCSR_SSI_SISR_TDE1) {
243 ssi_private->stats.tde1++;
247 if (sisr & CCSR_SSI_SISR_TDE0) {
248 ssi_private->stats.tde0++;
252 if (sisr & CCSR_SSI_SISR_ROE1) {
253 ssi_private->stats.roe1++;
254 sisr2 |= CCSR_SSI_SISR_ROE1;
258 if (sisr & CCSR_SSI_SISR_ROE0) {
259 ssi_private->stats.roe0++;
260 sisr2 |= CCSR_SSI_SISR_ROE0;
264 if (sisr & CCSR_SSI_SISR_TUE1) {
265 ssi_private->stats.tue1++;
266 sisr2 |= CCSR_SSI_SISR_TUE1;
270 if (sisr & CCSR_SSI_SISR_TUE0) {
271 ssi_private->stats.tue0++;
272 sisr2 |= CCSR_SSI_SISR_TUE0;
276 if (sisr & CCSR_SSI_SISR_TFS) {
277 ssi_private->stats.tfs++;
281 if (sisr & CCSR_SSI_SISR_RFS) {
282 ssi_private->stats.rfs++;
286 if (sisr & CCSR_SSI_SISR_TLS) {
287 ssi_private->stats.tls++;
291 if (sisr & CCSR_SSI_SISR_RLS) {
292 ssi_private->stats.rls++;
296 if (sisr & CCSR_SSI_SISR_RFF1) {
297 ssi_private->stats.rff1++;
301 if (sisr & CCSR_SSI_SISR_RFF0) {
302 ssi_private->stats.rff0++;
306 if (sisr & CCSR_SSI_SISR_TFE1) {
307 ssi_private->stats.tfe1++;
311 if (sisr & CCSR_SSI_SISR_TFE0) {
312 ssi_private->stats.tfe0++;
316 /* Clear the bits that we set */
318 write_ssi(sisr2, &ssi->sisr);
323 static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
325 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
328 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
330 if (ssi_private->imx_ac97)
331 i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
333 i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
336 * Section 16.5 of the MPC8610 reference manual says that the SSI needs
337 * to be disabled before updating the registers we set here.
339 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
342 * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
343 * enable the transmit and receive FIFO.
345 * FIXME: Little-endian samples require a different shift dir
347 write_ssi_mask(&ssi->scr,
348 CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
349 CCSR_SSI_SCR_TFR_CLK_DIS |
351 (synchronous ? CCSR_SSI_SCR_SYN : 0));
353 write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
354 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
355 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
357 write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
358 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
359 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
361 * The DC and PM bits are only used if the SSI is the clock master.
365 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
366 * use FIFO 1. We program the transmit water to signal a DMA transfer
367 * if there are only two (or fewer) elements left in the FIFO. Two
368 * elements equals one frame (left channel, right channel). This value,
369 * however, depends on the depth of the transmit buffer.
371 * We set the watermark on the same level as the DMA burstsize. For
372 * fiq it is probably better to use the biggest possible watermark
375 if (ssi_private->use_dma)
376 wm = ssi_private->fifo_depth - 2;
378 wm = ssi_private->fifo_depth;
380 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
381 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
385 * For ac97 interrupts are enabled with the startup of the substream
386 * because it is also running without an active substream. Normally SSI
387 * is only enabled when there is a substream.
389 if (ssi_private->imx_ac97) {
391 * Setup the clock control register
393 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
395 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
399 * Enable AC97 mode and startup the SSI
401 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
403 write_ssi(0xff, &ssi->saccdis);
404 write_ssi(0x300, &ssi->saccen);
407 * Enable SSI, Transmit and Receive
409 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
410 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
412 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
420 * fsl_ssi_startup: create a new substream
422 * This is the first function called when a stream is opened.
424 * If this is the first stream open, then grab the IRQ and program most of
427 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
428 struct snd_soc_dai *dai)
430 struct snd_soc_pcm_runtime *rtd = substream->private_data;
431 struct fsl_ssi_private *ssi_private =
432 snd_soc_dai_get_drvdata(rtd->cpu_dai);
433 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
436 * If this is the first stream opened, then request the IRQ
437 * and initialize the SSI registers.
439 if (!ssi_private->first_stream) {
440 ssi_private->first_stream = substream;
443 * fsl_ssi_setup was already called by ac97_init earlier if
444 * the driver is in ac97 mode.
446 if (!ssi_private->imx_ac97)
447 fsl_ssi_setup(ssi_private);
450 struct snd_pcm_runtime *first_runtime =
451 ssi_private->first_stream->runtime;
453 * This is the second stream open, and we're in
454 * synchronous mode, so we need to impose sample
455 * sample size constraints. This is because STCCR is
456 * used for playback and capture in synchronous mode,
457 * so there's no way to specify different word
460 * Note that this can cause a race condition if the
461 * second stream is opened before the first stream is
462 * fully initialized. We provide some protection by
463 * checking to make sure the first stream is
464 * initialized, but it's not perfect. ALSA sometimes
465 * re-initializes the driver with a different sample
466 * rate or size. If the second stream is opened
467 * before the first stream has received its final
468 * parameters, then the second stream may be
469 * constrained to the wrong sample rate or size.
471 if (first_runtime->sample_bits) {
472 snd_pcm_hw_constraint_minmax(substream->runtime,
473 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
474 first_runtime->sample_bits,
475 first_runtime->sample_bits);
479 ssi_private->second_stream = substream;
486 * fsl_ssi_hw_params - program the sample size
488 * Most of the SSI registers have been programmed in the startup function,
489 * but the word length must be programmed here. Unfortunately, programming
490 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
491 * cause a problem with supporting simultaneous playback and capture. If
492 * the SSI is already playing a stream, then that stream may be temporarily
493 * stopped when you start capture.
495 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
498 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
499 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
501 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
502 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
503 unsigned int sample_size =
504 snd_pcm_format_width(params_format(hw_params));
505 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
506 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
509 * If we're in synchronous mode, and the SSI is already enabled,
510 * then STCCR is already set properly.
512 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
516 * FIXME: The documentation says that SxCCR[WL] should not be
517 * modified while the SSI is enabled. The only time this can
518 * happen is if we're trying to do simultaneous playback and
519 * capture in asynchronous mode. Unfortunately, I have been enable
520 * to get that to work at all on the P1022DS. Therefore, we don't
521 * bother to disable/enable the SSI when setting SxCCR[WL], because
522 * the SSI will stop anyway. Maybe one day, this will get fixed.
525 /* In synchronous mode, the SSI uses STCCR for capture */
526 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
527 ssi_private->cpu_dai_drv.symmetric_rates)
528 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
530 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
536 * fsl_ssi_trigger: start and stop the DMA transfer.
538 * This function is called by ALSA to start, stop, pause, and resume the DMA
541 * The DMA channel is in external master start and pause mode, which
542 * means the SSI completely controls the flow of data.
544 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
545 struct snd_soc_dai *dai)
547 struct snd_soc_pcm_runtime *rtd = substream->private_data;
548 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
549 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
550 unsigned int sier_bits;
553 * Enable only the interrupts and DMA requests
554 * that are needed for the channel. As the fiq
555 * is polling for this bits, we have to ensure
556 * that this are aligned with the preallocated
560 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
561 if (ssi_private->use_dma)
562 sier_bits = SIER_FLAGS;
564 sier_bits = CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN;
566 if (ssi_private->use_dma)
567 sier_bits = SIER_FLAGS;
569 sier_bits = CCSR_SSI_SIER_RIE | CCSR_SSI_SIER_RFF0_EN;
573 case SNDRV_PCM_TRIGGER_START:
574 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
575 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
576 write_ssi_mask(&ssi->scr, 0,
577 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
579 write_ssi_mask(&ssi->scr, 0,
580 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
583 case SNDRV_PCM_TRIGGER_STOP:
584 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
585 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
586 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
588 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
590 if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
591 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0)
592 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
599 write_ssi(sier_bits, &ssi->sier);
605 * fsl_ssi_shutdown: shutdown the SSI
607 * Shutdown the SSI if there are no other substreams open.
609 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
610 struct snd_soc_dai *dai)
612 struct snd_soc_pcm_runtime *rtd = substream->private_data;
613 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
615 if (ssi_private->first_stream == substream)
616 ssi_private->first_stream = ssi_private->second_stream;
618 ssi_private->second_stream = NULL;
621 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
623 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
625 if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
626 dai->playback_dma_data = &ssi_private->dma_params_tx;
627 dai->capture_dma_data = &ssi_private->dma_params_rx;
633 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
634 .startup = fsl_ssi_startup,
635 .hw_params = fsl_ssi_hw_params,
636 .shutdown = fsl_ssi_shutdown,
637 .trigger = fsl_ssi_trigger,
640 /* Template for the CPU dai driver structure */
641 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
642 .probe = fsl_ssi_dai_probe,
644 /* The SSI does not support monaural audio. */
647 .rates = FSLSSI_I2S_RATES,
648 .formats = FSLSSI_I2S_FORMATS,
653 .rates = FSLSSI_I2S_RATES,
654 .formats = FSLSSI_I2S_FORMATS,
656 .ops = &fsl_ssi_dai_ops,
659 static const struct snd_soc_component_driver fsl_ssi_component = {
664 * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit.
666 * This function is called by ALSA to start, stop, pause, and resume the
669 static int fsl_ssi_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
670 struct snd_soc_dai *dai)
672 struct snd_soc_pcm_runtime *rtd = substream->private_data;
673 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(
675 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
678 case SNDRV_PCM_TRIGGER_START:
679 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
680 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
681 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TIE |
682 CCSR_SSI_SIER_TFE0_EN);
684 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RIE |
685 CCSR_SSI_SIER_RFF0_EN);
688 case SNDRV_PCM_TRIGGER_STOP:
689 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
690 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
691 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TIE |
692 CCSR_SSI_SIER_TFE0_EN, 0);
694 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RIE |
695 CCSR_SSI_SIER_RFF0_EN, 0);
702 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
703 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
705 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
710 static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops = {
711 .startup = fsl_ssi_startup,
712 .shutdown = fsl_ssi_shutdown,
713 .trigger = fsl_ssi_ac97_trigger,
716 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
719 .stream_name = "AC97 Playback",
722 .rates = SNDRV_PCM_RATE_8000_48000,
723 .formats = SNDRV_PCM_FMTBIT_S16_LE,
726 .stream_name = "AC97 Capture",
729 .rates = SNDRV_PCM_RATE_48000,
730 .formats = SNDRV_PCM_FMTBIT_S16_LE,
732 .ops = &fsl_ssi_ac97_dai_ops,
736 static struct fsl_ssi_private *fsl_ac97_data;
738 static void fsl_ssi_ac97_init(void)
740 fsl_ssi_setup(fsl_ac97_data);
743 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
746 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
755 write_ssi(lreg, &ssi->sacadd);
758 write_ssi(lval , &ssi->sacdat);
760 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
765 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
768 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
770 unsigned short val = -1;
773 lreg = (reg & 0x7f) << 12;
774 write_ssi(lreg, &ssi->sacadd);
775 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
780 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
785 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
786 .read = fsl_ssi_ac97_read,
787 .write = fsl_ssi_ac97_write,
790 /* Show the statistics of a flag only if its interrupt is enabled. The
791 * compiler will optimze this code to a no-op if the interrupt is not
794 #define SIER_SHOW(flag, name) \
796 if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \
797 length += sprintf(buf + length, #name "=%u\n", \
798 ssi_private->stats.name); \
803 * fsl_sysfs_ssi_show: display SSI statistics
805 * Display the statistics for the current SSI device. To avoid confusion,
806 * we only show those counts that are enabled.
808 static ssize_t fsl_sysfs_ssi_show(struct device *dev,
809 struct device_attribute *attr, char *buf)
811 struct fsl_ssi_private *ssi_private =
812 container_of(attr, struct fsl_ssi_private, dev_attr);
815 SIER_SHOW(RFRC_EN, rfrc);
816 SIER_SHOW(TFRC_EN, tfrc);
817 SIER_SHOW(CMDAU_EN, cmdau);
818 SIER_SHOW(CMDDU_EN, cmddu);
819 SIER_SHOW(RXT_EN, rxt);
820 SIER_SHOW(RDR1_EN, rdr1);
821 SIER_SHOW(RDR0_EN, rdr0);
822 SIER_SHOW(TDE1_EN, tde1);
823 SIER_SHOW(TDE0_EN, tde0);
824 SIER_SHOW(ROE1_EN, roe1);
825 SIER_SHOW(ROE0_EN, roe0);
826 SIER_SHOW(TUE1_EN, tue1);
827 SIER_SHOW(TUE0_EN, tue0);
828 SIER_SHOW(TFS_EN, tfs);
829 SIER_SHOW(RFS_EN, rfs);
830 SIER_SHOW(TLS_EN, tls);
831 SIER_SHOW(RLS_EN, rls);
832 SIER_SHOW(RFF1_EN, rff1);
833 SIER_SHOW(RFF0_EN, rff0);
834 SIER_SHOW(TFE1_EN, tfe1);
835 SIER_SHOW(TFE0_EN, tfe0);
841 * Make every character in a string lower-case
843 static void make_lowercase(char *s)
849 if ((c >= 'A') && (c <= 'Z'))
850 *p = c + ('a' - 'A');
855 static int fsl_ssi_probe(struct platform_device *pdev)
857 struct fsl_ssi_private *ssi_private;
859 struct device_attribute *dev_attr = NULL;
860 struct device_node *np = pdev->dev.of_node;
861 const char *p, *sprop;
862 const uint32_t *iprop;
868 /* SSIs that are not connected on the board should have a
869 * status = "disabled"
870 * property in their device tree nodes.
872 if (!of_device_is_available(np))
875 /* We only support the SSI in "I2S Slave" mode */
876 sprop = of_get_property(np, "fsl,mode", NULL);
878 dev_err(&pdev->dev, "fsl,mode property is necessary\n");
881 if (!strcmp(sprop, "ac97-slave")) {
883 } else if (strcmp(sprop, "i2s-slave")) {
884 dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop);
888 /* The DAI name is the last part of the full name of the node. */
889 p = strrchr(np->full_name, '/') + 1;
890 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
893 dev_err(&pdev->dev, "could not allocate DAI object\n");
897 strcpy(ssi_private->name, p);
899 ssi_private->use_dma = !of_property_read_bool(np,
900 "fsl,fiq-stream-filter");
903 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
904 sizeof(fsl_ssi_ac97_dai));
906 fsl_ac97_data = ssi_private;
907 ssi_private->imx_ac97 = true;
909 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
911 /* Initialize this copy of the CPU DAI driver structure */
912 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
913 sizeof(fsl_ssi_dai_template));
915 ssi_private->cpu_dai_drv.name = ssi_private->name;
917 /* Get the addresses and IRQ */
918 ret = of_address_to_resource(np, 0, &res);
920 dev_err(&pdev->dev, "could not determine device resources\n");
923 ssi_private->ssi = of_iomap(np, 0);
924 if (!ssi_private->ssi) {
925 dev_err(&pdev->dev, "could not map device resources\n");
928 ssi_private->ssi_phys = res.start;
930 ssi_private->irq = irq_of_parse_and_map(np, 0);
931 if (!ssi_private->irq) {
932 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
936 /* Are the RX and the TX clocks locked? */
937 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL))
938 ssi_private->cpu_dai_drv.symmetric_rates = 1;
940 /* Determine the FIFO depth. */
941 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
943 ssi_private->fifo_depth = be32_to_cpup(iprop);
945 /* Older 8610 DTs didn't have the fifo-depth property */
946 ssi_private->fifo_depth = 8;
948 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) {
950 ssi_private->ssi_on_imx = true;
952 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
953 if (IS_ERR(ssi_private->clk)) {
954 ret = PTR_ERR(ssi_private->clk);
955 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
958 ret = clk_prepare_enable(ssi_private->clk);
960 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
966 * We have burstsize be "fifo_depth - 2" to match the SSI
967 * watermark setting in fsl_ssi_startup().
969 ssi_private->dma_params_tx.maxburst =
970 ssi_private->fifo_depth - 2;
971 ssi_private->dma_params_rx.maxburst =
972 ssi_private->fifo_depth - 2;
973 ssi_private->dma_params_tx.addr =
974 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
975 ssi_private->dma_params_rx.addr =
976 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
977 ssi_private->dma_params_tx.filter_data =
978 &ssi_private->filter_data_tx;
979 ssi_private->dma_params_rx.filter_data =
980 &ssi_private->filter_data_rx;
981 if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
982 ssi_private->use_dma) {
984 * FIXME: This is a temporary solution until all
985 * necessary dma drivers support the generic dma
988 ret = of_property_read_u32_array(pdev->dev.of_node,
989 "fsl,ssi-dma-events", dma_events, 2);
990 if (ret && ssi_private->use_dma) {
991 dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
996 shared = of_device_is_compatible(of_get_parent(np),
999 imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
1000 dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1001 imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
1002 dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1003 } else if (ssi_private->use_dma) {
1004 /* The 'name' should not have any slashes in it. */
1005 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1006 fsl_ssi_isr, 0, ssi_private->name,
1009 dev_err(&pdev->dev, "could not claim irq %u\n",
1015 /* Initialize the the device_attribute structure */
1016 dev_attr = &ssi_private->dev_attr;
1017 sysfs_attr_init(&dev_attr->attr);
1018 dev_attr->attr.name = "statistics";
1019 dev_attr->attr.mode = S_IRUGO;
1020 dev_attr->show = fsl_sysfs_ssi_show;
1022 ret = device_create_file(&pdev->dev, dev_attr);
1024 dev_err(&pdev->dev, "could not create sysfs %s file\n",
1025 ssi_private->dev_attr.attr.name);
1029 /* Register with ASoC */
1030 dev_set_drvdata(&pdev->dev, ssi_private);
1032 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1033 &ssi_private->cpu_dai_drv, 1);
1035 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1039 if (ssi_private->ssi_on_imx) {
1040 if (!ssi_private->use_dma) {
1043 * Some boards use an incompatible codec. To get it
1044 * working, we are using imx-fiq-pcm-audio, that
1045 * can handle those codecs. DMA is not possible in this
1049 ssi_private->fiq_params.irq = ssi_private->irq;
1050 ssi_private->fiq_params.base = ssi_private->ssi;
1051 ssi_private->fiq_params.dma_params_rx =
1052 &ssi_private->dma_params_rx;
1053 ssi_private->fiq_params.dma_params_tx =
1054 &ssi_private->dma_params_tx;
1056 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1060 ret = imx_pcm_dma_init(pdev);
1067 * If codec-handle property is missing from SSI node, we assume
1068 * that the machine driver uses new binding which does not require
1069 * SSI driver to trigger machine driver's probe.
1071 if (!of_get_property(np, "codec-handle", NULL)) {
1072 ssi_private->new_binding = true;
1076 /* Trigger the machine driver's probe function. The platform driver
1077 * name of the machine driver is taken from /compatible property of the
1078 * device tree. We also pass the address of the CPU DAI driver
1081 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1082 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1083 p = strrchr(sprop, ',');
1086 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1087 make_lowercase(name);
1090 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1091 if (IS_ERR(ssi_private->pdev)) {
1092 ret = PTR_ERR(ssi_private->pdev);
1093 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1098 if (ssi_private->imx_ac97)
1099 fsl_ssi_ac97_init();
1104 if (ssi_private->ssi_on_imx)
1105 imx_pcm_dma_exit(pdev);
1106 snd_soc_unregister_component(&pdev->dev);
1109 device_remove_file(&pdev->dev, dev_attr);
1112 if (ssi_private->ssi_on_imx)
1113 clk_disable_unprepare(ssi_private->clk);
1116 irq_dispose_mapping(ssi_private->irq);
1121 static int fsl_ssi_remove(struct platform_device *pdev)
1123 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1125 if (!ssi_private->new_binding)
1126 platform_device_unregister(ssi_private->pdev);
1127 if (ssi_private->ssi_on_imx)
1128 imx_pcm_dma_exit(pdev);
1129 snd_soc_unregister_component(&pdev->dev);
1130 device_remove_file(&pdev->dev, &ssi_private->dev_attr);
1131 if (ssi_private->ssi_on_imx)
1132 clk_disable_unprepare(ssi_private->clk);
1133 irq_dispose_mapping(ssi_private->irq);
1138 static const struct of_device_id fsl_ssi_ids[] = {
1139 { .compatible = "fsl,mpc8610-ssi", },
1140 { .compatible = "fsl,imx21-ssi", },
1143 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
1145 static struct platform_driver fsl_ssi_driver = {
1147 .name = "fsl-ssi-dai",
1148 .owner = THIS_MODULE,
1149 .of_match_table = fsl_ssi_ids,
1151 .probe = fsl_ssi_probe,
1152 .remove = fsl_ssi_remove,
1155 module_platform_driver(fsl_ssi_driver);
1157 MODULE_ALIAS("platform:fsl-ssi-dai");
1158 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1159 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1160 MODULE_LICENSE("GPL v2");