2 * Freescale DMA ALSA SoC PCM driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
12 * This driver implements ASoC support for the Elo DMA controller, which is
13 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
14 * the PCM driver is what handles the DMA buffer.
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/delay.h>
23 #include <linux/gfp.h>
24 #include <linux/of_platform.h>
25 #include <linux/list.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
35 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */
38 * The formats that the DMA controller supports, which is anything
39 * that is 8, 16, or 32 bits.
41 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
42 SNDRV_PCM_FMTBIT_U8 | \
43 SNDRV_PCM_FMTBIT_S16_LE | \
44 SNDRV_PCM_FMTBIT_S16_BE | \
45 SNDRV_PCM_FMTBIT_U16_LE | \
46 SNDRV_PCM_FMTBIT_U16_BE | \
47 SNDRV_PCM_FMTBIT_S24_LE | \
48 SNDRV_PCM_FMTBIT_S24_BE | \
49 SNDRV_PCM_FMTBIT_U24_LE | \
50 SNDRV_PCM_FMTBIT_U24_BE | \
51 SNDRV_PCM_FMTBIT_S32_LE | \
52 SNDRV_PCM_FMTBIT_S32_BE | \
53 SNDRV_PCM_FMTBIT_U32_LE | \
54 SNDRV_PCM_FMTBIT_U32_BE)
56 #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
57 SNDRV_PCM_RATE_CONTINUOUS)
60 struct snd_soc_platform_driver dai;
61 dma_addr_t ssi_stx_phys;
62 dma_addr_t ssi_srx_phys;
63 struct ccsr_dma_channel __iomem *channel;
70 * The number of DMA links to use. Two is the bare minimum, but if you
71 * have really small links you might need more.
73 #define NUM_DMA_LINKS 2
75 /** fsl_dma_private: p-substream DMA data
77 * Each substream has a 1-to-1 association with a DMA channel.
79 * The link[] array is first because it needs to be aligned on a 32-byte
80 * boundary, so putting it first will ensure alignment without padding the
83 * @link[]: array of link descriptors
84 * @dma_channel: pointer to the DMA channel's registers
85 * @irq: IRQ for this DMA channel
86 * @substream: pointer to the substream object, needed by the ISR
87 * @ssi_sxx_phys: bus address of the STX or SRX register to use
88 * @ld_buf_phys: physical address of the LD buffer
89 * @current_link: index into link[] of the link currently being processed
90 * @dma_buf_phys: physical address of the DMA buffer
91 * @dma_buf_next: physical address of the next period to process
92 * @dma_buf_end: physical address of the byte after the end of the DMA
93 * @buffer period_size: the size of a single period
94 * @num_periods: the number of periods in the DMA buffer
96 struct fsl_dma_private {
97 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS];
98 struct ccsr_dma_channel __iomem *dma_channel;
100 struct snd_pcm_substream *substream;
101 dma_addr_t ssi_sxx_phys;
102 dma_addr_t ld_buf_phys;
103 unsigned int current_link;
104 dma_addr_t dma_buf_phys;
105 dma_addr_t dma_buf_next;
106 dma_addr_t dma_buf_end;
108 unsigned int num_periods;
112 * fsl_dma_hardare: define characteristics of the PCM hardware.
114 * The PCM hardware is the Freescale DMA controller. This structure defines
115 * the capabilities of that hardware.
117 * Since the sampling rate and data format are not controlled by the DMA
118 * controller, we specify no limits for those values. The only exception is
119 * period_bytes_min, which is set to a reasonably low value to prevent the
120 * DMA controller from generating too many interrupts per second.
122 * Since each link descriptor has a 32-bit byte count field, we set
123 * period_bytes_max to the largest 32-bit number. We also have no maximum
126 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a
127 * limitation in the SSI driver requires the sample rates for playback and
128 * capture to be the same.
130 static const struct snd_pcm_hardware fsl_dma_hardware = {
132 .info = SNDRV_PCM_INFO_INTERLEAVED |
133 SNDRV_PCM_INFO_MMAP |
134 SNDRV_PCM_INFO_MMAP_VALID |
135 SNDRV_PCM_INFO_JOINT_DUPLEX |
136 SNDRV_PCM_INFO_PAUSE,
137 .formats = FSLDMA_PCM_FORMATS,
138 .rates = FSLDMA_PCM_RATES,
141 .period_bytes_min = 512, /* A reasonable limit */
142 .period_bytes_max = (u32) -1,
143 .periods_min = NUM_DMA_LINKS,
144 .periods_max = (unsigned int) -1,
145 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */
149 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted
151 * This function should be called by the ISR whenever the DMA controller
152 * halts data transfer.
154 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream)
158 snd_pcm_stream_lock_irqsave(substream, flags);
160 if (snd_pcm_running(substream))
161 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
163 snd_pcm_stream_unlock_irqrestore(substream, flags);
167 * fsl_dma_update_pointers - update LD pointers to point to the next period
169 * As each period is completed, this function changes the the link
170 * descriptor pointers for that period to point to the next period.
172 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private)
174 struct fsl_dma_link_descriptor *link =
175 &dma_private->link[dma_private->current_link];
177 /* Update our link descriptors to point to the next period. On a 36-bit
178 * system, we also need to update the ESAD bits. We also set (keep) the
179 * snoop bits. See the comments in fsl_dma_hw_params() about snooping.
181 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
182 link->source_addr = cpu_to_be32(dma_private->dma_buf_next);
183 #ifdef CONFIG_PHYS_64BIT
184 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
185 upper_32_bits(dma_private->dma_buf_next));
188 link->dest_addr = cpu_to_be32(dma_private->dma_buf_next);
189 #ifdef CONFIG_PHYS_64BIT
190 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
191 upper_32_bits(dma_private->dma_buf_next));
195 /* Update our variables for next time */
196 dma_private->dma_buf_next += dma_private->period_size;
198 if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
199 dma_private->dma_buf_next = dma_private->dma_buf_phys;
201 if (++dma_private->current_link >= NUM_DMA_LINKS)
202 dma_private->current_link = 0;
206 * fsl_dma_isr: interrupt handler for the DMA controller
208 * @irq: IRQ of the DMA channel
209 * @dev_id: pointer to the dma_private structure for this DMA channel
211 static irqreturn_t fsl_dma_isr(int irq, void *dev_id)
213 struct fsl_dma_private *dma_private = dev_id;
214 struct snd_pcm_substream *substream = dma_private->substream;
215 struct snd_soc_pcm_runtime *rtd = substream->private_data;
216 struct device *dev = rtd->platform->dev;
217 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
218 irqreturn_t ret = IRQ_NONE;
221 /* We got an interrupt, so read the status register to see what we
222 were interrupted for.
224 sr = in_be32(&dma_channel->sr);
226 if (sr & CCSR_DMA_SR_TE) {
227 dev_err(dev, "dma transmit error\n");
228 fsl_dma_abort_stream(substream);
229 sr2 |= CCSR_DMA_SR_TE;
233 if (sr & CCSR_DMA_SR_CH)
236 if (sr & CCSR_DMA_SR_PE) {
237 dev_err(dev, "dma programming error\n");
238 fsl_dma_abort_stream(substream);
239 sr2 |= CCSR_DMA_SR_PE;
243 if (sr & CCSR_DMA_SR_EOLNI) {
244 sr2 |= CCSR_DMA_SR_EOLNI;
248 if (sr & CCSR_DMA_SR_CB)
251 if (sr & CCSR_DMA_SR_EOSI) {
252 /* Tell ALSA we completed a period. */
253 snd_pcm_period_elapsed(substream);
256 * Update our link descriptors to point to the next period. We
257 * only need to do this if the number of periods is not equal to
258 * the number of links.
260 if (dma_private->num_periods != NUM_DMA_LINKS)
261 fsl_dma_update_pointers(dma_private);
263 sr2 |= CCSR_DMA_SR_EOSI;
267 if (sr & CCSR_DMA_SR_EOLSI) {
268 sr2 |= CCSR_DMA_SR_EOLSI;
272 /* Clear the bits that we set */
274 out_be32(&dma_channel->sr, sr2);
280 * fsl_dma_new: initialize this PCM driver.
282 * This function is called when the codec driver calls snd_soc_new_pcms(),
283 * once for each .dai_link in the machine driver's snd_soc_card
286 * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which
287 * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM
288 * is specified. Therefore, any DMA buffers we allocate will always be in low
289 * memory, but we support for 36-bit physical addresses anyway.
291 * Regardless of where the memory is actually allocated, since the device can
292 * technically DMA to any 36-bit address, we do need to set the DMA mask to 36.
294 static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai,
297 static u64 fsl_dma_dmamask = DMA_BIT_MASK(36);
300 if (!card->dev->dma_mask)
301 card->dev->dma_mask = &fsl_dma_dmamask;
303 if (!card->dev->coherent_dma_mask)
304 card->dev->coherent_dma_mask = fsl_dma_dmamask;
306 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
307 fsl_dma_hardware.buffer_bytes_max,
308 &pcm->streams[0].substream->dma_buffer);
310 dev_err(card->dev, "can't allocate playback dma buffer\n");
314 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
315 fsl_dma_hardware.buffer_bytes_max,
316 &pcm->streams[1].substream->dma_buffer);
318 snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer);
319 dev_err(card->dev, "can't allocate capture dma buffer\n");
327 * fsl_dma_open: open a new substream.
329 * Each substream has its own DMA buffer.
331 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link
332 * descriptors that ping-pong from one period to the next. For example, if
333 * there are six periods and two link descriptors, this is how they look
334 * before playback starts:
336 * The last link descriptor
337 * ____________ points back to the first
346 * _________________________________________
347 * | | | | | | | The DMA buffer is
348 * | | | | | | | divided into 6 parts
349 * |______|______|______|______|______|______|
351 * and here's how they look after the first period is finished playing:
363 * _________________________________________
366 * |______|______|______|______|______|______|
368 * The first link descriptor now points to the third period. The DMA
369 * controller is currently playing the second period. When it finishes, it
370 * will jump back to the first descriptor and play the third period.
372 * There are four reasons we do this:
374 * 1. The only way to get the DMA controller to automatically restart the
375 * transfer when it gets to the end of the buffer is to use chaining
376 * mode. Basic direct mode doesn't offer that feature.
377 * 2. We need to receive an interrupt at the end of every period. The DMA
378 * controller can generate an interrupt at the end of every link transfer
379 * (aka segment). Making each period into a DMA segment will give us the
380 * interrupts we need.
381 * 3. By creating only two link descriptors, regardless of the number of
382 * periods, we do not need to reallocate the link descriptors if the
383 * number of periods changes.
384 * 4. All of the audio data is still stored in a single, contiguous DMA
385 * buffer, which is what ALSA expects. We're just dividing it into
386 * contiguous parts, and creating a link descriptor for each one.
388 static int fsl_dma_open(struct snd_pcm_substream *substream)
390 struct snd_pcm_runtime *runtime = substream->runtime;
391 struct snd_soc_pcm_runtime *rtd = substream->private_data;
392 struct device *dev = rtd->platform->dev;
393 struct dma_object *dma =
394 container_of(rtd->platform->driver, struct dma_object, dai);
395 struct fsl_dma_private *dma_private;
396 struct ccsr_dma_channel __iomem *dma_channel;
397 dma_addr_t ld_buf_phys;
398 u64 temp_link; /* Pointer to next link descriptor */
400 unsigned int channel;
405 * Reject any DMA buffer whose size is not a multiple of the period
406 * size. We need to make sure that the DMA buffer can be evenly divided
409 ret = snd_pcm_hw_constraint_integer(runtime,
410 SNDRV_PCM_HW_PARAM_PERIODS);
412 dev_err(dev, "invalid buffer size\n");
416 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
419 dev_err(dev, "dma channel already assigned\n");
423 dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private),
424 &ld_buf_phys, GFP_KERNEL);
426 dev_err(dev, "can't allocate dma private data\n");
429 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
430 dma_private->ssi_sxx_phys = dma->ssi_stx_phys;
432 dma_private->ssi_sxx_phys = dma->ssi_srx_phys;
434 dma_private->dma_channel = dma->channel;
435 dma_private->irq = dma->irq;
436 dma_private->substream = substream;
437 dma_private->ld_buf_phys = ld_buf_phys;
438 dma_private->dma_buf_phys = substream->dma_buffer.addr;
440 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private);
442 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
443 dma_private->irq, ret);
444 dma_free_coherent(dev, sizeof(struct fsl_dma_private),
445 dma_private, dma_private->ld_buf_phys);
451 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
452 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
453 runtime->private_data = dma_private;
455 /* Program the fixed DMA controller parameters */
457 dma_channel = dma_private->dma_channel;
459 temp_link = dma_private->ld_buf_phys +
460 sizeof(struct fsl_dma_link_descriptor);
462 for (i = 0; i < NUM_DMA_LINKS; i++) {
463 dma_private->link[i].next = cpu_to_be64(temp_link);
465 temp_link += sizeof(struct fsl_dma_link_descriptor);
467 /* The last link descriptor points to the first */
468 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys);
470 /* Tell the DMA controller where the first link descriptor is */
471 out_be32(&dma_channel->clndar,
472 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys));
473 out_be32(&dma_channel->eclndar,
474 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys));
476 /* The manual says the BCR must be clear before enabling EMP */
477 out_be32(&dma_channel->bcr, 0);
480 * Program the mode register for interrupts, external master control,
481 * and source/destination hold. Also clear the Channel Abort bit.
483 mr = in_be32(&dma_channel->mr) &
484 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE);
487 * We want External Master Start and External Master Pause enabled,
488 * because the SSI is controlling the DMA controller. We want the DMA
489 * controller to be set up in advance, and then we signal only the SSI
490 * to start transferring.
492 * We want End-Of-Segment Interrupts enabled, because this will generate
493 * an interrupt at the end of each segment (each link descriptor
494 * represents one segment). Each DMA segment is the same thing as an
495 * ALSA period, so this is how we get an interrupt at the end of every
498 * We want Error Interrupt enabled, so that we can get an error if
499 * the DMA controller is mis-programmed somehow.
501 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN |
504 /* For playback, we want the destination address to be held. For
505 capture, set the source address to be held. */
506 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
507 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE;
509 out_be32(&dma_channel->mr, mr);
515 * fsl_dma_hw_params: continue initializing the DMA links
517 * This function obtains hardware parameters about the opened stream and
518 * programs the DMA controller accordingly.
520 * One drawback of big-endian is that when copying integers of different
521 * sizes to a fixed-sized register, the address to which the integer must be
522 * copied is dependent on the size of the integer.
524 * For example, if P is the address of a 32-bit register, and X is a 32-bit
525 * integer, then X should be copied to address P. However, if X is a 16-bit
526 * integer, then it should be copied to P+2. If X is an 8-bit register,
527 * then it should be copied to P+3.
529 * So for playback of 8-bit samples, the DMA controller must transfer single
530 * bytes from the DMA buffer to the last byte of the STX0 register, i.e.
531 * offset by 3 bytes. For 16-bit samples, the offset is two bytes.
533 * For 24-bit samples, the offset is 1 byte. However, the DMA controller
534 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4,
535 * and 8 bytes at a time). So we do not support packed 24-bit samples.
536 * 24-bit data must be padded to 32 bits.
538 static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
539 struct snd_pcm_hw_params *hw_params)
541 struct snd_pcm_runtime *runtime = substream->runtime;
542 struct fsl_dma_private *dma_private = runtime->private_data;
543 struct snd_soc_pcm_runtime *rtd = substream->private_data;
544 struct device *dev = rtd->platform->dev;
546 /* Number of bits per sample */
547 unsigned int sample_size =
548 snd_pcm_format_physical_width(params_format(hw_params));
550 /* Number of bytes per frame */
551 unsigned int frame_size = 2 * (sample_size / 8);
553 /* Bus address of SSI STX register */
554 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys;
556 /* Size of the DMA buffer, in bytes */
557 size_t buffer_size = params_buffer_bytes(hw_params);
559 /* Number of bytes per period */
560 size_t period_size = params_period_bytes(hw_params);
562 /* Pointer to next period */
563 dma_addr_t temp_addr = substream->dma_buffer.addr;
565 /* Pointer to DMA controller */
566 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
568 u32 mr; /* DMA Mode Register */
572 /* Initialize our DMA tracking variables */
573 dma_private->period_size = period_size;
574 dma_private->num_periods = params_periods(hw_params);
575 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
576 dma_private->dma_buf_next = dma_private->dma_buf_phys +
577 (NUM_DMA_LINKS * period_size);
579 if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
580 /* This happens if the number of periods == NUM_DMA_LINKS */
581 dma_private->dma_buf_next = dma_private->dma_buf_phys;
583 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
584 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
586 /* Due to a quirk of the SSI's STX register, the target address
587 * for the DMA operations depends on the sample size. So we calculate
588 * that offset here. While we're at it, also tell the DMA controller
589 * how much data to transfer per sample.
591 switch (sample_size) {
593 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
597 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2;
601 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
604 /* We should never get here */
605 dev_err(dev, "unsupported sample size %u\n", sample_size);
610 * BWC should always be a multiple of the frame size. BWC determines
611 * how many bytes are sent/received before the DMA controller checks the
612 * SSI to see if it needs to stop. For playback, the transmit FIFO can
613 * hold three frames, so we want to send two frames at a time. For
614 * capture, the receive FIFO is triggered when it contains one frame, so
615 * we want to receive one frame at a time.
617 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
618 mr |= CCSR_DMA_MR_BWC(2 * frame_size);
620 mr |= CCSR_DMA_MR_BWC(frame_size);
622 out_be32(&dma_channel->mr, mr);
624 for (i = 0; i < NUM_DMA_LINKS; i++) {
625 struct fsl_dma_link_descriptor *link = &dma_private->link[i];
627 link->count = cpu_to_be32(period_size);
629 /* The snoop bit tells the DMA controller whether it should tell
630 * the ECM to snoop during a read or write to an address. For
631 * audio, we use DMA to transfer data between memory and an I/O
632 * device (the SSI's STX0 or SRX0 register). Snooping is only
633 * needed if there is a cache, so we need to snoop memory
634 * addresses only. For playback, that means we snoop the source
635 * but not the destination. For capture, we snoop the
636 * destination but not the source.
638 * Note that failing to snoop properly is unlikely to cause
639 * cache incoherency if the period size is larger than the
640 * size of L1 cache. This is because filling in one period will
641 * flush out the data for the previous period. So if you
642 * increased period_bytes_min to a large enough size, you might
643 * get more performance by not snooping, and you'll still be
644 * okay. You'll need to update fsl_dma_update_pointers() also.
646 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
647 link->source_addr = cpu_to_be32(temp_addr);
648 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
649 upper_32_bits(temp_addr));
651 link->dest_addr = cpu_to_be32(ssi_sxx_phys);
652 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
653 upper_32_bits(ssi_sxx_phys));
655 link->source_addr = cpu_to_be32(ssi_sxx_phys);
656 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
657 upper_32_bits(ssi_sxx_phys));
659 link->dest_addr = cpu_to_be32(temp_addr);
660 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
661 upper_32_bits(temp_addr));
664 temp_addr += period_size;
671 * fsl_dma_pointer: determine the current position of the DMA transfer
673 * This function is called by ALSA when ALSA wants to know where in the
674 * stream buffer the hardware currently is.
676 * For playback, the SAR register contains the physical address of the most
677 * recent DMA transfer. For capture, the value is in the DAR register.
679 * The base address of the buffer is stored in the source_addr field of the
680 * first link descriptor.
682 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream)
684 struct snd_pcm_runtime *runtime = substream->runtime;
685 struct fsl_dma_private *dma_private = runtime->private_data;
686 struct snd_soc_pcm_runtime *rtd = substream->private_data;
687 struct device *dev = rtd->platform->dev;
688 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
690 snd_pcm_uframes_t frames;
692 /* Obtain the current DMA pointer, but don't read the ESAD bits if we
693 * only have 32-bit DMA addresses. This function is typically called
694 * in interrupt context, so we need to optimize it.
696 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
697 position = in_be32(&dma_channel->sar);
698 #ifdef CONFIG_PHYS_64BIT
699 position |= (u64)(in_be32(&dma_channel->satr) &
700 CCSR_DMA_ATR_ESAD_MASK) << 32;
703 position = in_be32(&dma_channel->dar);
704 #ifdef CONFIG_PHYS_64BIT
705 position |= (u64)(in_be32(&dma_channel->datr) &
706 CCSR_DMA_ATR_ESAD_MASK) << 32;
711 * When capture is started, the SSI immediately starts to fill its FIFO.
712 * This means that the DMA controller is not started until the FIFO is
713 * full. However, ALSA calls this function before that happens, when
714 * MR.DAR is still zero. In this case, just return zero to indicate
715 * that nothing has been received yet.
720 if ((position < dma_private->dma_buf_phys) ||
721 (position > dma_private->dma_buf_end)) {
722 dev_err(dev, "dma pointer is out of range, halting stream\n");
723 return SNDRV_PCM_POS_XRUN;
726 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys);
729 * If the current address is just past the end of the buffer, wrap it
732 if (frames == runtime->buffer_size)
739 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params()
741 * Release the resources allocated in fsl_dma_hw_params() and de-program the
744 * This function can be called multiple times.
746 static int fsl_dma_hw_free(struct snd_pcm_substream *substream)
748 struct snd_pcm_runtime *runtime = substream->runtime;
749 struct fsl_dma_private *dma_private = runtime->private_data;
752 struct ccsr_dma_channel __iomem *dma_channel;
754 dma_channel = dma_private->dma_channel;
757 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA);
758 out_be32(&dma_channel->mr, 0);
760 /* Reset all the other registers */
761 out_be32(&dma_channel->sr, -1);
762 out_be32(&dma_channel->clndar, 0);
763 out_be32(&dma_channel->eclndar, 0);
764 out_be32(&dma_channel->satr, 0);
765 out_be32(&dma_channel->sar, 0);
766 out_be32(&dma_channel->datr, 0);
767 out_be32(&dma_channel->dar, 0);
768 out_be32(&dma_channel->bcr, 0);
769 out_be32(&dma_channel->nlndar, 0);
770 out_be32(&dma_channel->enlndar, 0);
777 * fsl_dma_close: close the stream.
779 static int fsl_dma_close(struct snd_pcm_substream *substream)
781 struct snd_pcm_runtime *runtime = substream->runtime;
782 struct fsl_dma_private *dma_private = runtime->private_data;
783 struct snd_soc_pcm_runtime *rtd = substream->private_data;
784 struct device *dev = rtd->platform->dev;
785 struct dma_object *dma =
786 container_of(rtd->platform->driver, struct dma_object, dai);
789 if (dma_private->irq)
790 free_irq(dma_private->irq, dma_private);
792 if (dma_private->ld_buf_phys) {
793 dma_unmap_single(dev, dma_private->ld_buf_phys,
794 sizeof(dma_private->link),
798 /* Deallocate the fsl_dma_private structure */
799 dma_free_coherent(dev, sizeof(struct fsl_dma_private),
800 dma_private, dma_private->ld_buf_phys);
801 substream->runtime->private_data = NULL;
810 * Remove this PCM driver.
812 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm)
814 struct snd_pcm_substream *substream;
817 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
818 substream = pcm->streams[i].substream;
820 snd_dma_free_pages(&substream->dma_buffer);
821 substream->dma_buffer.area = NULL;
822 substream->dma_buffer.addr = 0;
828 * find_ssi_node -- returns the SSI node that points to his DMA channel node
830 * Although this DMA driver attempts to operate independently of the other
831 * devices, it still needs to determine some information about the SSI device
832 * that it's working with. Unfortunately, the device tree does not contain
833 * a pointer from the DMA channel node to the SSI node -- the pointer goes the
834 * other way. So we need to scan the device tree for SSI nodes until we find
835 * the one that points to the given DMA channel node. It's ugly, but at least
836 * it's contained in this one function.
838 static struct device_node *find_ssi_node(struct device_node *dma_channel_np)
840 struct device_node *ssi_np, *np;
842 for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") {
843 /* Check each DMA phandle to see if it points to us. We
844 * assume that device_node pointers are a valid comparison.
846 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0);
847 if (np == dma_channel_np)
850 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0);
851 if (np == dma_channel_np)
858 static struct snd_pcm_ops fsl_dma_ops = {
859 .open = fsl_dma_open,
860 .close = fsl_dma_close,
861 .ioctl = snd_pcm_lib_ioctl,
862 .hw_params = fsl_dma_hw_params,
863 .hw_free = fsl_dma_hw_free,
864 .pointer = fsl_dma_pointer,
867 static int __devinit fsl_soc_dma_probe(struct of_device *of_dev,
868 const struct of_device_id *match)
870 struct dma_object *dma;
871 struct device_node *np = of_dev->dev.of_node;
872 struct device_node *ssi_np;
876 /* Find the SSI node that points to us. */
877 ssi_np = find_ssi_node(np);
879 dev_err(&of_dev->dev, "cannot find parent SSI node\n");
883 ret = of_address_to_resource(ssi_np, 0, &res);
886 dev_err(&of_dev->dev, "could not determine device resources\n");
890 dma = kzalloc(sizeof(*dma) + strlen(np->full_name), GFP_KERNEL);
892 dev_err(&of_dev->dev, "could not allocate dma object\n");
896 strcpy(dma->path, np->full_name);
897 dma->dai.ops = &fsl_dma_ops;
898 dma->dai.pcm_new = fsl_dma_new;
899 dma->dai.pcm_free = fsl_dma_free_dma_buffers;
901 /* Store the SSI-specific information that we need */
902 dma->ssi_stx_phys = res.start + offsetof(struct ccsr_ssi, stx0);
903 dma->ssi_srx_phys = res.start + offsetof(struct ccsr_ssi, srx0);
905 ret = snd_soc_register_platform(&of_dev->dev, &dma->dai);
907 dev_err(&of_dev->dev, "could not register platform\n");
912 dma->channel = of_iomap(np, 0);
913 dma->irq = irq_of_parse_and_map(np, 0);
915 dev_set_drvdata(&of_dev->dev, dma);
920 static int __devexit fsl_soc_dma_remove(struct of_device *of_dev)
922 struct dma_object *dma = dev_get_drvdata(&of_dev->dev);
924 snd_soc_unregister_platform(&of_dev->dev);
925 iounmap(dma->channel);
926 irq_dispose_mapping(dma->irq);
932 static const struct of_device_id fsl_soc_dma_ids[] = {
933 { .compatible = "fsl,ssi-dma-channel", },
936 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids);
938 static struct of_platform_driver fsl_soc_dma_driver = {
940 .name = "fsl-pcm-audio",
941 .owner = THIS_MODULE,
942 .of_match_table = fsl_soc_dma_ids,
944 .probe = fsl_soc_dma_probe,
945 .remove = __devexit_p(fsl_soc_dma_remove),
948 static int __init fsl_soc_dma_init(void)
950 pr_info("Freescale Elo DMA ASoC PCM Driver\n");
952 return of_register_platform_driver(&fsl_soc_dma_driver);
955 static void __exit fsl_soc_dma_exit(void)
957 of_unregister_platform_driver(&fsl_soc_dma_driver);
960 module_init(fsl_soc_dma_init);
961 module_exit(fsl_soc_dma_exit);
963 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
964 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver");
965 MODULE_LICENSE("GPL v2");