Pileus Git - ~andy/linux/blob - sound/soc/codecs/wm8996.c

   1 /*
   2  * wm8996.c - WM8996 audio codec interface
   3  *
   4  * Copyright 2011 Wolfson Microelectronics PLC.
   5  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/completion.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/gcd.h>
  20 #include <linux/gpio.h>
  21 #include <linux/i2c.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <linux/workqueue.h>
  25 #include <sound/core.h>
  26 #include <sound/jack.h>
  27 #include <sound/pcm.h>
  28 #include <sound/pcm_params.h>
  29 #include <sound/soc.h>
  30 #include <sound/initval.h>
  31 #include <sound/tlv.h>
  32 #include <trace/events/asoc.h>
  33
  34 #include <sound/wm8996.h>
  35 #include "wm8996.h"
  36
  37 #define WM8996_AIFS 2
  38
  39 #define HPOUT1L 1
  40 #define HPOUT1R 2
  41 #define HPOUT2L 4
  42 #define HPOUT2R 8
  43
  44 #define WM8996_NUM_SUPPLIES 4
  45 static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
  46         "DBVDD",
  47         "AVDD1",
  48         "AVDD2",
  49         "CPVDD",
  50 };
  51
  52 struct wm8996_priv {
  53         struct snd_soc_codec *codec;
  54
  55         int ldo1ena;
  56
  57         int sysclk;
  58         int sysclk_src;
  59
  60         int fll_src;
  61         int fll_fref;
  62         int fll_fout;
  63
  64         struct completion fll_lock;
  65
  66         u16 dcs_pending;
  67         struct completion dcs_done;
  68
  69         u16 hpout_ena;
  70         u16 hpout_pending;
  71
  72         struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
  73         struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
  74
  75         struct wm8996_pdata pdata;
  76
  77         int rx_rate[WM8996_AIFS];
  78         int bclk_rate[WM8996_AIFS];
  79
  80         /* Platform dependant ReTune mobile configuration */
  81         int num_retune_mobile_texts;
  82         const char **retune_mobile_texts;
  83         int retune_mobile_cfg[2];
  84         struct soc_enum retune_mobile_enum;
  85
  86         struct snd_soc_jack *jack;
  87         bool detecting;
  88         bool jack_mic;
  89         wm8996_polarity_fn polarity_cb;
  90
  91 #ifdef CONFIG_GPIOLIB
  92         struct gpio_chip gpio_chip;
  93 #endif
  94 };
  95
  96 /* We can't use the same notifier block for more than one supply and
  97  * there's no way I can see to get from a callback to the caller
  98  * except container_of().
  99  */
 100 #define WM8996_REGULATOR_EVENT(n) \
 101 static int wm8996_regulator_event_##n(struct notifier_block *nb, \
 102                                     unsigned long event, void *data)    \
 103 { \
 104         struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
 105                                                   disable_nb[n]); \
 106         if (event & REGULATOR_EVENT_DISABLE) { \
 107                 wm8996->codec->cache_sync = 1; \
 108         } \
 109         return 0; \
 110 }
 111
 112 WM8996_REGULATOR_EVENT(0)
 113 WM8996_REGULATOR_EVENT(1)
 114 WM8996_REGULATOR_EVENT(2)
 115 WM8996_REGULATOR_EVENT(3)
 116
 117 static const u16 wm8996_reg[WM8996_MAX_REGISTER] = {
 118         [WM8996_SOFTWARE_RESET] = 0x8996,
 119         [WM8996_POWER_MANAGEMENT_7] = 0x10,
 120         [WM8996_DAC1_HPOUT1_VOLUME] = 0x88,
 121         [WM8996_DAC2_HPOUT2_VOLUME] = 0x88,
 122         [WM8996_DAC1_LEFT_VOLUME] = 0x2c0,
 123         [WM8996_DAC1_RIGHT_VOLUME] = 0x2c0,
 124         [WM8996_DAC2_LEFT_VOLUME] = 0x2c0,
 125         [WM8996_DAC2_RIGHT_VOLUME] = 0x2c0,
 126         [WM8996_OUTPUT1_LEFT_VOLUME] = 0x80,
 127         [WM8996_OUTPUT1_RIGHT_VOLUME] = 0x80,
 128         [WM8996_OUTPUT2_LEFT_VOLUME] = 0x80,
 129         [WM8996_OUTPUT2_RIGHT_VOLUME] = 0x80,
 130         [WM8996_MICBIAS_1] = 0x39,
 131         [WM8996_MICBIAS_2] = 0x39,
 132         [WM8996_LDO_1] = 0x3,
 133         [WM8996_LDO_2] = 0x13,
 134         [WM8996_ACCESSORY_DETECT_MODE_1] = 0x4,
 135         [WM8996_HEADPHONE_DETECT_1] = 0x20,
 136         [WM8996_MIC_DETECT_1] = 0x7600,
 137         [WM8996_MIC_DETECT_2] = 0xbf,
 138         [WM8996_CHARGE_PUMP_1] = 0x1f25,
 139         [WM8996_CHARGE_PUMP_2] = 0xab19,
 140         [WM8996_DC_SERVO_5] = 0x2a2a,
 141         [WM8996_CONTROL_INTERFACE_1] = 0x8004,
 142         [WM8996_CLOCKING_1] = 0x10,
 143         [WM8996_AIF_RATE] = 0x83,
 144         [WM8996_FLL_CONTROL_4] = 0x5dc0,
 145         [WM8996_FLL_CONTROL_5] = 0xc84,
 146         [WM8996_FLL_EFS_2] = 0x2,
 147         [WM8996_AIF1_TX_LRCLK_1] = 0x80,
 148         [WM8996_AIF1_TX_LRCLK_2] = 0x8,
 149         [WM8996_AIF1_RX_LRCLK_1] = 0x80,
 150         [WM8996_AIF1TX_DATA_CONFIGURATION_1] = 0x1818,
 151         [WM8996_AIF1RX_DATA_CONFIGURATION] = 0x1818,
 152         [WM8996_AIF1TX_TEST] = 0x7,
 153         [WM8996_AIF2_TX_LRCLK_1] = 0x80,
 154         [WM8996_AIF2_TX_LRCLK_2] = 0x8,
 155         [WM8996_AIF2_RX_LRCLK_1] = 0x80,
 156         [WM8996_AIF2TX_DATA_CONFIGURATION_1] = 0x1818,
 157         [WM8996_AIF2RX_DATA_CONFIGURATION] = 0x1818,
 158         [WM8996_AIF2TX_TEST] = 0x1,
 159         [WM8996_DSP1_TX_LEFT_VOLUME] = 0xc0,
 160         [WM8996_DSP1_TX_RIGHT_VOLUME] = 0xc0,
 161         [WM8996_DSP1_RX_LEFT_VOLUME] = 0xc0,
 162         [WM8996_DSP1_RX_RIGHT_VOLUME] = 0xc0,
 163         [WM8996_DSP1_TX_FILTERS] = 0x2000,
 164         [WM8996_DSP1_RX_FILTERS_1] = 0x200,
 165         [WM8996_DSP1_RX_FILTERS_2] = 0x10,
 166         [WM8996_DSP1_DRC_1] = 0x98,
 167         [WM8996_DSP1_DRC_2] = 0x845,
 168         [WM8996_DSP1_RX_EQ_GAINS_1] = 0x6318,
 169         [WM8996_DSP1_RX_EQ_GAINS_2] = 0x6300,
 170         [WM8996_DSP1_RX_EQ_BAND_1_A] = 0xfca,
 171         [WM8996_DSP1_RX_EQ_BAND_1_B] = 0x400,
 172         [WM8996_DSP1_RX_EQ_BAND_1_PG] = 0xd8,
 173         [WM8996_DSP1_RX_EQ_BAND_2_A] = 0x1eb5,
 174         [WM8996_DSP1_RX_EQ_BAND_2_B] = 0xf145,
 175         [WM8996_DSP1_RX_EQ_BAND_2_C] = 0xb75,
 176         [WM8996_DSP1_RX_EQ_BAND_2_PG] = 0x1c5,
 177         [WM8996_DSP1_RX_EQ_BAND_3_A] = 0x1c58,
 178         [WM8996_DSP1_RX_EQ_BAND_3_B] = 0xf373,
 179         [WM8996_DSP1_RX_EQ_BAND_3_C] = 0xa54,
 180         [WM8996_DSP1_RX_EQ_BAND_3_PG] = 0x558,
 181         [WM8996_DSP1_RX_EQ_BAND_4_A] = 0x168e,
 182         [WM8996_DSP1_RX_EQ_BAND_4_B] = 0xf829,
 183         [WM8996_DSP1_RX_EQ_BAND_4_C] = 0x7ad,
 184         [WM8996_DSP1_RX_EQ_BAND_4_PG] = 0x1103,
 185         [WM8996_DSP1_RX_EQ_BAND_5_A] = 0x564,
 186         [WM8996_DSP1_RX_EQ_BAND_5_B] = 0x559,
 187         [WM8996_DSP1_RX_EQ_BAND_5_PG] = 0x4000,
 188         [WM8996_DSP2_TX_LEFT_VOLUME] = 0xc0,
 189         [WM8996_DSP2_TX_RIGHT_VOLUME] = 0xc0,
 190         [WM8996_DSP2_RX_LEFT_VOLUME] = 0xc0,
 191         [WM8996_DSP2_RX_RIGHT_VOLUME] = 0xc0,
 192         [WM8996_DSP2_TX_FILTERS] = 0x2000,
 193         [WM8996_DSP2_RX_FILTERS_1] = 0x200,
 194         [WM8996_DSP2_RX_FILTERS_2] = 0x10,
 195         [WM8996_DSP2_DRC_1] = 0x98,
 196         [WM8996_DSP2_DRC_2] = 0x845,
 197         [WM8996_DSP2_RX_EQ_GAINS_1] = 0x6318,
 198         [WM8996_DSP2_RX_EQ_GAINS_2] = 0x6300,
 199         [WM8996_DSP2_RX_EQ_BAND_1_A] = 0xfca,
 200         [WM8996_DSP2_RX_EQ_BAND_1_B] = 0x400,
 201         [WM8996_DSP2_RX_EQ_BAND_1_PG] = 0xd8,
 202         [WM8996_DSP2_RX_EQ_BAND_2_A] = 0x1eb5,
 203         [WM8996_DSP2_RX_EQ_BAND_2_B] = 0xf145,
 204         [WM8996_DSP2_RX_EQ_BAND_2_C] = 0xb75,
 205         [WM8996_DSP2_RX_EQ_BAND_2_PG] = 0x1c5,
 206         [WM8996_DSP2_RX_EQ_BAND_3_A] = 0x1c58,
 207         [WM8996_DSP2_RX_EQ_BAND_3_B] = 0xf373,
 208         [WM8996_DSP2_RX_EQ_BAND_3_C] = 0xa54,
 209         [WM8996_DSP2_RX_EQ_BAND_3_PG] = 0x558,
 210         [WM8996_DSP2_RX_EQ_BAND_4_A] = 0x168e,
 211         [WM8996_DSP2_RX_EQ_BAND_4_B] = 0xf829,
 212         [WM8996_DSP2_RX_EQ_BAND_4_C] = 0x7ad,
 213         [WM8996_DSP2_RX_EQ_BAND_4_PG] = 0x1103,
 214         [WM8996_DSP2_RX_EQ_BAND_5_A] = 0x564,
 215         [WM8996_DSP2_RX_EQ_BAND_5_B] = 0x559,
 216         [WM8996_DSP2_RX_EQ_BAND_5_PG] = 0x4000,
 217         [WM8996_OVERSAMPLING] = 0xd,
 218         [WM8996_SIDETONE] = 0x1040,
 219         [WM8996_GPIO_1] = 0xa101,
 220         [WM8996_GPIO_2] = 0xa101,
 221         [WM8996_GPIO_3] = 0xa101,
 222         [WM8996_GPIO_4] = 0xa101,
 223         [WM8996_GPIO_5] = 0xa101,
 224         [WM8996_PULL_CONTROL_2] = 0x140,
 225         [WM8996_INTERRUPT_STATUS_1_MASK] = 0x1f,
 226         [WM8996_INTERRUPT_STATUS_2_MASK] = 0x1ecf,
 227         [WM8996_RIGHT_PDM_SPEAKER] = 0x1,
 228         [WM8996_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69,
 229         [WM8996_PDM_SPEAKER_VOLUME] = 0x66,
 230         [WM8996_WRITE_SEQUENCER_0] = 0x1,
 231         [WM8996_WRITE_SEQUENCER_1] = 0x1,
 232         [WM8996_WRITE_SEQUENCER_3] = 0x6,
 233         [WM8996_WRITE_SEQUENCER_4] = 0x40,
 234         [WM8996_WRITE_SEQUENCER_5] = 0x1,
 235         [WM8996_WRITE_SEQUENCER_6] = 0xf,
 236         [WM8996_WRITE_SEQUENCER_7] = 0x6,
 237         [WM8996_WRITE_SEQUENCER_8] = 0x1,
 238         [WM8996_WRITE_SEQUENCER_9] = 0x3,
 239         [WM8996_WRITE_SEQUENCER_10] = 0x104,
 240         [WM8996_WRITE_SEQUENCER_12] = 0x60,
 241         [WM8996_WRITE_SEQUENCER_13] = 0x11,
 242         [WM8996_WRITE_SEQUENCER_14] = 0x401,
 243         [WM8996_WRITE_SEQUENCER_16] = 0x50,
 244         [WM8996_WRITE_SEQUENCER_17] = 0x3,
 245         [WM8996_WRITE_SEQUENCER_18] = 0x100,
 246         [WM8996_WRITE_SEQUENCER_20] = 0x51,
 247         [WM8996_WRITE_SEQUENCER_21] = 0x3,
 248         [WM8996_WRITE_SEQUENCER_22] = 0x104,
 249         [WM8996_WRITE_SEQUENCER_23] = 0xa,
 250         [WM8996_WRITE_SEQUENCER_24] = 0x60,
 251         [WM8996_WRITE_SEQUENCER_25] = 0x3b,
 252         [WM8996_WRITE_SEQUENCER_26] = 0x502,
 253         [WM8996_WRITE_SEQUENCER_27] = 0x100,
 254         [WM8996_WRITE_SEQUENCER_28] = 0x2fff,
 255         [WM8996_WRITE_SEQUENCER_32] = 0x2fff,
 256         [WM8996_WRITE_SEQUENCER_36] = 0x2fff,
 257         [WM8996_WRITE_SEQUENCER_40] = 0x2fff,
 258         [WM8996_WRITE_SEQUENCER_44] = 0x2fff,
 259         [WM8996_WRITE_SEQUENCER_48] = 0x2fff,
 260         [WM8996_WRITE_SEQUENCER_52] = 0x2fff,
 261         [WM8996_WRITE_SEQUENCER_56] = 0x2fff,
 262         [WM8996_WRITE_SEQUENCER_60] = 0x2fff,
 263         [WM8996_WRITE_SEQUENCER_64] = 0x1,
 264         [WM8996_WRITE_SEQUENCER_65] = 0x1,
 265         [WM8996_WRITE_SEQUENCER_67] = 0x6,
 266         [WM8996_WRITE_SEQUENCER_68] = 0x40,
 267         [WM8996_WRITE_SEQUENCER_69] = 0x1,
 268         [WM8996_WRITE_SEQUENCER_70] = 0xf,
 269         [WM8996_WRITE_SEQUENCER_71] = 0x6,
 270         [WM8996_WRITE_SEQUENCER_72] = 0x1,
 271         [WM8996_WRITE_SEQUENCER_73] = 0x3,
 272         [WM8996_WRITE_SEQUENCER_74] = 0x104,
 273         [WM8996_WRITE_SEQUENCER_76] = 0x60,
 274         [WM8996_WRITE_SEQUENCER_77] = 0x11,
 275         [WM8996_WRITE_SEQUENCER_78] = 0x401,
 276         [WM8996_WRITE_SEQUENCER_80] = 0x50,
 277         [WM8996_WRITE_SEQUENCER_81] = 0x3,
 278         [WM8996_WRITE_SEQUENCER_82] = 0x100,
 279         [WM8996_WRITE_SEQUENCER_84] = 0x60,
 280         [WM8996_WRITE_SEQUENCER_85] = 0x3b,
 281         [WM8996_WRITE_SEQUENCER_86] = 0x502,
 282         [WM8996_WRITE_SEQUENCER_87] = 0x100,
 283         [WM8996_WRITE_SEQUENCER_88] = 0x2fff,
 284         [WM8996_WRITE_SEQUENCER_92] = 0x2fff,
 285         [WM8996_WRITE_SEQUENCER_96] = 0x2fff,
 286         [WM8996_WRITE_SEQUENCER_100] = 0x2fff,
 287         [WM8996_WRITE_SEQUENCER_104] = 0x2fff,
 288         [WM8996_WRITE_SEQUENCER_108] = 0x2fff,
 289         [WM8996_WRITE_SEQUENCER_112] = 0x2fff,
 290         [WM8996_WRITE_SEQUENCER_116] = 0x2fff,
 291         [WM8996_WRITE_SEQUENCER_120] = 0x2fff,
 292         [WM8996_WRITE_SEQUENCER_124] = 0x2fff,
 293         [WM8996_WRITE_SEQUENCER_128] = 0x1,
 294         [WM8996_WRITE_SEQUENCER_129] = 0x1,
 295         [WM8996_WRITE_SEQUENCER_131] = 0x6,
 296         [WM8996_WRITE_SEQUENCER_132] = 0x40,
 297         [WM8996_WRITE_SEQUENCER_133] = 0x1,
 298         [WM8996_WRITE_SEQUENCER_134] = 0xf,
 299         [WM8996_WRITE_SEQUENCER_135] = 0x6,
 300         [WM8996_WRITE_SEQUENCER_136] = 0x1,
 301         [WM8996_WRITE_SEQUENCER_137] = 0x3,
 302         [WM8996_WRITE_SEQUENCER_138] = 0x106,
 303         [WM8996_WRITE_SEQUENCER_140] = 0x61,
 304         [WM8996_WRITE_SEQUENCER_141] = 0x11,
 305         [WM8996_WRITE_SEQUENCER_142] = 0x401,
 306         [WM8996_WRITE_SEQUENCER_144] = 0x50,
 307         [WM8996_WRITE_SEQUENCER_145] = 0x3,
 308         [WM8996_WRITE_SEQUENCER_146] = 0x102,
 309         [WM8996_WRITE_SEQUENCER_148] = 0x51,
 310         [WM8996_WRITE_SEQUENCER_149] = 0x3,
 311         [WM8996_WRITE_SEQUENCER_150] = 0x106,
 312         [WM8996_WRITE_SEQUENCER_151] = 0xa,
 313         [WM8996_WRITE_SEQUENCER_152] = 0x61,
 314         [WM8996_WRITE_SEQUENCER_153] = 0x3b,
 315         [WM8996_WRITE_SEQUENCER_154] = 0x502,
 316         [WM8996_WRITE_SEQUENCER_155] = 0x100,
 317         [WM8996_WRITE_SEQUENCER_156] = 0x2fff,
 318         [WM8996_WRITE_SEQUENCER_160] = 0x2fff,
 319         [WM8996_WRITE_SEQUENCER_164] = 0x2fff,
 320         [WM8996_WRITE_SEQUENCER_168] = 0x2fff,
 321         [WM8996_WRITE_SEQUENCER_172] = 0x2fff,
 322         [WM8996_WRITE_SEQUENCER_176] = 0x2fff,
 323         [WM8996_WRITE_SEQUENCER_180] = 0x2fff,
 324         [WM8996_WRITE_SEQUENCER_184] = 0x2fff,
 325         [WM8996_WRITE_SEQUENCER_188] = 0x2fff,
 326         [WM8996_WRITE_SEQUENCER_192] = 0x1,
 327         [WM8996_WRITE_SEQUENCER_193] = 0x1,
 328         [WM8996_WRITE_SEQUENCER_195] = 0x6,
 329         [WM8996_WRITE_SEQUENCER_196] = 0x40,
 330         [WM8996_WRITE_SEQUENCER_197] = 0x1,
 331         [WM8996_WRITE_SEQUENCER_198] = 0xf,
 332         [WM8996_WRITE_SEQUENCER_199] = 0x6,
 333         [WM8996_WRITE_SEQUENCER_200] = 0x1,
 334         [WM8996_WRITE_SEQUENCER_201] = 0x3,
 335         [WM8996_WRITE_SEQUENCER_202] = 0x106,
 336         [WM8996_WRITE_SEQUENCER_204] = 0x61,
 337         [WM8996_WRITE_SEQUENCER_205] = 0x11,
 338         [WM8996_WRITE_SEQUENCER_206] = 0x401,
 339         [WM8996_WRITE_SEQUENCER_208] = 0x50,
 340         [WM8996_WRITE_SEQUENCER_209] = 0x3,
 341         [WM8996_WRITE_SEQUENCER_210] = 0x102,
 342         [WM8996_WRITE_SEQUENCER_212] = 0x61,
 343         [WM8996_WRITE_SEQUENCER_213] = 0x3b,
 344         [WM8996_WRITE_SEQUENCER_214] = 0x502,
 345         [WM8996_WRITE_SEQUENCER_215] = 0x100,
 346         [WM8996_WRITE_SEQUENCER_216] = 0x2fff,
 347         [WM8996_WRITE_SEQUENCER_220] = 0x2fff,
 348         [WM8996_WRITE_SEQUENCER_224] = 0x2fff,
 349         [WM8996_WRITE_SEQUENCER_228] = 0x2fff,
 350         [WM8996_WRITE_SEQUENCER_232] = 0x2fff,
 351         [WM8996_WRITE_SEQUENCER_236] = 0x2fff,
 352         [WM8996_WRITE_SEQUENCER_240] = 0x2fff,
 353         [WM8996_WRITE_SEQUENCER_244] = 0x2fff,
 354         [WM8996_WRITE_SEQUENCER_248] = 0x2fff,
 355         [WM8996_WRITE_SEQUENCER_252] = 0x2fff,
 356         [WM8996_WRITE_SEQUENCER_256] = 0x60,
 357         [WM8996_WRITE_SEQUENCER_258] = 0x601,
 358         [WM8996_WRITE_SEQUENCER_260] = 0x50,
 359         [WM8996_WRITE_SEQUENCER_262] = 0x100,
 360         [WM8996_WRITE_SEQUENCER_264] = 0x1,
 361         [WM8996_WRITE_SEQUENCER_266] = 0x104,
 362         [WM8996_WRITE_SEQUENCER_267] = 0x100,
 363         [WM8996_WRITE_SEQUENCER_268] = 0x2fff,
 364         [WM8996_WRITE_SEQUENCER_272] = 0x2fff,
 365         [WM8996_WRITE_SEQUENCER_276] = 0x2fff,
 366         [WM8996_WRITE_SEQUENCER_280] = 0x2fff,
 367         [WM8996_WRITE_SEQUENCER_284] = 0x2fff,
 368         [WM8996_WRITE_SEQUENCER_288] = 0x2fff,
 369         [WM8996_WRITE_SEQUENCER_292] = 0x2fff,
 370         [WM8996_WRITE_SEQUENCER_296] = 0x2fff,
 371         [WM8996_WRITE_SEQUENCER_300] = 0x2fff,
 372         [WM8996_WRITE_SEQUENCER_304] = 0x2fff,
 373         [WM8996_WRITE_SEQUENCER_308] = 0x2fff,
 374         [WM8996_WRITE_SEQUENCER_312] = 0x2fff,
 375         [WM8996_WRITE_SEQUENCER_316] = 0x2fff,
 376         [WM8996_WRITE_SEQUENCER_320] = 0x61,
 377         [WM8996_WRITE_SEQUENCER_322] = 0x601,
 378         [WM8996_WRITE_SEQUENCER_324] = 0x50,
 379         [WM8996_WRITE_SEQUENCER_326] = 0x102,
 380         [WM8996_WRITE_SEQUENCER_328] = 0x1,
 381         [WM8996_WRITE_SEQUENCER_330] = 0x106,
 382         [WM8996_WRITE_SEQUENCER_331] = 0x100,
 383         [WM8996_WRITE_SEQUENCER_332] = 0x2fff,
 384         [WM8996_WRITE_SEQUENCER_336] = 0x2fff,
 385         [WM8996_WRITE_SEQUENCER_340] = 0x2fff,
 386         [WM8996_WRITE_SEQUENCER_344] = 0x2fff,
 387         [WM8996_WRITE_SEQUENCER_348] = 0x2fff,
 388         [WM8996_WRITE_SEQUENCER_352] = 0x2fff,
 389         [WM8996_WRITE_SEQUENCER_356] = 0x2fff,
 390         [WM8996_WRITE_SEQUENCER_360] = 0x2fff,
 391         [WM8996_WRITE_SEQUENCER_364] = 0x2fff,
 392         [WM8996_WRITE_SEQUENCER_368] = 0x2fff,
 393         [WM8996_WRITE_SEQUENCER_372] = 0x2fff,
 394         [WM8996_WRITE_SEQUENCER_376] = 0x2fff,
 395         [WM8996_WRITE_SEQUENCER_380] = 0x2fff,
 396         [WM8996_WRITE_SEQUENCER_384] = 0x60,
 397         [WM8996_WRITE_SEQUENCER_386] = 0x601,
 398         [WM8996_WRITE_SEQUENCER_388] = 0x61,
 399         [WM8996_WRITE_SEQUENCER_390] = 0x601,
 400         [WM8996_WRITE_SEQUENCER_392] = 0x50,
 401         [WM8996_WRITE_SEQUENCER_394] = 0x300,
 402         [WM8996_WRITE_SEQUENCER_396] = 0x1,
 403         [WM8996_WRITE_SEQUENCER_398] = 0x304,
 404         [WM8996_WRITE_SEQUENCER_400] = 0x40,
 405         [WM8996_WRITE_SEQUENCER_402] = 0xf,
 406         [WM8996_WRITE_SEQUENCER_404] = 0x1,
 407         [WM8996_WRITE_SEQUENCER_407] = 0x100,
 408 };
 409
 410 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
 411 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
 412 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 413 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
 414 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
 415 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
 416 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 417 static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
 418
 419 static const char *sidetone_hpf_text[] = {
 420         "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
 421 };
 422
 423 static const struct soc_enum sidetone_hpf =
 424         SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 7, sidetone_hpf_text);
 425
 426 static const char *hpf_mode_text[] = {
 427         "HiFi", "Custom", "Voice"
 428 };
 429
 430 static const struct soc_enum dsp1tx_hpf_mode =
 431         SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
 432
 433 static const struct soc_enum dsp2tx_hpf_mode =
 434         SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
 435
 436 static const char *hpf_cutoff_text[] = {
 437         "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
 438 };
 439
 440 static const struct soc_enum dsp1tx_hpf_cutoff =
 441         SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
 442
 443 static const struct soc_enum dsp2tx_hpf_cutoff =
 444         SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
 445
 446 static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block)
 447 {
 448         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 449         struct wm8996_pdata *pdata = &wm8996->pdata;
 450         int base, best, best_val, save, i, cfg, iface;
 451
 452         if (!wm8996->num_retune_mobile_texts)
 453                 return;
 454
 455         switch (block) {
 456         case 0:
 457                 base = WM8996_DSP1_RX_EQ_GAINS_1;
 458                 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
 459                     WM8996_DSP1RX_SRC)
 460                         iface = 1;
 461                 else
 462                         iface = 0;
 463                 break;
 464         case 1:
 465                 base = WM8996_DSP1_RX_EQ_GAINS_2;
 466                 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
 467                     WM8996_DSP2RX_SRC)
 468                         iface = 1;
 469                 else
 470                         iface = 0;
 471                 break;
 472         default:
 473                 return;
 474         }
 475
 476         /* Find the version of the currently selected configuration
 477          * with the nearest sample rate. */
 478         cfg = wm8996->retune_mobile_cfg[block];
 479         best = 0;
 480         best_val = INT_MAX;
 481         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 482                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 483                            wm8996->retune_mobile_texts[cfg]) == 0 &&
 484                     abs(pdata->retune_mobile_cfgs[i].rate
 485                         - wm8996->rx_rate[iface]) < best_val) {
 486                         best = i;
 487                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 488                                        - wm8996->rx_rate[iface]);
 489                 }
 490         }
 491
 492         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 493                 block,
 494                 pdata->retune_mobile_cfgs[best].name,
 495                 pdata->retune_mobile_cfgs[best].rate,
 496                 wm8996->rx_rate[iface]);
 497
 498         /* The EQ will be disabled while reconfiguring it, remember the
 499          * current configuration.
 500          */
 501         save = snd_soc_read(codec, base);
 502         save &= WM8996_DSP1RX_EQ_ENA;
 503
 504         for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
 505                 snd_soc_update_bits(codec, base + i, 0xffff,
 506                                     pdata->retune_mobile_cfgs[best].regs[i]);
 507
 508         snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save);
 509 }
 510
 511 /* Icky as hell but saves code duplication */
 512 static int wm8996_get_retune_mobile_block(const char *name)
 513 {
 514         if (strcmp(name, "DSP1 EQ Mode") == 0)
 515                 return 0;
 516         if (strcmp(name, "DSP2 EQ Mode") == 0)
 517                 return 1;
 518         return -EINVAL;
 519 }
 520
 521 static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 522                                          struct snd_ctl_elem_value *ucontrol)
 523 {
 524         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 525         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 526         struct wm8996_pdata *pdata = &wm8996->pdata;
 527         int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
 528         int value = ucontrol->value.integer.value[0];
 529
 530         if (block < 0)
 531                 return block;
 532
 533         if (value >= pdata->num_retune_mobile_cfgs)
 534                 return -EINVAL;
 535
 536         wm8996->retune_mobile_cfg[block] = value;
 537
 538         wm8996_set_retune_mobile(codec, block);
 539
 540         return 0;
 541 }
 542
 543 static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 544                                          struct snd_ctl_elem_value *ucontrol)
 545 {
 546         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 547         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 548         int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
 549
 550         ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
 551
 552         return 0;
 553 }
 554
 555 static const struct snd_kcontrol_new wm8996_snd_controls[] = {
 556 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
 557                  WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
 558 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
 559              WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
 560
 561 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
 562                0, 5, 24, 0, sidetone_tlv),
 563 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
 564                0, 5, 24, 0, sidetone_tlv),
 565 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
 566 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
 567 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
 568
 569 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
 570                  WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 571 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
 572                  WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 573
 574 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
 575            13, 1, 0),
 576 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
 577 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
 578 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
 579
 580 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
 581            13, 1, 0),
 582 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
 583 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
 584 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
 585
 586 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
 587                  WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 588 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
 589
 590 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
 591                  WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 592 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
 593
 594 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
 595                  WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 596 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
 597              WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
 598
 599 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
 600                  WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 601 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
 602              WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
 603
 604 SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
 605 SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
 606 SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
 607 SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
 608
 609 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
 610 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
 611
 612 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
 613 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
 614
 615 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
 616                 0, threedstereo_tlv),
 617 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
 618                 0, threedstereo_tlv),
 619
 620 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
 621                8, 0, out_digital_tlv),
 622 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
 623                8, 0, out_digital_tlv),
 624
 625 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
 626                  WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
 627 SOC_DOUBLE_R("Output 1 ZC Switch",  WM8996_OUTPUT1_LEFT_VOLUME,
 628              WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
 629
 630 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
 631                  WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
 632 SOC_DOUBLE_R("Output 2 ZC Switch",  WM8996_OUTPUT2_LEFT_VOLUME,
 633              WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
 634
 635 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
 636                spk_tlv),
 637 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
 638              WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
 639 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
 640              WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
 641
 642 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
 643 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
 644 };
 645
 646 static const struct snd_kcontrol_new wm8996_eq_controls[] = {
 647 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
 648                eq_tlv),
 649 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
 650                eq_tlv),
 651 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
 652                eq_tlv),
 653 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
 654                eq_tlv),
 655 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
 656                eq_tlv),
 657
 658 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
 659                eq_tlv),
 660 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
 661                eq_tlv),
 662 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
 663                eq_tlv),
 664 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
 665                eq_tlv),
 666 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
 667                eq_tlv),
 668 };
 669
 670 static int cp_event(struct snd_soc_dapm_widget *w,
 671                     struct snd_kcontrol *kcontrol, int event)
 672 {
 673         switch (event) {
 674         case SND_SOC_DAPM_POST_PMU:
 675                 msleep(5);
 676                 break;
 677         default:
 678                 BUG();
 679                 return -EINVAL;
 680         }
 681
 682         return 0;
 683 }
 684
 685 static int rmv_short_event(struct snd_soc_dapm_widget *w,
 686                            struct snd_kcontrol *kcontrol, int event)
 687 {
 688         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
 689
 690         /* Record which outputs we enabled */
 691         switch (event) {
 692         case SND_SOC_DAPM_PRE_PMD:
 693                 wm8996->hpout_pending &= ~w->shift;
 694                 break;
 695         case SND_SOC_DAPM_PRE_PMU:
 696                 wm8996->hpout_pending |= w->shift;
 697                 break;
 698         default:
 699                 BUG();
 700                 return -EINVAL;
 701         }
 702
 703         return 0;
 704 }
 705
 706 static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
 707 {
 708         struct i2c_client *i2c = to_i2c_client(codec->dev);
 709         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 710         int i, ret;
 711         unsigned long timeout = 200;
 712
 713         snd_soc_write(codec, WM8996_DC_SERVO_2, mask);
 714
 715         /* Use the interrupt if possible */
 716         do {
 717                 if (i2c->irq) {
 718                         timeout = wait_for_completion_timeout(&wm8996->dcs_done,
 719                                                               msecs_to_jiffies(200));
 720                         if (timeout == 0)
 721                                 dev_err(codec->dev, "DC servo timed out\n");
 722
 723                 } else {
 724                         msleep(1);
 725                         if (--i) {
 726                                 timeout = 0;
 727                                 break;
 728                         }
 729                 }
 730
 731                 ret = snd_soc_read(codec, WM8996_DC_SERVO_2);
 732                 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
 733         } while (ret & mask);
 734
 735         if (timeout == 0)
 736                 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
 737         else
 738                 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
 739 }
 740
 741 static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm,
 742                                 enum snd_soc_dapm_type event, int subseq)
 743 {
 744         struct snd_soc_codec *codec = container_of(dapm,
 745                                                    struct snd_soc_codec, dapm);
 746         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 747         u16 val, mask;
 748
 749         /* Complete any pending DC servo starts */
 750         if (wm8996->dcs_pending) {
 751                 dev_dbg(codec->dev, "Starting DC servo for %x\n",
 752                         wm8996->dcs_pending);
 753
 754                 /* Trigger a startup sequence */
 755                 wait_for_dc_servo(codec, wm8996->dcs_pending
 756                                          << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
 757
 758                 wm8996->dcs_pending = 0;
 759         }
 760
 761         if (wm8996->hpout_pending != wm8996->hpout_ena) {
 762                 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
 763                         wm8996->hpout_ena, wm8996->hpout_pending);
 764
 765                 val = 0;
 766                 mask = 0;
 767                 if (wm8996->hpout_pending & HPOUT1L) {
 768                         val |= WM8996_HPOUT1L_RMV_SHORT;
 769                         mask |= WM8996_HPOUT1L_RMV_SHORT;
 770                 } else {
 771                         mask |= WM8996_HPOUT1L_RMV_SHORT |
 772                                 WM8996_HPOUT1L_OUTP |
 773                                 WM8996_HPOUT1L_DLY;
 774                 }
 775
 776                 if (wm8996->hpout_pending & HPOUT1R) {
 777                         val |= WM8996_HPOUT1R_RMV_SHORT;
 778                         mask |= WM8996_HPOUT1R_RMV_SHORT;
 779                 } else {
 780                         mask |= WM8996_HPOUT1R_RMV_SHORT |
 781                                 WM8996_HPOUT1R_OUTP |
 782                                 WM8996_HPOUT1R_DLY;
 783                 }
 784
 785                 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val);
 786
 787                 val = 0;
 788                 mask = 0;
 789                 if (wm8996->hpout_pending & HPOUT2L) {
 790                         val |= WM8996_HPOUT2L_RMV_SHORT;
 791                         mask |= WM8996_HPOUT2L_RMV_SHORT;
 792                 } else {
 793                         mask |= WM8996_HPOUT2L_RMV_SHORT |
 794                                 WM8996_HPOUT2L_OUTP |
 795                                 WM8996_HPOUT2L_DLY;
 796                 }
 797
 798                 if (wm8996->hpout_pending & HPOUT2R) {
 799                         val |= WM8996_HPOUT2R_RMV_SHORT;
 800                         mask |= WM8996_HPOUT2R_RMV_SHORT;
 801                 } else {
 802                         mask |= WM8996_HPOUT2R_RMV_SHORT |
 803                                 WM8996_HPOUT2R_OUTP |
 804                                 WM8996_HPOUT2R_DLY;
 805                 }
 806
 807                 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val);
 808
 809                 wm8996->hpout_ena = wm8996->hpout_pending;
 810         }
 811 }
 812
 813 static int dcs_start(struct snd_soc_dapm_widget *w,
 814                      struct snd_kcontrol *kcontrol, int event)
 815 {
 816         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
 817
 818         switch (event) {
 819         case SND_SOC_DAPM_POST_PMU:
 820                 wm8996->dcs_pending |= 1 << w->shift;
 821                 break;
 822         default:
 823                 BUG();
 824                 return -EINVAL;
 825         }
 826
 827         return 0;
 828 }
 829
 830 static const char *sidetone_text[] = {
 831         "IN1", "IN2",
 832 };
 833
 834 static const struct soc_enum left_sidetone_enum =
 835         SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text);
 836
 837 static const struct snd_kcontrol_new left_sidetone =
 838         SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
 839
 840 static const struct soc_enum right_sidetone_enum =
 841         SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text);
 842
 843 static const struct snd_kcontrol_new right_sidetone =
 844         SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
 845
 846 static const char *spk_text[] = {
 847         "DAC1L", "DAC1R", "DAC2L", "DAC2R"
 848 };
 849
 850 static const struct soc_enum spkl_enum =
 851         SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text);
 852
 853 static const struct snd_kcontrol_new spkl_mux =
 854         SOC_DAPM_ENUM("SPKL", spkl_enum);
 855
 856 static const struct soc_enum spkr_enum =
 857         SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
 858
 859 static const struct snd_kcontrol_new spkr_mux =
 860         SOC_DAPM_ENUM("SPKR", spkr_enum);
 861
 862 static const char *dsp1rx_text[] = {
 863         "AIF1", "AIF2"
 864 };
 865
 866 static const struct soc_enum dsp1rx_enum =
 867         SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
 868
 869 static const struct snd_kcontrol_new dsp1rx =
 870         SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
 871
 872 static const char *dsp2rx_text[] = {
 873          "AIF2", "AIF1"
 874 };
 875
 876 static const struct soc_enum dsp2rx_enum =
 877         SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
 878
 879 static const struct snd_kcontrol_new dsp2rx =
 880         SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
 881
 882 static const char *aif2tx_text[] = {
 883         "DSP2", "DSP1", "AIF1"
 884 };
 885
 886 static const struct soc_enum aif2tx_enum =
 887         SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
 888
 889 static const struct snd_kcontrol_new aif2tx =
 890         SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
 891
 892 static const char *inmux_text[] = {
 893         "ADC", "DMIC1", "DMIC2"
 894 };
 895
 896 static const struct soc_enum in1_enum =
 897         SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text);
 898
 899 static const struct snd_kcontrol_new in1_mux =
 900         SOC_DAPM_ENUM("IN1 Mux", in1_enum);
 901
 902 static const struct soc_enum in2_enum =
 903         SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text);
 904
 905 static const struct snd_kcontrol_new in2_mux =
 906         SOC_DAPM_ENUM("IN2 Mux", in2_enum);
 907
 908 static const struct snd_kcontrol_new dac2r_mix[] = {
 909 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
 910                 5, 1, 0),
 911 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
 912                 4, 1, 0),
 913 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
 914 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
 915 };
 916
 917 static const struct snd_kcontrol_new dac2l_mix[] = {
 918 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
 919                 5, 1, 0),
 920 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
 921                 4, 1, 0),
 922 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
 923 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
 924 };
 925
 926 static const struct snd_kcontrol_new dac1r_mix[] = {
 927 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
 928                 5, 1, 0),
 929 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
 930                 4, 1, 0),
 931 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
 932 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
 933 };
 934
 935 static const struct snd_kcontrol_new dac1l_mix[] = {
 936 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
 937                 5, 1, 0),
 938 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
 939                 4, 1, 0),
 940 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
 941 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
 942 };
 943
 944 static const struct snd_kcontrol_new dsp1txl[] = {
 945 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
 946                 1, 1, 0),
 947 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
 948                 0, 1, 0),
 949 };
 950
 951 static const struct snd_kcontrol_new dsp1txr[] = {
 952 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
 953                 1, 1, 0),
 954 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
 955                 0, 1, 0),
 956 };
 957
 958 static const struct snd_kcontrol_new dsp2txl[] = {
 959 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
 960                 1, 1, 0),
 961 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
 962                 0, 1, 0),
 963 };
 964
 965 static const struct snd_kcontrol_new dsp2txr[] = {
 966 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
 967                 1, 1, 0),
 968 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
 969                 0, 1, 0),
 970 };
 971
 972
 973 static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
 974 SND_SOC_DAPM_INPUT("IN1LN"),
 975 SND_SOC_DAPM_INPUT("IN1LP"),
 976 SND_SOC_DAPM_INPUT("IN1RN"),
 977 SND_SOC_DAPM_INPUT("IN1RP"),
 978
 979 SND_SOC_DAPM_INPUT("IN2LN"),
 980 SND_SOC_DAPM_INPUT("IN2LP"),
 981 SND_SOC_DAPM_INPUT("IN2RN"),
 982 SND_SOC_DAPM_INPUT("IN2RP"),
 983
 984 SND_SOC_DAPM_INPUT("DMIC1DAT"),
 985 SND_SOC_DAPM_INPUT("DMIC2DAT"),
 986
 987 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
 988 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
 989 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
 990 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
 991                       SND_SOC_DAPM_POST_PMU),
 992
 993 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
 994 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
 995 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
 996 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
 997 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
 998
 999 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
1000 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
1001
1002 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
1003 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
1004 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
1005 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
1006
1007 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1008 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1009
1010 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
1011 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
1012 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
1013 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
1014
1015 SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
1016 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
1017
1018 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1019 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1020
1021 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
1022 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
1023 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
1024 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
1025
1026 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
1027                    dsp2txl, ARRAY_SIZE(dsp2txl)),
1028 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
1029                    dsp2txr, ARRAY_SIZE(dsp2txr)),
1030 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
1031                    dsp1txl, ARRAY_SIZE(dsp1txl)),
1032 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
1033                    dsp1txr, ARRAY_SIZE(dsp1txr)),
1034
1035 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1036                    dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1037 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1038                    dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1039 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1040                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1041 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1042                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1043
1044 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
1045 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
1046 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
1047 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
1048
1049 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 1,
1050                     WM8996_POWER_MANAGEMENT_4, 9, 0),
1051 SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 2,
1052                     WM8996_POWER_MANAGEMENT_4, 8, 0),
1053
1054 SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 1,
1055                     WM8996_POWER_MANAGEMENT_6, 9, 0),
1056 SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 2,
1057                     WM8996_POWER_MANAGEMENT_6, 8, 0),
1058
1059 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1060                     WM8996_POWER_MANAGEMENT_4, 5, 0),
1061 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1062                     WM8996_POWER_MANAGEMENT_4, 4, 0),
1063 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1064                     WM8996_POWER_MANAGEMENT_4, 3, 0),
1065 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1066                     WM8996_POWER_MANAGEMENT_4, 2, 0),
1067 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1068                     WM8996_POWER_MANAGEMENT_4, 1, 0),
1069 SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1070                     WM8996_POWER_MANAGEMENT_4, 0, 0),
1071
1072 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1073                      WM8996_POWER_MANAGEMENT_6, 5, 0),
1074 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1075                      WM8996_POWER_MANAGEMENT_6, 4, 0),
1076 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1077                      WM8996_POWER_MANAGEMENT_6, 3, 0),
1078 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1079                      WM8996_POWER_MANAGEMENT_6, 2, 0),
1080 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1081                      WM8996_POWER_MANAGEMENT_6, 1, 0),
1082 SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1083                      WM8996_POWER_MANAGEMENT_6, 0, 0),
1084
1085 /* We route as stereo pairs so define some dummy widgets to squash
1086  * things down for now.  RXA = 0,1, RXB = 2,3 and so on */
1087 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1088 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1089 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1090 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1091 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1092
1093 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1094 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1095 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1096
1097 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1098 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1099 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1100 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1101
1102 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1103 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1104 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1105                    SND_SOC_DAPM_POST_PMU),
1106 SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8996_ANALOGUE_HP_2, 6, 0, NULL, 0),
1107 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1108                    rmv_short_event,
1109                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1110
1111 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1112 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1113 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1114                    SND_SOC_DAPM_POST_PMU),
1115 SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8996_ANALOGUE_HP_2, 2, 0, NULL, 0),
1116 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1117                    rmv_short_event,
1118                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1119
1120 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1121 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1122 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1123                    SND_SOC_DAPM_POST_PMU),
1124 SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8996_ANALOGUE_HP_1, 6, 0, NULL, 0),
1125 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1126                    rmv_short_event,
1127                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1128
1129 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1130 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1131 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1132                    SND_SOC_DAPM_POST_PMU),
1133 SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8996_ANALOGUE_HP_1, 2, 0, NULL, 0),
1134 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1135                    rmv_short_event,
1136                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1137
1138 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1139 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1140 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1141 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1142 SND_SOC_DAPM_OUTPUT("SPKDAT"),
1143 };
1144
1145 static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1146         { "AIFCLK", NULL, "SYSCLK" },
1147         { "SYSDSPCLK", NULL, "SYSCLK" },
1148         { "Charge Pump", NULL, "SYSCLK" },
1149
1150         { "MICB1", NULL, "LDO2" },
1151         { "MICB1", NULL, "MICB1 Audio" },
1152         { "MICB2", NULL, "LDO2" },
1153         { "MICB2", NULL, "MICB2 Audio" },
1154
1155         { "IN1L PGA", NULL, "IN2LN" },
1156         { "IN1L PGA", NULL, "IN2LP" },
1157         { "IN1L PGA", NULL, "IN1LN" },
1158         { "IN1L PGA", NULL, "IN1LP" },
1159
1160         { "IN1R PGA", NULL, "IN2RN" },
1161         { "IN1R PGA", NULL, "IN2RP" },
1162         { "IN1R PGA", NULL, "IN1RN" },
1163         { "IN1R PGA", NULL, "IN1RP" },
1164
1165         { "ADCL", NULL, "IN1L PGA" },
1166
1167         { "ADCR", NULL, "IN1R PGA" },
1168
1169         { "DMIC1L", NULL, "DMIC1DAT" },
1170         { "DMIC1R", NULL, "DMIC1DAT" },
1171         { "DMIC2L", NULL, "DMIC2DAT" },
1172         { "DMIC2R", NULL, "DMIC2DAT" },
1173
1174         { "DMIC2L", NULL, "DMIC2" },
1175         { "DMIC2R", NULL, "DMIC2" },
1176         { "DMIC1L", NULL, "DMIC1" },
1177         { "DMIC1R", NULL, "DMIC1" },
1178
1179         { "IN1L Mux", "ADC", "ADCL" },
1180         { "IN1L Mux", "DMIC1", "DMIC1L" },
1181         { "IN1L Mux", "DMIC2", "DMIC2L" },
1182
1183         { "IN1R Mux", "ADC", "ADCR" },
1184         { "IN1R Mux", "DMIC1", "DMIC1R" },
1185         { "IN1R Mux", "DMIC2", "DMIC2R" },
1186
1187         { "IN2L Mux", "ADC", "ADCL" },
1188         { "IN2L Mux", "DMIC1", "DMIC1L" },
1189         { "IN2L Mux", "DMIC2", "DMIC2L" },
1190
1191         { "IN2R Mux", "ADC", "ADCR" },
1192         { "IN2R Mux", "DMIC1", "DMIC1R" },
1193         { "IN2R Mux", "DMIC2", "DMIC2R" },
1194
1195         { "Left Sidetone", "IN1", "IN1L Mux" },
1196         { "Left Sidetone", "IN2", "IN2L Mux" },
1197
1198         { "Right Sidetone", "IN1", "IN1R Mux" },
1199         { "Right Sidetone", "IN2", "IN2R Mux" },
1200
1201         { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1202         { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1203
1204         { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1205         { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1206
1207         { "AIF1TX0", NULL, "DSP1TXL" },
1208         { "AIF1TX1", NULL, "DSP1TXR" },
1209         { "AIF1TX2", NULL, "DSP2TXL" },
1210         { "AIF1TX3", NULL, "DSP2TXR" },
1211         { "AIF1TX4", NULL, "AIF2RX0" },
1212         { "AIF1TX5", NULL, "AIF2RX1" },
1213
1214         { "AIF1RX0", NULL, "AIFCLK" },
1215         { "AIF1RX1", NULL, "AIFCLK" },
1216         { "AIF1RX2", NULL, "AIFCLK" },
1217         { "AIF1RX3", NULL, "AIFCLK" },
1218         { "AIF1RX4", NULL, "AIFCLK" },
1219         { "AIF1RX5", NULL, "AIFCLK" },
1220
1221         { "AIF2RX0", NULL, "AIFCLK" },
1222         { "AIF2RX1", NULL, "AIFCLK" },
1223
1224         { "AIF1TX0", NULL, "AIFCLK" },
1225         { "AIF1TX1", NULL, "AIFCLK" },
1226         { "AIF1TX2", NULL, "AIFCLK" },
1227         { "AIF1TX3", NULL, "AIFCLK" },
1228         { "AIF1TX4", NULL, "AIFCLK" },
1229         { "AIF1TX5", NULL, "AIFCLK" },
1230
1231         { "AIF2TX0", NULL, "AIFCLK" },
1232         { "AIF2TX1", NULL, "AIFCLK" },
1233
1234         { "DSP1RXL", NULL, "SYSDSPCLK" },
1235         { "DSP1RXR", NULL, "SYSDSPCLK" },
1236         { "DSP2RXL", NULL, "SYSDSPCLK" },
1237         { "DSP2RXR", NULL, "SYSDSPCLK" },
1238         { "DSP1TXL", NULL, "SYSDSPCLK" },
1239         { "DSP1TXR", NULL, "SYSDSPCLK" },
1240         { "DSP2TXL", NULL, "SYSDSPCLK" },
1241         { "DSP2TXR", NULL, "SYSDSPCLK" },
1242
1243         { "AIF1RXA", NULL, "AIF1RX0" },
1244         { "AIF1RXA", NULL, "AIF1RX1" },
1245         { "AIF1RXB", NULL, "AIF1RX2" },
1246         { "AIF1RXB", NULL, "AIF1RX3" },
1247         { "AIF1RXC", NULL, "AIF1RX4" },
1248         { "AIF1RXC", NULL, "AIF1RX5" },
1249
1250         { "AIF2RX", NULL, "AIF2RX0" },
1251         { "AIF2RX", NULL, "AIF2RX1" },
1252
1253         { "AIF2TX", "DSP2", "DSP2TX" },
1254         { "AIF2TX", "DSP1", "DSP1RX" },
1255         { "AIF2TX", "AIF1", "AIF1RXC" },
1256
1257         { "DSP1RXL", NULL, "DSP1RX" },
1258         { "DSP1RXR", NULL, "DSP1RX" },
1259         { "DSP2RXL", NULL, "DSP2RX" },
1260         { "DSP2RXR", NULL, "DSP2RX" },
1261
1262         { "DSP2TX", NULL, "DSP2TXL" },
1263         { "DSP2TX", NULL, "DSP2TXR" },
1264
1265         { "DSP1RX", "AIF1", "AIF1RXA" },
1266         { "DSP1RX", "AIF2", "AIF2RX" },
1267
1268         { "DSP2RX", "AIF1", "AIF1RXB" },
1269         { "DSP2RX", "AIF2", "AIF2RX" },
1270
1271         { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1272         { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1273         { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1274         { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1275
1276         { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1277         { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1278         { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1279         { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1280
1281         { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1282         { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1283         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1284         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1285
1286         { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1287         { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1288         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1289         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1290
1291         { "DAC1L", NULL, "DAC1L Mixer" },
1292         { "DAC1R", NULL, "DAC1R Mixer" },
1293         { "DAC2L", NULL, "DAC2L Mixer" },
1294         { "DAC2R", NULL, "DAC2R Mixer" },
1295
1296         { "HPOUT2L PGA", NULL, "Charge Pump" },
1297         { "HPOUT2L PGA", NULL, "DAC2L" },
1298         { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1299         { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1300         { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1301         { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1302
1303         { "HPOUT2R PGA", NULL, "Charge Pump" },
1304         { "HPOUT2R PGA", NULL, "DAC2R" },
1305         { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1306         { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1307         { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1308         { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1309
1310         { "HPOUT1L PGA", NULL, "Charge Pump" },
1311         { "HPOUT1L PGA", NULL, "DAC1L" },
1312         { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1313         { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1314         { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1315         { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1316
1317         { "HPOUT1R PGA", NULL, "Charge Pump" },
1318         { "HPOUT1R PGA", NULL, "DAC1R" },
1319         { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1320         { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1321         { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1322         { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1323
1324         { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1325         { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1326         { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1327         { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1328
1329         { "SPKL", "DAC1L", "DAC1L" },
1330         { "SPKL", "DAC1R", "DAC1R" },
1331         { "SPKL", "DAC2L", "DAC2L" },
1332         { "SPKL", "DAC2R", "DAC2R" },
1333
1334         { "SPKR", "DAC1L", "DAC1L" },
1335         { "SPKR", "DAC1R", "DAC1R" },
1336         { "SPKR", "DAC2L", "DAC2L" },
1337         { "SPKR", "DAC2R", "DAC2R" },
1338
1339         { "SPKL PGA", NULL, "SPKL" },
1340         { "SPKR PGA", NULL, "SPKR" },
1341
1342         { "SPKDAT", NULL, "SPKL PGA" },
1343         { "SPKDAT", NULL, "SPKR PGA" },
1344 };
1345
1346 static int wm8996_readable_register(struct snd_soc_codec *codec,
1347                                     unsigned int reg)
1348 {
1349         /* Due to the sparseness of the register map the compiler
1350          * output from an explicit switch statement ends up being much
1351          * more efficient than a table.
1352          */
1353         switch (reg) {
1354         case WM8996_SOFTWARE_RESET:
1355         case WM8996_POWER_MANAGEMENT_1:
1356         case WM8996_POWER_MANAGEMENT_2:
1357         case WM8996_POWER_MANAGEMENT_3:
1358         case WM8996_POWER_MANAGEMENT_4:
1359         case WM8996_POWER_MANAGEMENT_5:
1360         case WM8996_POWER_MANAGEMENT_6:
1361         case WM8996_POWER_MANAGEMENT_7:
1362         case WM8996_POWER_MANAGEMENT_8:
1363         case WM8996_LEFT_LINE_INPUT_VOLUME:
1364         case WM8996_RIGHT_LINE_INPUT_VOLUME:
1365         case WM8996_LINE_INPUT_CONTROL:
1366         case WM8996_DAC1_HPOUT1_VOLUME:
1367         case WM8996_DAC2_HPOUT2_VOLUME:
1368         case WM8996_DAC1_LEFT_VOLUME:
1369         case WM8996_DAC1_RIGHT_VOLUME:
1370         case WM8996_DAC2_LEFT_VOLUME:
1371         case WM8996_DAC2_RIGHT_VOLUME:
1372         case WM8996_OUTPUT1_LEFT_VOLUME:
1373         case WM8996_OUTPUT1_RIGHT_VOLUME:
1374         case WM8996_OUTPUT2_LEFT_VOLUME:
1375         case WM8996_OUTPUT2_RIGHT_VOLUME:
1376         case WM8996_MICBIAS_1:
1377         case WM8996_MICBIAS_2:
1378         case WM8996_LDO_1:
1379         case WM8996_LDO_2:
1380         case WM8996_ACCESSORY_DETECT_MODE_1:
1381         case WM8996_ACCESSORY_DETECT_MODE_2:
1382         case WM8996_HEADPHONE_DETECT_1:
1383         case WM8996_HEADPHONE_DETECT_2:
1384         case WM8996_MIC_DETECT_1:
1385         case WM8996_MIC_DETECT_2:
1386         case WM8996_MIC_DETECT_3:
1387         case WM8996_CHARGE_PUMP_1:
1388         case WM8996_CHARGE_PUMP_2:
1389         case WM8996_DC_SERVO_1:
1390         case WM8996_DC_SERVO_2:
1391         case WM8996_DC_SERVO_3:
1392         case WM8996_DC_SERVO_5:
1393         case WM8996_DC_SERVO_6:
1394         case WM8996_DC_SERVO_7:
1395         case WM8996_DC_SERVO_READBACK_0:
1396         case WM8996_ANALOGUE_HP_1:
1397         case WM8996_ANALOGUE_HP_2:
1398         case WM8996_CHIP_REVISION:
1399         case WM8996_CONTROL_INTERFACE_1:
1400         case WM8996_WRITE_SEQUENCER_CTRL_1:
1401         case WM8996_WRITE_SEQUENCER_CTRL_2:
1402         case WM8996_AIF_CLOCKING_1:
1403         case WM8996_AIF_CLOCKING_2:
1404         case WM8996_CLOCKING_1:
1405         case WM8996_CLOCKING_2:
1406         case WM8996_AIF_RATE:
1407         case WM8996_FLL_CONTROL_1:
1408         case WM8996_FLL_CONTROL_2:
1409         case WM8996_FLL_CONTROL_3:
1410         case WM8996_FLL_CONTROL_4:
1411         case WM8996_FLL_CONTROL_5:
1412         case WM8996_FLL_CONTROL_6:
1413         case WM8996_FLL_EFS_1:
1414         case WM8996_FLL_EFS_2:
1415         case WM8996_AIF1_CONTROL:
1416         case WM8996_AIF1_BCLK:
1417         case WM8996_AIF1_TX_LRCLK_1:
1418         case WM8996_AIF1_TX_LRCLK_2:
1419         case WM8996_AIF1_RX_LRCLK_1:
1420         case WM8996_AIF1_RX_LRCLK_2:
1421         case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1422         case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1423         case WM8996_AIF1RX_DATA_CONFIGURATION:
1424         case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1425         case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1426         case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1427         case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1428         case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1429         case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1430         case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1431         case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1432         case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1433         case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1434         case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1435         case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1436         case WM8996_AIF1RX_MONO_CONFIGURATION:
1437         case WM8996_AIF1TX_TEST:
1438         case WM8996_AIF2_CONTROL:
1439         case WM8996_AIF2_BCLK:
1440         case WM8996_AIF2_TX_LRCLK_1:
1441         case WM8996_AIF2_TX_LRCLK_2:
1442         case WM8996_AIF2_RX_LRCLK_1:
1443         case WM8996_AIF2_RX_LRCLK_2:
1444         case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1445         case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1446         case WM8996_AIF2RX_DATA_CONFIGURATION:
1447         case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1448         case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1449         case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1450         case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1451         case WM8996_AIF2RX_MONO_CONFIGURATION:
1452         case WM8996_AIF2TX_TEST:
1453         case WM8996_DSP1_TX_LEFT_VOLUME:
1454         case WM8996_DSP1_TX_RIGHT_VOLUME:
1455         case WM8996_DSP1_RX_LEFT_VOLUME:
1456         case WM8996_DSP1_RX_RIGHT_VOLUME:
1457         case WM8996_DSP1_TX_FILTERS:
1458         case WM8996_DSP1_RX_FILTERS_1:
1459         case WM8996_DSP1_RX_FILTERS_2:
1460         case WM8996_DSP1_DRC_1:
1461         case WM8996_DSP1_DRC_2:
1462         case WM8996_DSP1_DRC_3:
1463         case WM8996_DSP1_DRC_4:
1464         case WM8996_DSP1_DRC_5:
1465         case WM8996_DSP1_RX_EQ_GAINS_1:
1466         case WM8996_DSP1_RX_EQ_GAINS_2:
1467         case WM8996_DSP1_RX_EQ_BAND_1_A:
1468         case WM8996_DSP1_RX_EQ_BAND_1_B:
1469         case WM8996_DSP1_RX_EQ_BAND_1_PG:
1470         case WM8996_DSP1_RX_EQ_BAND_2_A:
1471         case WM8996_DSP1_RX_EQ_BAND_2_B:
1472         case WM8996_DSP1_RX_EQ_BAND_2_C:
1473         case WM8996_DSP1_RX_EQ_BAND_2_PG:
1474         case WM8996_DSP1_RX_EQ_BAND_3_A:
1475         case WM8996_DSP1_RX_EQ_BAND_3_B:
1476         case WM8996_DSP1_RX_EQ_BAND_3_C:
1477         case WM8996_DSP1_RX_EQ_BAND_3_PG:
1478         case WM8996_DSP1_RX_EQ_BAND_4_A:
1479         case WM8996_DSP1_RX_EQ_BAND_4_B:
1480         case WM8996_DSP1_RX_EQ_BAND_4_C:
1481         case WM8996_DSP1_RX_EQ_BAND_4_PG:
1482         case WM8996_DSP1_RX_EQ_BAND_5_A:
1483         case WM8996_DSP1_RX_EQ_BAND_5_B:
1484         case WM8996_DSP1_RX_EQ_BAND_5_PG:
1485         case WM8996_DSP2_TX_LEFT_VOLUME:
1486         case WM8996_DSP2_TX_RIGHT_VOLUME:
1487         case WM8996_DSP2_RX_LEFT_VOLUME:
1488         case WM8996_DSP2_RX_RIGHT_VOLUME:
1489         case WM8996_DSP2_TX_FILTERS:
1490         case WM8996_DSP2_RX_FILTERS_1:
1491         case WM8996_DSP2_RX_FILTERS_2:
1492         case WM8996_DSP2_DRC_1:
1493         case WM8996_DSP2_DRC_2:
1494         case WM8996_DSP2_DRC_3:
1495         case WM8996_DSP2_DRC_4:
1496         case WM8996_DSP2_DRC_5:
1497         case WM8996_DSP2_RX_EQ_GAINS_1:
1498         case WM8996_DSP2_RX_EQ_GAINS_2:
1499         case WM8996_DSP2_RX_EQ_BAND_1_A:
1500         case WM8996_DSP2_RX_EQ_BAND_1_B:
1501         case WM8996_DSP2_RX_EQ_BAND_1_PG:
1502         case WM8996_DSP2_RX_EQ_BAND_2_A:
1503         case WM8996_DSP2_RX_EQ_BAND_2_B:
1504         case WM8996_DSP2_RX_EQ_BAND_2_C:
1505         case WM8996_DSP2_RX_EQ_BAND_2_PG:
1506         case WM8996_DSP2_RX_EQ_BAND_3_A:
1507         case WM8996_DSP2_RX_EQ_BAND_3_B:
1508         case WM8996_DSP2_RX_EQ_BAND_3_C:
1509         case WM8996_DSP2_RX_EQ_BAND_3_PG:
1510         case WM8996_DSP2_RX_EQ_BAND_4_A:
1511         case WM8996_DSP2_RX_EQ_BAND_4_B:
1512         case WM8996_DSP2_RX_EQ_BAND_4_C:
1513         case WM8996_DSP2_RX_EQ_BAND_4_PG:
1514         case WM8996_DSP2_RX_EQ_BAND_5_A:
1515         case WM8996_DSP2_RX_EQ_BAND_5_B:
1516         case WM8996_DSP2_RX_EQ_BAND_5_PG:
1517         case WM8996_DAC1_MIXER_VOLUMES:
1518         case WM8996_DAC1_LEFT_MIXER_ROUTING:
1519         case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1520         case WM8996_DAC2_MIXER_VOLUMES:
1521         case WM8996_DAC2_LEFT_MIXER_ROUTING:
1522         case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1523         case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1524         case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1525         case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1526         case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1527         case WM8996_DSP_TX_MIXER_SELECT:
1528         case WM8996_DAC_SOFTMUTE:
1529         case WM8996_OVERSAMPLING:
1530         case WM8996_SIDETONE:
1531         case WM8996_GPIO_1:
1532         case WM8996_GPIO_2:
1533         case WM8996_GPIO_3:
1534         case WM8996_GPIO_4:
1535         case WM8996_GPIO_5:
1536         case WM8996_PULL_CONTROL_1:
1537         case WM8996_PULL_CONTROL_2:
1538         case WM8996_INTERRUPT_STATUS_1:
1539         case WM8996_INTERRUPT_STATUS_2:
1540         case WM8996_INTERRUPT_RAW_STATUS_2:
1541         case WM8996_INTERRUPT_STATUS_1_MASK:
1542         case WM8996_INTERRUPT_STATUS_2_MASK:
1543         case WM8996_INTERRUPT_CONTROL:
1544         case WM8996_LEFT_PDM_SPEAKER:
1545         case WM8996_RIGHT_PDM_SPEAKER:
1546         case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1547         case WM8996_PDM_SPEAKER_VOLUME:
1548                 return 1;
1549         default:
1550                 return 0;
1551         }
1552 }
1553
1554 static int wm8996_volatile_register(struct snd_soc_codec *codec,
1555                                     unsigned int reg)
1556 {
1557         switch (reg) {
1558         case WM8996_SOFTWARE_RESET:
1559         case WM8996_CHIP_REVISION:
1560         case WM8996_LDO_1:
1561         case WM8996_LDO_2:
1562         case WM8996_INTERRUPT_STATUS_1:
1563         case WM8996_INTERRUPT_STATUS_2:
1564         case WM8996_INTERRUPT_RAW_STATUS_2:
1565         case WM8996_DC_SERVO_READBACK_0:
1566         case WM8996_DC_SERVO_2:
1567         case WM8996_DC_SERVO_6:
1568         case WM8996_DC_SERVO_7:
1569         case WM8996_FLL_CONTROL_6:
1570         case WM8996_MIC_DETECT_3:
1571         case WM8996_HEADPHONE_DETECT_1:
1572         case WM8996_HEADPHONE_DETECT_2:
1573                 return 1;
1574         default:
1575                 return 0;
1576         }
1577 }
1578
1579 static int wm8996_reset(struct snd_soc_codec *codec)
1580 {
1581         return snd_soc_write(codec, WM8996_SOFTWARE_RESET, 0x8915);
1582 }
1583
1584 static const int bclk_divs[] = {
1585         1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1586 };
1587
1588 static void wm8996_update_bclk(struct snd_soc_codec *codec)
1589 {
1590         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1591         int aif, best, cur_val, bclk_rate, bclk_reg, i;
1592
1593         /* Don't bother if we're in a low frequency idle mode that
1594          * can't support audio.
1595          */
1596         if (wm8996->sysclk < 64000)
1597                 return;
1598
1599         for (aif = 0; aif < WM8996_AIFS; aif++) {
1600                 switch (aif) {
1601                 case 0:
1602                         bclk_reg = WM8996_AIF1_BCLK;
1603                         break;
1604                 case 1:
1605                         bclk_reg = WM8996_AIF2_BCLK;
1606                         break;
1607                 }
1608
1609                 bclk_rate = wm8996->bclk_rate[aif];
1610
1611                 /* Pick a divisor for BCLK as close as we can get to ideal */
1612                 best = 0;
1613                 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1614                         cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1615                         if (cur_val < 0) /* BCLK table is sorted */
1616                                 break;
1617                         best = i;
1618                 }
1619                 bclk_rate = wm8996->sysclk / bclk_divs[best];
1620                 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1621                         bclk_divs[best], bclk_rate);
1622
1623                 snd_soc_update_bits(codec, bclk_reg,
1624                                     WM8996_AIF1_BCLK_DIV_MASK, best);
1625         }
1626 }
1627
1628 static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1629                                  enum snd_soc_bias_level level)
1630 {
1631         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1632         int ret;
1633
1634         switch (level) {
1635         case SND_SOC_BIAS_ON:
1636                 break;
1637
1638         case SND_SOC_BIAS_PREPARE:
1639                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1640                         snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
1641                                             WM8996_BG_ENA, WM8996_BG_ENA);
1642                         msleep(2);
1643                 }
1644                 break;
1645
1646         case SND_SOC_BIAS_STANDBY:
1647                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1648                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1649                                                     wm8996->supplies);
1650                         if (ret != 0) {
1651                                 dev_err(codec->dev,
1652                                         "Failed to enable supplies: %d\n",
1653                                         ret);
1654                                 return ret;
1655                         }
1656
1657                         if (wm8996->pdata.ldo_ena >= 0) {
1658                                 gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1659                                                         1);
1660                                 msleep(5);
1661                         }
1662
1663                         codec->cache_only = false;
1664                         snd_soc_cache_sync(codec);
1665                 }
1666
1667                 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
1668                                     WM8996_BG_ENA, 0);
1669                 break;
1670
1671         case SND_SOC_BIAS_OFF:
1672                 codec->cache_only = true;
1673                 if (wm8996->pdata.ldo_ena >= 0)
1674                         gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1675                 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1676                                        wm8996->supplies);
1677                 break;
1678         }
1679
1680         codec->dapm.bias_level = level;
1681
1682         return 0;
1683 }
1684
1685 static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1686 {
1687         struct snd_soc_codec *codec = dai->codec;
1688         int aifctrl = 0;
1689         int bclk = 0;
1690         int lrclk_tx = 0;
1691         int lrclk_rx = 0;
1692         int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1693
1694         switch (dai->id) {
1695         case 0:
1696                 aifctrl_reg = WM8996_AIF1_CONTROL;
1697                 bclk_reg = WM8996_AIF1_BCLK;
1698                 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1699                 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1700                 break;
1701         case 1:
1702                 aifctrl_reg = WM8996_AIF2_CONTROL;
1703                 bclk_reg = WM8996_AIF2_BCLK;
1704                 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1705                 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1706                 break;
1707         default:
1708                 BUG();
1709                 return -EINVAL;
1710         }
1711
1712         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1713         case SND_SOC_DAIFMT_NB_NF:
1714                 break;
1715         case SND_SOC_DAIFMT_IB_NF:
1716                 bclk |= WM8996_AIF1_BCLK_INV;
1717                 break;
1718         case SND_SOC_DAIFMT_NB_IF:
1719                 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1720                 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1721                 break;
1722         case SND_SOC_DAIFMT_IB_IF:
1723                 bclk |= WM8996_AIF1_BCLK_INV;
1724                 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1725                 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1726                 break;
1727         }
1728
1729         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1730         case SND_SOC_DAIFMT_CBS_CFS:
1731                 break;
1732         case SND_SOC_DAIFMT_CBS_CFM:
1733                 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1734                 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1735                 break;
1736         case SND_SOC_DAIFMT_CBM_CFS:
1737                 bclk |= WM8996_AIF1_BCLK_MSTR;
1738                 break;
1739         case SND_SOC_DAIFMT_CBM_CFM:
1740                 bclk |= WM8996_AIF1_BCLK_MSTR;
1741                 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1742                 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1743                 break;
1744         default:
1745                 return -EINVAL;
1746         }
1747
1748         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1749         case SND_SOC_DAIFMT_DSP_A:
1750                 break;
1751         case SND_SOC_DAIFMT_DSP_B:
1752                 aifctrl |= 1;
1753                 break;
1754         case SND_SOC_DAIFMT_I2S:
1755                 aifctrl |= 2;
1756                 break;
1757         case SND_SOC_DAIFMT_LEFT_J:
1758                 aifctrl |= 3;
1759                 break;
1760         default:
1761                 return -EINVAL;
1762         }
1763
1764         snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1765         snd_soc_update_bits(codec, bclk_reg,
1766                             WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1767                             bclk);
1768         snd_soc_update_bits(codec, lrclk_tx_reg,
1769                             WM8996_AIF1TX_LRCLK_INV |
1770                             WM8996_AIF1TX_LRCLK_MSTR,
1771                             lrclk_tx);
1772         snd_soc_update_bits(codec, lrclk_rx_reg,
1773                             WM8996_AIF1RX_LRCLK_INV |
1774                             WM8996_AIF1RX_LRCLK_MSTR,
1775                             lrclk_rx);
1776
1777         return 0;
1778 }
1779
1780 static const int dsp_divs[] = {
1781         48000, 32000, 16000, 8000
1782 };
1783
1784 static int wm8996_hw_params(struct snd_pcm_substream *substream,
1785                             struct snd_pcm_hw_params *params,
1786                             struct snd_soc_dai *dai)
1787 {
1788         struct snd_soc_codec *codec = dai->codec;
1789         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1790         int bits, i, bclk_rate;
1791         int aifdata = 0;
1792         int lrclk = 0;
1793         int dsp = 0;
1794         int aifdata_reg, lrclk_reg, dsp_shift;
1795
1796         switch (dai->id) {
1797         case 0:
1798                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1799                     (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1800                         aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1801                         lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1802                 } else {
1803                         aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1804                         lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1805                 }
1806                 dsp_shift = 0;
1807                 break;
1808         case 1:
1809                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1810                     (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1811                         aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1812                         lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1813                 } else {
1814                         aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1815                         lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1816                 }
1817                 dsp_shift = WM8996_DSP2_DIV_SHIFT;
1818                 break;
1819         default:
1820                 BUG();
1821                 return -EINVAL;
1822         }
1823
1824         bclk_rate = snd_soc_params_to_bclk(params);
1825         if (bclk_rate < 0) {
1826                 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1827                 return bclk_rate;
1828         }
1829
1830         wm8996->bclk_rate[dai->id] = bclk_rate;
1831         wm8996->rx_rate[dai->id] = params_rate(params);
1832
1833         /* Needs looking at for TDM */
1834         bits = snd_pcm_format_width(params_format(params));
1835         if (bits < 0)
1836                 return bits;
1837         aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1838
1839         for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1840                 if (dsp_divs[i] == params_rate(params))
1841                         break;
1842         }
1843         if (i == ARRAY_SIZE(dsp_divs)) {
1844                 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1845                         params_rate(params));
1846                 return -EINVAL;
1847         }
1848         dsp |= i << dsp_shift;
1849
1850         wm8996_update_bclk(codec);
1851
1852         lrclk = bclk_rate / params_rate(params);
1853         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1854                 lrclk, bclk_rate / lrclk);
1855
1856         snd_soc_update_bits(codec, aifdata_reg,
1857                             WM8996_AIF1TX_WL_MASK |
1858                             WM8996_AIF1TX_SLOT_LEN_MASK,
1859                             aifdata);
1860         snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1861                             lrclk);
1862         snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2,
1863                             WM8996_DSP1_DIV_SHIFT << dsp_shift, dsp);
1864
1865         return 0;
1866 }
1867
1868 static int wm8996_set_sysclk(struct snd_soc_dai *dai,
1869                 int clk_id, unsigned int freq, int dir)
1870 {
1871         struct snd_soc_codec *codec = dai->codec;
1872         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1873         int lfclk = 0;
1874         int ratediv = 0;
1875         int src;
1876         int old;
1877
1878         if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
1879                 return 0;
1880
1881         /* Disable SYSCLK while we reconfigure */
1882         old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
1883         snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1884                             WM8996_SYSCLK_ENA, 0);
1885
1886         switch (clk_id) {
1887         case WM8996_SYSCLK_MCLK1:
1888                 wm8996->sysclk = freq;
1889                 src = 0;
1890                 break;
1891         case WM8996_SYSCLK_MCLK2:
1892                 wm8996->sysclk = freq;
1893                 src = 1;
1894                 break;
1895         case WM8996_SYSCLK_FLL:
1896                 wm8996->sysclk = freq;
1897                 src = 2;
1898                 break;
1899         default:
1900                 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
1901                 return -EINVAL;
1902         }
1903
1904         switch (wm8996->sysclk) {
1905         case 6144000:
1906                 snd_soc_update_bits(codec, WM8996_AIF_RATE,
1907                                     WM8996_SYSCLK_RATE, 0);
1908                 break;
1909         case 24576000:
1910                 ratediv = WM8996_SYSCLK_DIV;
1911         case 12288000:
1912                 snd_soc_update_bits(codec, WM8996_AIF_RATE,
1913                                     WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
1914                 break;
1915         case 32000:
1916         case 32768:
1917                 lfclk = WM8996_LFCLK_ENA;
1918                 break;
1919         default:
1920                 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
1921                          wm8996->sysclk);
1922                 return -EINVAL;
1923         }
1924
1925         wm8996_update_bclk(codec);
1926
1927         snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1928                             WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
1929                             src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
1930         snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
1931         snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1932                             WM8996_SYSCLK_ENA, old);
1933
1934         wm8996->sysclk_src = clk_id;
1935
1936         return 0;
1937 }
1938
1939 struct _fll_div {
1940         u16 fll_fratio;
1941         u16 fll_outdiv;
1942         u16 fll_refclk_div;
1943         u16 fll_loop_gain;
1944         u16 fll_ref_freq;
1945         u16 n;
1946         u16 theta;
1947         u16 lambda;
1948 };
1949
1950 static struct {
1951         unsigned int min;
1952         unsigned int max;
1953         u16 fll_fratio;
1954         int ratio;
1955 } fll_fratios[] = {
1956         {       0,    64000, 4, 16 },
1957         {   64000,   128000, 3,  8 },
1958         {  128000,   256000, 2,  4 },
1959         {  256000,  1000000, 1,  2 },
1960         { 1000000, 13500000, 0,  1 },
1961 };
1962
1963 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1964                        unsigned int Fout)
1965 {
1966         unsigned int target;
1967         unsigned int div;
1968         unsigned int fratio, gcd_fll;
1969         int i;
1970
1971         /* Fref must be <=13.5MHz */
1972         div = 1;
1973         fll_div->fll_refclk_div = 0;
1974         while ((Fref / div) > 13500000) {
1975                 div *= 2;
1976                 fll_div->fll_refclk_div++;
1977
1978                 if (div > 8) {
1979                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1980                                Fref);
1981                         return -EINVAL;
1982                 }
1983         }
1984
1985         pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1986
1987         /* Apply the division for our remaining calculations */
1988         Fref /= div;
1989
1990         if (Fref >= 3000000)
1991                 fll_div->fll_loop_gain = 5;
1992         else
1993                 fll_div->fll_loop_gain = 0;
1994
1995         if (Fref >= 48000)
1996                 fll_div->fll_ref_freq = 0;
1997         else
1998                 fll_div->fll_ref_freq = 1;
1999
2000         /* Fvco should be 90-100MHz; don't check the upper bound */
2001         div = 2;
2002         while (Fout * div < 90000000) {
2003                 div++;
2004                 if (div > 64) {
2005                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2006                                Fout);
2007                         return -EINVAL;
2008                 }
2009         }
2010         target = Fout * div;
2011         fll_div->fll_outdiv = div - 1;
2012
2013         pr_debug("FLL Fvco=%dHz\n", target);
2014
2015         /* Find an appropraite FLL_FRATIO and factor it out of the target */
2016         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2017                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2018                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2019                         fratio = fll_fratios[i].ratio;
2020                         break;
2021                 }
2022         }
2023         if (i == ARRAY_SIZE(fll_fratios)) {
2024                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2025                 return -EINVAL;
2026         }
2027
2028         fll_div->n = target / (fratio * Fref);
2029
2030         if (target % Fref == 0) {
2031                 fll_div->theta = 0;
2032                 fll_div->lambda = 0;
2033         } else {
2034                 gcd_fll = gcd(target, fratio * Fref);
2035
2036                 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2037                         / gcd_fll;
2038                 fll_div->lambda = (fratio * Fref) / gcd_fll;
2039         }
2040
2041         pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2042                  fll_div->n, fll_div->theta, fll_div->lambda);
2043         pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2044                  fll_div->fll_fratio, fll_div->fll_outdiv,
2045                  fll_div->fll_refclk_div);
2046
2047         return 0;
2048 }
2049
2050 static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2051                           unsigned int Fref, unsigned int Fout)
2052 {
2053         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2054         struct i2c_client *i2c = to_i2c_client(codec->dev);
2055         struct _fll_div fll_div;
2056         unsigned long timeout;
2057         int ret, reg;
2058
2059         /* Any change? */
2060         if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2061             Fout == wm8996->fll_fout)
2062                 return 0;
2063
2064         if (Fout == 0) {
2065                 dev_dbg(codec->dev, "FLL disabled\n");
2066
2067                 wm8996->fll_fref = 0;
2068                 wm8996->fll_fout = 0;
2069
2070                 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2071                                     WM8996_FLL_ENA, 0);
2072
2073                 return 0;
2074         }
2075
2076         ret = fll_factors(&fll_div, Fref, Fout);
2077         if (ret != 0)
2078                 return ret;
2079
2080         switch (source) {
2081         case WM8996_FLL_MCLK1:
2082                 reg = 0;
2083                 break;
2084         case WM8996_FLL_MCLK2:
2085                 reg = 1;
2086                 break;
2087         case WM8996_FLL_DACLRCLK1:
2088                 reg = 2;
2089                 break;
2090         case WM8996_FLL_BCLK1:
2091                 reg = 3;
2092                 break;
2093         default:
2094                 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2095                 return -EINVAL;
2096         }
2097
2098         reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2099         reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2100
2101         snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5,
2102                             WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2103                             WM8996_FLL_REFCLK_SRC_MASK, reg);
2104
2105         reg = 0;
2106         if (fll_div.theta || fll_div.lambda)
2107                 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2108         else
2109                 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2110         snd_soc_write(codec, WM8996_FLL_EFS_2, reg);
2111
2112         snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2,
2113                             WM8996_FLL_OUTDIV_MASK |
2114                             WM8996_FLL_FRATIO_MASK,
2115                             (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2116                             (fll_div.fll_fratio));
2117
2118         snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta);
2119
2120         snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4,
2121                             WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2122                             (fll_div.n << WM8996_FLL_N_SHIFT) |
2123                             fll_div.fll_loop_gain);
2124
2125         snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda);
2126
2127         /* Clear any pending completions (eg, from failed startups) */
2128         try_wait_for_completion(&wm8996->fll_lock);
2129
2130         snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2131                             WM8996_FLL_ENA, WM8996_FLL_ENA);
2132
2133         /* The FLL supports live reconfiguration - kick that in case we were
2134          * already enabled.
2135          */
2136         snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2137
2138         /* Wait for the FLL to lock, using the interrupt if possible */
2139         if (Fref > 1000000)
2140                 timeout = usecs_to_jiffies(300);
2141         else
2142                 timeout = msecs_to_jiffies(2);
2143
2144         /* Allow substantially longer if we've actually got the IRQ */
2145         if (i2c->irq)
2146                 timeout *= 1000;
2147
2148         ret = wait_for_completion_timeout(&wm8996->fll_lock, timeout);
2149
2150         if (ret == 0 && i2c->irq) {
2151                 dev_err(codec->dev, "Timed out waiting for FLL\n");
2152                 ret = -ETIMEDOUT;
2153         } else {
2154                 ret = 0;
2155         }
2156
2157         dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2158
2159         wm8996->fll_fref = Fref;
2160         wm8996->fll_fout = Fout;
2161         wm8996->fll_src = source;
2162
2163         return ret;
2164 }
2165
2166 #ifdef CONFIG_GPIOLIB
2167 static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip)
2168 {
2169         return container_of(chip, struct wm8996_priv, gpio_chip);
2170 }
2171
2172 static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2173 {
2174         struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2175         struct snd_soc_codec *codec = wm8996->codec;
2176
2177         snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2178                             WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
2179 }
2180
2181 static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2182                                      unsigned offset, int value)
2183 {
2184         struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2185         struct snd_soc_codec *codec = wm8996->codec;
2186         int val;
2187
2188         val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2189
2190         return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2191                                    WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2192                                    WM8996_GP1_LVL, val);
2193 }
2194
2195 static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2196 {
2197         struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2198         struct snd_soc_codec *codec = wm8996->codec;
2199         int ret;
2200
2201         ret = snd_soc_read(codec, WM8996_GPIO_1 + offset);
2202         if (ret < 0)
2203                 return ret;
2204
2205         return (ret & WM8996_GP1_LVL) != 0;
2206 }
2207
2208 static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2209 {
2210         struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2211         struct snd_soc_codec *codec = wm8996->codec;
2212
2213         return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2214                                    WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2215                                    (1 << WM8996_GP1_FN_SHIFT) |
2216                                    (1 << WM8996_GP1_DIR_SHIFT));
2217 }
2218
2219 static struct gpio_chip wm8996_template_chip = {
2220         .label                  = "wm8996",
2221         .owner                  = THIS_MODULE,
2222         .direction_output       = wm8996_gpio_direction_out,
2223         .set                    = wm8996_gpio_set,
2224         .direction_input        = wm8996_gpio_direction_in,
2225         .get                    = wm8996_gpio_get,
2226         .can_sleep              = 1,
2227 };
2228
2229 static void wm8996_init_gpio(struct snd_soc_codec *codec)
2230 {
2231         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2232         int ret;
2233
2234         wm8996->gpio_chip = wm8996_template_chip;
2235         wm8996->gpio_chip.ngpio = 5;
2236         wm8996->gpio_chip.dev = codec->dev;
2237
2238         if (wm8996->pdata.gpio_base)
2239                 wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
2240         else
2241                 wm8996->gpio_chip.base = -1;
2242
2243         ret = gpiochip_add(&wm8996->gpio_chip);
2244         if (ret != 0)
2245                 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
2246 }
2247
2248 static void wm8996_free_gpio(struct snd_soc_codec *codec)
2249 {
2250         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2251         int ret;
2252
2253         ret = gpiochip_remove(&wm8996->gpio_chip);
2254         if (ret != 0)
2255                 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
2256 }
2257 #else
2258 static void wm8996_init_gpio(struct snd_soc_codec *codec)
2259 {
2260 }
2261
2262 static void wm8996_free_gpio(struct snd_soc_codec *codec)
2263 {
2264 }
2265 #endif
2266
2267 /**
2268  * wm8996_detect - Enable default WM8996 jack detection
2269  *
2270  * The WM8996 has advanced accessory detection support for headsets.
2271  * This function provides a default implementation which integrates
2272  * the majority of this functionality with minimal user configuration.
2273  *
2274  * This will detect headset, headphone and short circuit button and
2275  * will also detect inverted microphone ground connections and update
2276  * the polarity of the connections.
2277  */
2278 int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2279                   wm8996_polarity_fn polarity_cb)
2280 {
2281         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2282
2283         wm8996->jack = jack;
2284         wm8996->detecting = true;
2285         wm8996->polarity_cb = polarity_cb;
2286
2287         if (wm8996->polarity_cb)
2288                 wm8996->polarity_cb(codec, 0);
2289
2290         /* Clear discarge to avoid noise during detection */
2291         snd_soc_update_bits(codec, WM8996_MICBIAS_1,
2292                             WM8996_MICB1_DISCH, 0);
2293         snd_soc_update_bits(codec, WM8996_MICBIAS_2,
2294                             WM8996_MICB2_DISCH, 0);
2295
2296         /* LDO2 powers the microphones, SYSCLK clocks detection */
2297         snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2298         snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2299
2300         /* We start off just enabling microphone detection - even a
2301          * plain headphone will trigger detection.
2302          */
2303         snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2304                             WM8996_MICD_ENA, WM8996_MICD_ENA);
2305
2306         /* Slowest detection rate, gives debounce for initial detection */
2307         snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2308                             WM8996_MICD_RATE_MASK,
2309                             WM8996_MICD_RATE_MASK);
2310
2311         /* Enable interrupts and we're off */
2312         snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK,
2313                             WM8996_IM_MICD_EINT, 0);
2314
2315         return 0;
2316 }
2317 EXPORT_SYMBOL_GPL(wm8996_detect);
2318
2319 static void wm8996_micd(struct snd_soc_codec *codec)
2320 {
2321         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2322         int val, reg;
2323
2324         val = snd_soc_read(codec, WM8996_MIC_DETECT_3);
2325
2326         dev_dbg(codec->dev, "Microphone event: %x\n", val);
2327
2328         if (!(val & WM8996_MICD_VALID)) {
2329                 dev_warn(codec->dev, "Microphone detection state invalid\n");
2330                 return;
2331         }
2332
2333         /* No accessory, reset everything and report removal */
2334         if (!(val & WM8996_MICD_STS)) {
2335                 dev_dbg(codec->dev, "Jack removal detected\n");
2336                 wm8996->jack_mic = false;
2337                 wm8996->detecting = true;
2338                 snd_soc_jack_report(wm8996->jack, 0,
2339                                     SND_JACK_HEADSET | SND_JACK_BTN_0);
2340                 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2341                                     WM8996_MICD_RATE_MASK,
2342                                     WM8996_MICD_RATE_MASK);
2343                 return;
2344         }
2345
2346         /* If the measurement is very high we've got a microphone but
2347          * do a little debounce to account for mechanical issues.
2348          */
2349         if (val & 0x400) {
2350                 dev_dbg(codec->dev, "Microphone detected\n");
2351                 snd_soc_jack_report(wm8996->jack, SND_JACK_HEADSET,
2352                                     SND_JACK_HEADSET | SND_JACK_BTN_0);
2353                 wm8996->jack_mic = true;
2354                 wm8996->detecting = false;
2355
2356                 /* Increase poll rate to give better responsiveness
2357                  * for buttons */
2358                 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2359                                     WM8996_MICD_RATE_MASK,
2360                                     5 << WM8996_MICD_RATE_SHIFT);
2361         }
2362
2363         /* If we detected a lower impedence during initial startup
2364          * then we probably have the wrong polarity, flip it.  Don't
2365          * do this for the lowest impedences to speed up detection of
2366          * plain headphones.
2367          */
2368         if (wm8996->detecting && (val & 0x3f0)) {
2369                 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2);
2370                 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2371                         WM8996_MICD_BIAS_SRC;
2372                 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2373                                     WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2374                                     WM8996_MICD_BIAS_SRC, reg);
2375
2376                 if (wm8996->polarity_cb)
2377                         wm8996->polarity_cb(codec,
2378                                             (reg & WM8996_MICD_SRC) != 0);
2379
2380                 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2381                         (reg & WM8996_MICD_SRC) != 0);
2382
2383                 return;
2384         }
2385
2386         /* Don't distinguish between buttons, just report any low
2387          * impedence as BTN_0.
2388          */
2389         if (val & 0x3fc) {
2390                 if (wm8996->jack_mic) {
2391                         dev_dbg(codec->dev, "Mic button detected\n");
2392                         snd_soc_jack_report(wm8996->jack,
2393                                             SND_JACK_HEADSET | SND_JACK_BTN_0,
2394                                             SND_JACK_HEADSET | SND_JACK_BTN_0);
2395                 } else {
2396                         dev_dbg(codec->dev, "Headphone detected\n");
2397                         snd_soc_jack_report(wm8996->jack,
2398                                             SND_JACK_HEADPHONE,
2399                                             SND_JACK_HEADSET |
2400                                             SND_JACK_BTN_0);
2401
2402                         /* Increase the detection rate a bit for
2403                          * responsiveness.
2404                          */
2405                         snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2406                                             WM8996_MICD_RATE_MASK,
2407                                             7 << WM8996_MICD_RATE_SHIFT);
2408
2409                         wm8996->detecting = false;
2410                 }
2411         }
2412 }
2413
2414 static irqreturn_t wm8996_irq(int irq, void *data)
2415 {
2416         struct snd_soc_codec *codec = data;
2417         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2418         int irq_val;
2419
2420         irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2);
2421         if (irq_val < 0) {
2422                 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2423                         irq_val);
2424                 return IRQ_NONE;
2425         }
2426         irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK);
2427
2428         if (!irq_val)
2429                 return IRQ_NONE;
2430
2431         snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val);
2432
2433         if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2434                 dev_dbg(codec->dev, "DC servo IRQ\n");
2435                 complete(&wm8996->dcs_done);
2436         }
2437
2438         if (irq_val & WM8996_FIFOS_ERR_EINT)
2439                 dev_err(codec->dev, "Digital core FIFO error\n");
2440
2441         if (irq_val & WM8996_FLL_LOCK_EINT) {
2442                 dev_dbg(codec->dev, "FLL locked\n");
2443                 complete(&wm8996->fll_lock);
2444         }
2445
2446         if (irq_val & WM8996_MICD_EINT)
2447                 wm8996_micd(codec);
2448
2449         return IRQ_HANDLED;
2450 }
2451
2452 static irqreturn_t wm8996_edge_irq(int irq, void *data)
2453 {
2454         irqreturn_t ret = IRQ_NONE;
2455         irqreturn_t val;
2456
2457         do {
2458                 val = wm8996_irq(irq, data);
2459                 if (val != IRQ_NONE)
2460                         ret = val;
2461         } while (val != IRQ_NONE);
2462
2463         return ret;
2464 }
2465
2466 static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec)
2467 {
2468         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2469         struct wm8996_pdata *pdata = &wm8996->pdata;
2470
2471         struct snd_kcontrol_new controls[] = {
2472                 SOC_ENUM_EXT("DSP1 EQ Mode",
2473                              wm8996->retune_mobile_enum,
2474                              wm8996_get_retune_mobile_enum,
2475                              wm8996_put_retune_mobile_enum),
2476                 SOC_ENUM_EXT("DSP2 EQ Mode",
2477                              wm8996->retune_mobile_enum,
2478                              wm8996_get_retune_mobile_enum,
2479                              wm8996_put_retune_mobile_enum),
2480         };
2481         int ret, i, j;
2482         const char **t;
2483
2484         /* We need an array of texts for the enum API but the number
2485          * of texts is likely to be less than the number of
2486          * configurations due to the sample rate dependency of the
2487          * configurations. */
2488         wm8996->num_retune_mobile_texts = 0;
2489         wm8996->retune_mobile_texts = NULL;
2490         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2491                 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2492                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2493                                    wm8996->retune_mobile_texts[j]) == 0)
2494                                 break;
2495                 }
2496
2497                 if (j != wm8996->num_retune_mobile_texts)
2498                         continue;
2499
2500                 /* Expand the array... */
2501                 t = krealloc(wm8996->retune_mobile_texts,
2502                              sizeof(char *) *
2503                              (wm8996->num_retune_mobile_texts + 1),
2504                              GFP_KERNEL);
2505                 if (t == NULL)
2506                         continue;
2507
2508                 /* ...store the new entry... */
2509                 t[wm8996->num_retune_mobile_texts] =
2510                         pdata->retune_mobile_cfgs[i].name;
2511
2512                 /* ...and remember the new version. */
2513                 wm8996->num_retune_mobile_texts++;
2514                 wm8996->retune_mobile_texts = t;
2515         }
2516
2517         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2518                 wm8996->num_retune_mobile_texts);
2519
2520         wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts;
2521         wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2522
2523         ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
2524         if (ret != 0)
2525                 dev_err(codec->dev,
2526                         "Failed to add ReTune Mobile controls: %d\n", ret);
2527 }
2528
2529 static int wm8996_probe(struct snd_soc_codec *codec)
2530 {
2531         int ret;
2532         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2533         struct i2c_client *i2c = to_i2c_client(codec->dev);
2534         struct snd_soc_dapm_context *dapm = &codec->dapm;
2535         int i, irq_flags;
2536
2537         wm8996->codec = codec;
2538
2539         init_completion(&wm8996->dcs_done);
2540         init_completion(&wm8996->fll_lock);
2541
2542         dapm->idle_bias_off = true;
2543         dapm->bias_level = SND_SOC_BIAS_OFF;
2544
2545         ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
2546         if (ret != 0) {
2547                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2548                 goto err;
2549         }
2550
2551         for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
2552                 wm8996->supplies[i].supply = wm8996_supply_names[i];
2553
2554         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8996->supplies),
2555                                  wm8996->supplies);
2556         if (ret != 0) {
2557                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2558                 goto err;
2559         }
2560
2561         wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2562         wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2563         wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
2564         wm8996->disable_nb[3].notifier_call = wm8996_regulator_event_3;
2565
2566         /* This should really be moved into the regulator core */
2567         for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2568                 ret = regulator_register_notifier(wm8996->supplies[i].consumer,
2569                                                   &wm8996->disable_nb[i]);
2570                 if (ret != 0) {
2571                         dev_err(codec->dev,
2572                                 "Failed to register regulator notifier: %d\n",
2573                                 ret);
2574                 }
2575         }
2576
2577         ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
2578                                     wm8996->supplies);
2579         if (ret != 0) {
2580                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2581                 goto err_get;
2582         }
2583
2584         if (wm8996->pdata.ldo_ena >= 0) {
2585                 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
2586                 msleep(5);
2587         }
2588
2589         ret = snd_soc_read(codec, WM8996_SOFTWARE_RESET);
2590         if (ret < 0) {
2591                 dev_err(codec->dev, "Failed to read ID register: %d\n", ret);
2592                 goto err_enable;
2593         }
2594         if (ret != 0x8915) {
2595                 dev_err(codec->dev, "Device is not a WM8996, ID %x\n", ret);
2596                 ret = -EINVAL;
2597                 goto err_enable;
2598         }
2599
2600         ret = snd_soc_read(codec, WM8996_CHIP_REVISION);
2601         if (ret < 0) {
2602                 dev_err(codec->dev, "Failed to read device revision: %d\n",
2603                         ret);
2604                 goto err_enable;
2605         }
2606
2607         dev_info(codec->dev, "revision %c\n",
2608                  (ret & WM8996_CHIP_REV_MASK) + 'A');
2609
2610         if (wm8996->pdata.ldo_ena >= 0) {
2611                 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
2612         } else {
2613                 ret = wm8996_reset(codec);
2614                 if (ret < 0) {
2615                         dev_err(codec->dev, "Failed to issue reset\n");
2616                         goto err_enable;
2617                 }
2618         }
2619
2620         codec->cache_only = true;
2621
2622         /* Apply platform data settings */
2623         snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL,
2624                             WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2625                             wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2626                             wm8996->pdata.inr_mode);
2627
2628         for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2629                 if (!wm8996->pdata.gpio_default[i])
2630                         continue;
2631
2632                 snd_soc_write(codec, WM8996_GPIO_1 + i,
2633                               wm8996->pdata.gpio_default[i] & 0xffff);
2634         }
2635
2636         if (wm8996->pdata.spkmute_seq)
2637                 snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2638                                     WM8996_SPK_MUTE_ENDIAN |
2639                                     WM8996_SPK_MUTE_SEQ1_MASK,
2640                                     wm8996->pdata.spkmute_seq);
2641
2642         snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2643                             WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2644                             WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2645
2646         /* Latch volume update bits */
2647         snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME,
2648                             WM8996_IN1_VU, WM8996_IN1_VU);
2649         snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME,
2650                             WM8996_IN1_VU, WM8996_IN1_VU);
2651
2652         snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME,
2653                             WM8996_DAC1_VU, WM8996_DAC1_VU);
2654         snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME,
2655                             WM8996_DAC1_VU, WM8996_DAC1_VU);
2656         snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME,
2657                             WM8996_DAC2_VU, WM8996_DAC2_VU);
2658         snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME,
2659                             WM8996_DAC2_VU, WM8996_DAC2_VU);
2660
2661         snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME,
2662                             WM8996_DAC1_VU, WM8996_DAC1_VU);
2663         snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME,
2664                             WM8996_DAC1_VU, WM8996_DAC1_VU);
2665         snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME,
2666                             WM8996_DAC2_VU, WM8996_DAC2_VU);
2667         snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME,
2668                             WM8996_DAC2_VU, WM8996_DAC2_VU);
2669
2670         snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME,
2671                             WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2672         snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME,
2673                             WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2674         snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME,
2675                             WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2676         snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME,
2677                             WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2678
2679         snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME,
2680                             WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2681         snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME,
2682                             WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2683         snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME,
2684                             WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2685         snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME,
2686                             WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2687
2688         /* No support currently for the underclocked TDM modes and
2689          * pick a default TDM layout with each channel pair working with
2690          * slots 0 and 1. */
2691         snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2692                             WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2693                             WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2694                             1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2695         snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2696                             WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2697                             WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2698                             1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2699         snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2700                             WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2701                             WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2702                             1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2703         snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2704                             WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2705                             WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2706                             1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2707         snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2708                             WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2709                             WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2710                             1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2711         snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2712                             WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2713                             WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2714                             1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2715
2716         snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2717                             WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2718                             WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2719                             1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2720         snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2721                             WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2722                             WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2723                             1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2724
2725         snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2726                             WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2727                             WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2728                             1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2729         snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2730                             WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2731                             WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2732                             1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2733         snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2734                             WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2735                             WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2736                             1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2737         snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
2738                             WM8996_AIF1TX_CHAN3_SLOTS_MASK |
2739                             WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2740                             1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2741         snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
2742                             WM8996_AIF1TX_CHAN4_SLOTS_MASK |
2743                             WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2744                             1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2745         snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
2746                             WM8996_AIF1TX_CHAN5_SLOTS_MASK |
2747                             WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2748                             1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2749
2750         snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
2751                             WM8996_AIF2TX_CHAN0_SLOTS_MASK |
2752                             WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
2753                             1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2754         snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2755                             WM8996_AIF2TX_CHAN1_SLOTS_MASK |
2756                             WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
2757                             1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2758
2759         if (wm8996->pdata.num_retune_mobile_cfgs)
2760                 wm8996_retune_mobile_pdata(codec);
2761         else
2762                 snd_soc_add_controls(codec, wm8996_eq_controls,
2763                                      ARRAY_SIZE(wm8996_eq_controls));
2764
2765         /* If the TX LRCLK pins are not in LRCLK mode configure the
2766          * AIFs to source their clocks from the RX LRCLKs.
2767          */
2768         if ((snd_soc_read(codec, WM8996_GPIO_1)))
2769                 snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2,
2770                                     WM8996_AIF1TX_LRCLK_MODE,
2771                                     WM8996_AIF1TX_LRCLK_MODE);
2772
2773         if ((snd_soc_read(codec, WM8996_GPIO_2)))
2774                 snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2,
2775                                     WM8996_AIF2TX_LRCLK_MODE,
2776                                     WM8996_AIF2TX_LRCLK_MODE);
2777
2778         regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2779
2780         wm8996_init_gpio(codec);
2781
2782         if (i2c->irq) {
2783                 if (wm8996->pdata.irq_flags)
2784                         irq_flags = wm8996->pdata.irq_flags;
2785                 else
2786                         irq_flags = IRQF_TRIGGER_LOW;
2787
2788                 irq_flags |= IRQF_ONESHOT;
2789
2790                 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2791                         ret = request_threaded_irq(i2c->irq, NULL,
2792                                                    wm8996_edge_irq,
2793                                                    irq_flags, "wm8996", codec);
2794                 else
2795                         ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
2796                                                    irq_flags, "wm8996", codec);
2797
2798                 if (ret == 0) {
2799                         /* Unmask the interrupt */
2800                         snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2801                                             WM8996_IM_IRQ, 0);
2802
2803                         /* Enable error reporting and DC servo status */
2804                         snd_soc_update_bits(codec,
2805                                             WM8996_INTERRUPT_STATUS_2_MASK,
2806                                             WM8996_IM_DCS_DONE_23_EINT |
2807                                             WM8996_IM_DCS_DONE_01_EINT |
2808                                             WM8996_IM_FLL_LOCK_EINT |
2809                                             WM8996_IM_FIFOS_ERR_EINT,
2810                                             0);
2811                 } else {
2812                         dev_err(codec->dev, "Failed to request IRQ: %d\n",
2813                                 ret);
2814                 }
2815         }
2816
2817         return 0;
2818
2819 err_enable:
2820         if (wm8996->pdata.ldo_ena >= 0)
2821                 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
2822
2823         regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2824 err_get:
2825         regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2826 err:
2827         return ret;
2828 }
2829
2830 static int wm8996_remove(struct snd_soc_codec *codec)
2831 {
2832         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2833         struct i2c_client *i2c = to_i2c_client(codec->dev);
2834         int i;
2835
2836         snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2837                             WM8996_IM_IRQ, WM8996_IM_IRQ);
2838
2839         if (i2c->irq)
2840                 free_irq(i2c->irq, codec);
2841
2842         wm8996_free_gpio(codec);
2843
2844         for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
2845                 regulator_unregister_notifier(wm8996->supplies[i].consumer,
2846                                               &wm8996->disable_nb[i]);
2847         regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2848
2849         return 0;
2850 }
2851
2852 static struct snd_soc_codec_driver soc_codec_dev_wm8996 = {
2853         .probe =        wm8996_probe,
2854         .remove =       wm8996_remove,
2855         .set_bias_level = wm8996_set_bias_level,
2856         .seq_notifier = wm8996_seq_notifier,
2857         .reg_cache_size = WM8996_MAX_REGISTER + 1,
2858         .reg_word_size = sizeof(u16),
2859         .reg_cache_default = wm8996_reg,
2860         .volatile_register = wm8996_volatile_register,
2861         .readable_register = wm8996_readable_register,
2862         .compress_type = SND_SOC_RBTREE_COMPRESSION,
2863         .controls = wm8996_snd_controls,
2864         .num_controls = ARRAY_SIZE(wm8996_snd_controls),
2865         .dapm_widgets = wm8996_dapm_widgets,
2866         .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
2867         .dapm_routes = wm8996_dapm_routes,
2868         .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
2869         .set_pll = wm8996_set_fll,
2870 };
2871
2872 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
2873                       SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
2874 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
2875                         SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
2876                         SNDRV_PCM_FMTBIT_S32_LE)
2877
2878 static struct snd_soc_dai_ops wm8996_dai_ops = {
2879         .set_fmt = wm8996_set_fmt,
2880         .hw_params = wm8996_hw_params,
2881         .set_sysclk = wm8996_set_sysclk,
2882 };
2883
2884 static struct snd_soc_dai_driver wm8996_dai[] = {
2885         {
2886                 .name = "wm8996-aif1",
2887                 .playback = {
2888                         .stream_name = "AIF1 Playback",
2889                         .channels_min = 1,
2890                         .channels_max = 6,
2891                         .rates = WM8996_RATES,
2892                         .formats = WM8996_FORMATS,
2893                 },
2894                 .capture = {
2895                          .stream_name = "AIF1 Capture",
2896                          .channels_min = 1,
2897                          .channels_max = 6,
2898                          .rates = WM8996_RATES,
2899                          .formats = WM8996_FORMATS,
2900                  },
2901                 .ops = &wm8996_dai_ops,
2902         },
2903         {
2904                 .name = "wm8996-aif2",
2905                 .playback = {
2906                         .stream_name = "AIF2 Playback",
2907                         .channels_min = 1,
2908                         .channels_max = 2,
2909                         .rates = WM8996_RATES,
2910                         .formats = WM8996_FORMATS,
2911                 },
2912                 .capture = {
2913                          .stream_name = "AIF2 Capture",
2914                          .channels_min = 1,
2915                          .channels_max = 2,
2916                          .rates = WM8996_RATES,
2917                          .formats = WM8996_FORMATS,
2918                  },
2919                 .ops = &wm8996_dai_ops,
2920         },
2921 };
2922
2923 static __devinit int wm8996_i2c_probe(struct i2c_client *i2c,
2924                                       const struct i2c_device_id *id)
2925 {
2926         struct wm8996_priv *wm8996;
2927         int ret;
2928
2929         wm8996 = kzalloc(sizeof(struct wm8996_priv), GFP_KERNEL);
2930         if (wm8996 == NULL)
2931                 return -ENOMEM;
2932
2933         i2c_set_clientdata(i2c, wm8996);
2934
2935         if (dev_get_platdata(&i2c->dev))
2936                 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
2937                        sizeof(wm8996->pdata));
2938
2939         if (wm8996->pdata.ldo_ena > 0) {
2940                 ret = gpio_request_one(wm8996->pdata.ldo_ena,
2941                                        GPIOF_OUT_INIT_LOW, "WM8996 ENA");
2942                 if (ret < 0) {
2943                         dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
2944                                 wm8996->pdata.ldo_ena, ret);
2945                         goto err;
2946                 }
2947         }
2948
2949         ret = snd_soc_register_codec(&i2c->dev,
2950                                      &soc_codec_dev_wm8996, wm8996_dai,
2951                                      ARRAY_SIZE(wm8996_dai));
2952         if (ret < 0)
2953                 goto err_gpio;
2954
2955         return ret;
2956
2957 err_gpio:
2958         if (wm8996->pdata.ldo_ena > 0)
2959                 gpio_free(wm8996->pdata.ldo_ena);
2960 err:
2961         kfree(wm8996);
2962
2963         return ret;
2964 }
2965
2966 static __devexit int wm8996_i2c_remove(struct i2c_client *client)
2967 {
2968         struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
2969
2970         snd_soc_unregister_codec(&client->dev);
2971         if (wm8996->pdata.ldo_ena > 0)
2972                 gpio_free(wm8996->pdata.ldo_ena);
2973         kfree(i2c_get_clientdata(client));
2974         return 0;
2975 }
2976
2977 static const struct i2c_device_id wm8996_i2c_id[] = {
2978         { "wm8996", 0 },
2979         { }
2980 };
2981 MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
2982
2983 static struct i2c_driver wm8996_i2c_driver = {
2984         .driver = {
2985                 .name = "wm8996",
2986                 .owner = THIS_MODULE,
2987         },
2988         .probe =    wm8996_i2c_probe,
2989         .remove =   __devexit_p(wm8996_i2c_remove),
2990         .id_table = wm8996_i2c_id,
2991 };
2992
2993 static int __init wm8996_modinit(void)
2994 {
2995         int ret;
2996
2997         ret = i2c_add_driver(&wm8996_i2c_driver);
2998         if (ret != 0) {
2999                 printk(KERN_ERR "Failed to register WM8996 I2C driver: %d\n",
3000                        ret);
3001         }
3002
3003         return ret;
3004 }
3005 module_init(wm8996_modinit);
3006
3007 static void __exit wm8996_exit(void)
3008 {
3009         i2c_del_driver(&wm8996_i2c_driver);
3010 }
3011 module_exit(wm8996_exit);
3012
3013 MODULE_DESCRIPTION("ASoC WM8996 driver");
3014 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3015 MODULE_LICENSE("GPL");