Pileus Git - ~andy/linux/blob - sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM8994_NUM_DRC 3
  42 #define WM8994_NUM_EQ  3
  43
  44 static int wm8994_drc_base[] = {
  45         WM8994_AIF1_DRC1_1,
  46         WM8994_AIF1_DRC2_1,
  47         WM8994_AIF2_DRC_1,
  48 };
  49
  50 static int wm8994_retune_mobile_base[] = {
  51         WM8994_AIF1_DAC1_EQ_GAINS_1,
  52         WM8994_AIF1_DAC2_EQ_GAINS_1,
  53         WM8994_AIF2_EQ_GAINS_1,
  54 };
  55
  56 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
  57 {
  58         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  59         struct wm8994 *control = wm8994->control_data;
  60
  61         switch (reg) {
  62         case WM8994_GPIO_1:
  63         case WM8994_GPIO_2:
  64         case WM8994_GPIO_3:
  65         case WM8994_GPIO_4:
  66         case WM8994_GPIO_5:
  67         case WM8994_GPIO_6:
  68         case WM8994_GPIO_7:
  69         case WM8994_GPIO_8:
  70         case WM8994_GPIO_9:
  71         case WM8994_GPIO_10:
  72         case WM8994_GPIO_11:
  73         case WM8994_INTERRUPT_STATUS_1:
  74         case WM8994_INTERRUPT_STATUS_2:
  75         case WM8994_INTERRUPT_RAW_STATUS_2:
  76                 return 1;
  77
  78         case WM8958_DSP2_PROGRAM:
  79         case WM8958_DSP2_CONFIG:
  80         case WM8958_DSP2_EXECCONTROL:
  81                 if (control->type == WM8958)
  82                         return 1;
  83                 else
  84                         return 0;
  85
  86         default:
  87                 break;
  88         }
  89
  90         if (reg >= WM8994_CACHE_SIZE)
  91                 return 0;
  92         return wm8994_access_masks[reg].readable != 0;
  93 }
  94
  95 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
  96 {
  97         if (reg >= WM8994_CACHE_SIZE)
  98                 return 1;
  99
 100         switch (reg) {
 101         case WM8994_SOFTWARE_RESET:
 102         case WM8994_CHIP_REVISION:
 103         case WM8994_DC_SERVO_1:
 104         case WM8994_DC_SERVO_READBACK:
 105         case WM8994_RATE_STATUS:
 106         case WM8994_LDO_1:
 107         case WM8994_LDO_2:
 108         case WM8958_DSP2_EXECCONTROL:
 109         case WM8958_MIC_DETECT_3:
 110         case WM8994_DC_SERVO_4E:
 111                 return 1;
 112         default:
 113                 return 0;
 114         }
 115 }
 116
 117 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 118         unsigned int value)
 119 {
 120         int ret;
 121
 122         BUG_ON(reg > WM8994_MAX_REGISTER);
 123
 124         if (!wm8994_volatile(codec, reg)) {
 125                 ret = snd_soc_cache_write(codec, reg, value);
 126                 if (ret != 0)
 127                         dev_err(codec->dev, "Cache write to %x failed: %d\n",
 128                                 reg, ret);
 129         }
 130
 131         return wm8994_reg_write(codec->control_data, reg, value);
 132 }
 133
 134 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 135                                 unsigned int reg)
 136 {
 137         unsigned int val;
 138         int ret;
 139
 140         BUG_ON(reg > WM8994_MAX_REGISTER);
 141
 142         if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
 143             reg < codec->driver->reg_cache_size) {
 144                 ret = snd_soc_cache_read(codec, reg, &val);
 145                 if (ret >= 0)
 146                         return val;
 147                 else
 148                         dev_err(codec->dev, "Cache read from %x failed: %d\n",
 149                                 reg, ret);
 150         }
 151
 152         return wm8994_reg_read(codec->control_data, reg);
 153 }
 154
 155 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 156 {
 157         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 158         int rate;
 159         int reg1 = 0;
 160         int offset;
 161
 162         if (aif)
 163                 offset = 4;
 164         else
 165                 offset = 0;
 166
 167         switch (wm8994->sysclk[aif]) {
 168         case WM8994_SYSCLK_MCLK1:
 169                 rate = wm8994->mclk[0];
 170                 break;
 171
 172         case WM8994_SYSCLK_MCLK2:
 173                 reg1 |= 0x8;
 174                 rate = wm8994->mclk[1];
 175                 break;
 176
 177         case WM8994_SYSCLK_FLL1:
 178                 reg1 |= 0x10;
 179                 rate = wm8994->fll[0].out;
 180                 break;
 181
 182         case WM8994_SYSCLK_FLL2:
 183                 reg1 |= 0x18;
 184                 rate = wm8994->fll[1].out;
 185                 break;
 186
 187         default:
 188                 return -EINVAL;
 189         }
 190
 191         if (rate >= 13500000) {
 192                 rate /= 2;
 193                 reg1 |= WM8994_AIF1CLK_DIV;
 194
 195                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 196                         aif + 1, rate);
 197         }
 198
 199         wm8994->aifclk[aif] = rate;
 200
 201         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 202                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 203                             reg1);
 204
 205         return 0;
 206 }
 207
 208 static int configure_clock(struct snd_soc_codec *codec)
 209 {
 210         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 211         int old, new;
 212
 213         /* Bring up the AIF clocks first */
 214         configure_aif_clock(codec, 0);
 215         configure_aif_clock(codec, 1);
 216
 217         /* Then switch CLK_SYS over to the higher of them; a change
 218          * can only happen as a result of a clocking change which can
 219          * only be made outside of DAPM so we can safely redo the
 220          * clocking.
 221          */
 222
 223         /* If they're equal it doesn't matter which is used */
 224         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 225                 return 0;
 226
 227         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 228                 new = WM8994_SYSCLK_SRC;
 229         else
 230                 new = 0;
 231
 232         old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
 233
 234         /* If there's no change then we're done. */
 235         if (old == new)
 236                 return 0;
 237
 238         snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
 239
 240         snd_soc_dapm_sync(&codec->dapm);
 241
 242         return 0;
 243 }
 244
 245 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 246                          struct snd_soc_dapm_widget *sink)
 247 {
 248         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 249         const char *clk;
 250
 251         /* Check what we're currently using for CLK_SYS */
 252         if (reg & WM8994_SYSCLK_SRC)
 253                 clk = "AIF2CLK";
 254         else
 255                 clk = "AIF1CLK";
 256
 257         return strcmp(source->name, clk) == 0;
 258 }
 259
 260 static const char *sidetone_hpf_text[] = {
 261         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 262 };
 263
 264 static const struct soc_enum sidetone_hpf =
 265         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 266
 267 static const char *adc_hpf_text[] = {
 268         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 269 };
 270
 271 static const struct soc_enum aif1adc1_hpf =
 272         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 273
 274 static const struct soc_enum aif1adc2_hpf =
 275         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 276
 277 static const struct soc_enum aif2adc_hpf =
 278         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 279
 280 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 281 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 282 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 283 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 284 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 285
 286 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 287 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 288         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 289         .put = wm8994_put_drc_sw, \
 290         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 291
 292 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 293                              struct snd_ctl_elem_value *ucontrol)
 294 {
 295         struct soc_mixer_control *mc =
 296                 (struct soc_mixer_control *)kcontrol->private_value;
 297         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 298         int mask, ret;
 299
 300         /* Can't enable both ADC and DAC paths simultaneously */
 301         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 302                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 303                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 304         else
 305                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 306
 307         ret = snd_soc_read(codec, mc->reg);
 308         if (ret < 0)
 309                 return ret;
 310         if (ret & mask)
 311                 return -EINVAL;
 312
 313         return snd_soc_put_volsw(kcontrol, ucontrol);
 314 }
 315
 316 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 317 {
 318         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 319         struct wm8994_pdata *pdata = wm8994->pdata;
 320         int base = wm8994_drc_base[drc];
 321         int cfg = wm8994->drc_cfg[drc];
 322         int save, i;
 323
 324         /* Save any enables; the configuration should clear them. */
 325         save = snd_soc_read(codec, base);
 326         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 327                 WM8994_AIF1ADC1R_DRC_ENA;
 328
 329         for (i = 0; i < WM8994_DRC_REGS; i++)
 330                 snd_soc_update_bits(codec, base + i, 0xffff,
 331                                     pdata->drc_cfgs[cfg].regs[i]);
 332
 333         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 334                              WM8994_AIF1ADC1L_DRC_ENA |
 335                              WM8994_AIF1ADC1R_DRC_ENA, save);
 336 }
 337
 338 /* Icky as hell but saves code duplication */
 339 static int wm8994_get_drc(const char *name)
 340 {
 341         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 342                 return 0;
 343         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 344                 return 1;
 345         if (strcmp(name, "AIF2DRC Mode") == 0)
 346                 return 2;
 347         return -EINVAL;
 348 }
 349
 350 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 351                                struct snd_ctl_elem_value *ucontrol)
 352 {
 353         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 354         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 355         struct wm8994_pdata *pdata = wm8994->pdata;
 356         int drc = wm8994_get_drc(kcontrol->id.name);
 357         int value = ucontrol->value.integer.value[0];
 358
 359         if (drc < 0)
 360                 return drc;
 361
 362         if (value >= pdata->num_drc_cfgs)
 363                 return -EINVAL;
 364
 365         wm8994->drc_cfg[drc] = value;
 366
 367         wm8994_set_drc(codec, drc);
 368
 369         return 0;
 370 }
 371
 372 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 373                                struct snd_ctl_elem_value *ucontrol)
 374 {
 375         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 376         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 377         int drc = wm8994_get_drc(kcontrol->id.name);
 378
 379         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 380
 381         return 0;
 382 }
 383
 384 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 385 {
 386         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 387         struct wm8994_pdata *pdata = wm8994->pdata;
 388         int base = wm8994_retune_mobile_base[block];
 389         int iface, best, best_val, save, i, cfg;
 390
 391         if (!pdata || !wm8994->num_retune_mobile_texts)
 392                 return;
 393
 394         switch (block) {
 395         case 0:
 396         case 1:
 397                 iface = 0;
 398                 break;
 399         case 2:
 400                 iface = 1;
 401                 break;
 402         default:
 403                 return;
 404         }
 405
 406         /* Find the version of the currently selected configuration
 407          * with the nearest sample rate. */
 408         cfg = wm8994->retune_mobile_cfg[block];
 409         best = 0;
 410         best_val = INT_MAX;
 411         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 412                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 413                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 414                     abs(pdata->retune_mobile_cfgs[i].rate
 415                         - wm8994->dac_rates[iface]) < best_val) {
 416                         best = i;
 417                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 418                                        - wm8994->dac_rates[iface]);
 419                 }
 420         }
 421
 422         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 423                 block,
 424                 pdata->retune_mobile_cfgs[best].name,
 425                 pdata->retune_mobile_cfgs[best].rate,
 426                 wm8994->dac_rates[iface]);
 427
 428         /* The EQ will be disabled while reconfiguring it, remember the
 429          * current configuration.
 430          */
 431         save = snd_soc_read(codec, base);
 432         save &= WM8994_AIF1DAC1_EQ_ENA;
 433
 434         for (i = 0; i < WM8994_EQ_REGS; i++)
 435                 snd_soc_update_bits(codec, base + i, 0xffff,
 436                                 pdata->retune_mobile_cfgs[best].regs[i]);
 437
 438         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 439 }
 440
 441 /* Icky as hell but saves code duplication */
 442 static int wm8994_get_retune_mobile_block(const char *name)
 443 {
 444         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 445                 return 0;
 446         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 447                 return 1;
 448         if (strcmp(name, "AIF2 EQ Mode") == 0)
 449                 return 2;
 450         return -EINVAL;
 451 }
 452
 453 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 454                                          struct snd_ctl_elem_value *ucontrol)
 455 {
 456         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 457         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 458         struct wm8994_pdata *pdata = wm8994->pdata;
 459         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 460         int value = ucontrol->value.integer.value[0];
 461
 462         if (block < 0)
 463                 return block;
 464
 465         if (value >= pdata->num_retune_mobile_cfgs)
 466                 return -EINVAL;
 467
 468         wm8994->retune_mobile_cfg[block] = value;
 469
 470         wm8994_set_retune_mobile(codec, block);
 471
 472         return 0;
 473 }
 474
 475 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 476                                          struct snd_ctl_elem_value *ucontrol)
 477 {
 478         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 479         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 480         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 481
 482         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 483
 484         return 0;
 485 }
 486
 487 static const char *aif_chan_src_text[] = {
 488         "Left", "Right"
 489 };
 490
 491 static const struct soc_enum aif1adcl_src =
 492         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 493
 494 static const struct soc_enum aif1adcr_src =
 495         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 496
 497 static const struct soc_enum aif2adcl_src =
 498         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 499
 500 static const struct soc_enum aif2adcr_src =
 501         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 502
 503 static const struct soc_enum aif1dacl_src =
 504         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 505
 506 static const struct soc_enum aif1dacr_src =
 507         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 508
 509 static const struct soc_enum aif2dacl_src =
 510         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 511
 512 static const struct soc_enum aif2dacr_src =
 513         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 514
 515 static const char *osr_text[] = {
 516         "Low Power", "High Performance",
 517 };
 518
 519 static const struct soc_enum dac_osr =
 520         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 521
 522 static const struct soc_enum adc_osr =
 523         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 524
 525 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 526 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 527                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 528                  1, 119, 0, digital_tlv),
 529 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 530                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 531                  1, 119, 0, digital_tlv),
 532 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 533                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 534                  1, 119, 0, digital_tlv),
 535
 536 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 537 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 538 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 539 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 540
 541 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 542 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 543 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 544 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 545
 546 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 547                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 548 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 549                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 550 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 551                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 552
 553 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 554 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 555
 556 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 557 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 558 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 559
 560 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 561 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 562 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 563
 564 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 565 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 566 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 567
 568 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 569 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 570 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 571
 572 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 573                5, 12, 0, st_tlv),
 574 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 575                0, 12, 0, st_tlv),
 576 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 577                5, 12, 0, st_tlv),
 578 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 579                0, 12, 0, st_tlv),
 580 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 581 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 582
 583 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 584 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 585
 586 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 587 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 588
 589 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 590 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 591
 592 SOC_ENUM("ADC OSR", adc_osr),
 593 SOC_ENUM("DAC OSR", dac_osr),
 594
 595 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 596                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 597 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 598              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 599
 600 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 601                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 602 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 603              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 604
 605 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 606                6, 1, 1, wm_hubs_spkmix_tlv),
 607 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 608                2, 1, 1, wm_hubs_spkmix_tlv),
 609
 610 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 611                6, 1, 1, wm_hubs_spkmix_tlv),
 612 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 613                2, 1, 1, wm_hubs_spkmix_tlv),
 614
 615 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 616                10, 15, 0, wm8994_3d_tlv),
 617 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 618            8, 1, 0),
 619 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 620                10, 15, 0, wm8994_3d_tlv),
 621 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 622            8, 1, 0),
 623 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 624                10, 15, 0, wm8994_3d_tlv),
 625 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 626            8, 1, 0),
 627 };
 628
 629 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 630 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 631                eq_tlv),
 632 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 633                eq_tlv),
 634 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 635                eq_tlv),
 636 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 637                eq_tlv),
 638 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 639                eq_tlv),
 640
 641 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 642                eq_tlv),
 643 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 644                eq_tlv),
 645 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 646                eq_tlv),
 647 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 648                eq_tlv),
 649 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 650                eq_tlv),
 651
 652 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 653                eq_tlv),
 654 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 655                eq_tlv),
 656 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 657                eq_tlv),
 658 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 659                eq_tlv),
 660 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 661                eq_tlv),
 662 };
 663
 664 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 665 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 666 };
 667
 668 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 669                          struct snd_kcontrol *kcontrol, int event)
 670 {
 671         struct snd_soc_codec *codec = w->codec;
 672
 673         switch (event) {
 674         case SND_SOC_DAPM_PRE_PMU:
 675                 return configure_clock(codec);
 676
 677         case SND_SOC_DAPM_POST_PMD:
 678                 configure_clock(codec);
 679                 break;
 680         }
 681
 682         return 0;
 683 }
 684
 685 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 686 {
 687         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 688         int enable = 1;
 689         int source = 0;  /* GCC flow analysis can't track enable */
 690         int reg, reg_r;
 691
 692         /* Only support direct DAC->headphone paths */
 693         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 694         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 695                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 696                 enable = 0;
 697         }
 698
 699         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 700         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 701                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 702                 enable = 0;
 703         }
 704
 705         /* We also need the same setting for L/R and only one path */
 706         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 707         switch (reg) {
 708         case WM8994_AIF2DACL_TO_DAC1L:
 709                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 710                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 711                 break;
 712         case WM8994_AIF1DAC2L_TO_DAC1L:
 713                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 714                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 715                 break;
 716         case WM8994_AIF1DAC1L_TO_DAC1L:
 717                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 718                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 719                 break;
 720         default:
 721                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 722                 enable = 0;
 723                 break;
 724         }
 725
 726         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 727         if (reg_r != reg) {
 728                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 729                 enable = 0;
 730         }
 731
 732         if (enable) {
 733                 dev_dbg(codec->dev, "Class W enabled\n");
 734                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 735                                     WM8994_CP_DYN_PWR |
 736                                     WM8994_CP_DYN_SRC_SEL_MASK,
 737                                     source | WM8994_CP_DYN_PWR);
 738                 wm8994->hubs.class_w = true;
 739
 740         } else {
 741                 dev_dbg(codec->dev, "Class W disabled\n");
 742                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 743                                     WM8994_CP_DYN_PWR, 0);
 744                 wm8994->hubs.class_w = false;
 745         }
 746 }
 747
 748 static int late_enable_ev(struct snd_soc_dapm_widget *w,
 749                           struct snd_kcontrol *kcontrol, int event)
 750 {
 751         struct snd_soc_codec *codec = w->codec;
 752         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 753
 754         switch (event) {
 755         case SND_SOC_DAPM_PRE_PMU:
 756                 if (wm8994->aif1clk_enable) {
 757                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 758                                             WM8994_AIF1CLK_ENA_MASK,
 759                                             WM8994_AIF1CLK_ENA);
 760                         wm8994->aif1clk_enable = 0;
 761                 }
 762                 if (wm8994->aif2clk_enable) {
 763                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 764                                             WM8994_AIF2CLK_ENA_MASK,
 765                                             WM8994_AIF2CLK_ENA);
 766                         wm8994->aif2clk_enable = 0;
 767                 }
 768                 break;
 769         }
 770
 771         /* We may also have postponed startup of DSP, handle that. */
 772         wm8958_aif_ev(w, kcontrol, event);
 773
 774         return 0;
 775 }
 776
 777 static int late_disable_ev(struct snd_soc_dapm_widget *w,
 778                            struct snd_kcontrol *kcontrol, int event)
 779 {
 780         struct snd_soc_codec *codec = w->codec;
 781         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 782
 783         switch (event) {
 784         case SND_SOC_DAPM_POST_PMD:
 785                 if (wm8994->aif1clk_disable) {
 786                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 787                                             WM8994_AIF1CLK_ENA_MASK, 0);
 788                         wm8994->aif1clk_disable = 0;
 789                 }
 790                 if (wm8994->aif2clk_disable) {
 791                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 792                                             WM8994_AIF2CLK_ENA_MASK, 0);
 793                         wm8994->aif2clk_disable = 0;
 794                 }
 795                 break;
 796         }
 797
 798         return 0;
 799 }
 800
 801 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
 802                       struct snd_kcontrol *kcontrol, int event)
 803 {
 804         struct snd_soc_codec *codec = w->codec;
 805         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 806
 807         switch (event) {
 808         case SND_SOC_DAPM_PRE_PMU:
 809                 wm8994->aif1clk_enable = 1;
 810                 break;
 811         case SND_SOC_DAPM_POST_PMD:
 812                 wm8994->aif1clk_disable = 1;
 813                 break;
 814         }
 815
 816         return 0;
 817 }
 818
 819 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
 820                       struct snd_kcontrol *kcontrol, int event)
 821 {
 822         struct snd_soc_codec *codec = w->codec;
 823         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 824
 825         switch (event) {
 826         case SND_SOC_DAPM_PRE_PMU:
 827                 wm8994->aif2clk_enable = 1;
 828                 break;
 829         case SND_SOC_DAPM_POST_PMD:
 830                 wm8994->aif2clk_disable = 1;
 831                 break;
 832         }
 833
 834         return 0;
 835 }
 836
 837 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
 838                       struct snd_kcontrol *kcontrol, int event)
 839 {
 840         late_enable_ev(w, kcontrol, event);
 841         return 0;
 842 }
 843
 844 static int micbias_ev(struct snd_soc_dapm_widget *w,
 845                       struct snd_kcontrol *kcontrol, int event)
 846 {
 847         late_enable_ev(w, kcontrol, event);
 848         return 0;
 849 }
 850
 851 static int dac_ev(struct snd_soc_dapm_widget *w,
 852                   struct snd_kcontrol *kcontrol, int event)
 853 {
 854         struct snd_soc_codec *codec = w->codec;
 855         unsigned int mask = 1 << w->shift;
 856
 857         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
 858                             mask, mask);
 859         return 0;
 860 }
 861
 862 static const char *hp_mux_text[] = {
 863         "Mixer",
 864         "DAC",
 865 };
 866
 867 #define WM8994_HP_ENUM(xname, xenum) \
 868 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 869         .info = snd_soc_info_enum_double, \
 870         .get = snd_soc_dapm_get_enum_double, \
 871         .put = wm8994_put_hp_enum, \
 872         .private_value = (unsigned long)&xenum }
 873
 874 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
 875                               struct snd_ctl_elem_value *ucontrol)
 876 {
 877         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
 878         struct snd_soc_dapm_widget *w = wlist->widgets[0];
 879         struct snd_soc_codec *codec = w->codec;
 880         int ret;
 881
 882         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
 883
 884         wm8994_update_class_w(codec);
 885
 886         return ret;
 887 }
 888
 889 static const struct soc_enum hpl_enum =
 890         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
 891
 892 static const struct snd_kcontrol_new hpl_mux =
 893         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
 894
 895 static const struct soc_enum hpr_enum =
 896         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
 897
 898 static const struct snd_kcontrol_new hpr_mux =
 899         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
 900
 901 static const char *adc_mux_text[] = {
 902         "ADC",
 903         "DMIC",
 904 };
 905
 906 static const struct soc_enum adc_enum =
 907         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
 908
 909 static const struct snd_kcontrol_new adcl_mux =
 910         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
 911
 912 static const struct snd_kcontrol_new adcr_mux =
 913         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
 914
 915 static const struct snd_kcontrol_new left_speaker_mixer[] = {
 916 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
 917 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
 918 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
 919 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
 920 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
 921 };
 922
 923 static const struct snd_kcontrol_new right_speaker_mixer[] = {
 924 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
 925 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
 926 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
 927 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
 928 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
 929 };
 930
 931 /* Debugging; dump chip status after DAPM transitions */
 932 static int post_ev(struct snd_soc_dapm_widget *w,
 933             struct snd_kcontrol *kcontrol, int event)
 934 {
 935         struct snd_soc_codec *codec = w->codec;
 936         dev_dbg(codec->dev, "SRC status: %x\n",
 937                 snd_soc_read(codec,
 938                              WM8994_RATE_STATUS));
 939         return 0;
 940 }
 941
 942 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
 943 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
 944                 1, 1, 0),
 945 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
 946                 0, 1, 0),
 947 };
 948
 949 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
 950 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
 951                 1, 1, 0),
 952 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
 953                 0, 1, 0),
 954 };
 955
 956 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
 957 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
 958                 1, 1, 0),
 959 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
 960                 0, 1, 0),
 961 };
 962
 963 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
 964 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
 965                 1, 1, 0),
 966 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
 967                 0, 1, 0),
 968 };
 969
 970 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
 971 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 972                 5, 1, 0),
 973 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 974                 4, 1, 0),
 975 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 976                 2, 1, 0),
 977 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 978                 1, 1, 0),
 979 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 980                 0, 1, 0),
 981 };
 982
 983 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
 984 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 985                 5, 1, 0),
 986 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 987                 4, 1, 0),
 988 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 989                 2, 1, 0),
 990 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 991                 1, 1, 0),
 992 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 993                 0, 1, 0),
 994 };
 995
 996 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
 997 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 998         .info = snd_soc_info_volsw, \
 999         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1000         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1001
1002 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1003                               struct snd_ctl_elem_value *ucontrol)
1004 {
1005         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1006         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1007         struct snd_soc_codec *codec = w->codec;
1008         int ret;
1009
1010         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1011
1012         wm8994_update_class_w(codec);
1013
1014         return ret;
1015 }
1016
1017 static const struct snd_kcontrol_new dac1l_mix[] = {
1018 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1019                       5, 1, 0),
1020 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1021                       4, 1, 0),
1022 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1023                       2, 1, 0),
1024 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1025                       1, 1, 0),
1026 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1027                       0, 1, 0),
1028 };
1029
1030 static const struct snd_kcontrol_new dac1r_mix[] = {
1031 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1032                       5, 1, 0),
1033 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1034                       4, 1, 0),
1035 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1036                       2, 1, 0),
1037 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1038                       1, 1, 0),
1039 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1040                       0, 1, 0),
1041 };
1042
1043 static const char *sidetone_text[] = {
1044         "ADC/DMIC1", "DMIC2",
1045 };
1046
1047 static const struct soc_enum sidetone1_enum =
1048         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1049
1050 static const struct snd_kcontrol_new sidetone1_mux =
1051         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1052
1053 static const struct soc_enum sidetone2_enum =
1054         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1055
1056 static const struct snd_kcontrol_new sidetone2_mux =
1057         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1058
1059 static const char *aif1dac_text[] = {
1060         "AIF1DACDAT", "AIF3DACDAT",
1061 };
1062
1063 static const struct soc_enum aif1dac_enum =
1064         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1065
1066 static const struct snd_kcontrol_new aif1dac_mux =
1067         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1068
1069 static const char *aif2dac_text[] = {
1070         "AIF2DACDAT", "AIF3DACDAT",
1071 };
1072
1073 static const struct soc_enum aif2dac_enum =
1074         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1075
1076 static const struct snd_kcontrol_new aif2dac_mux =
1077         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1078
1079 static const char *aif2adc_text[] = {
1080         "AIF2ADCDAT", "AIF3DACDAT",
1081 };
1082
1083 static const struct soc_enum aif2adc_enum =
1084         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1085
1086 static const struct snd_kcontrol_new aif2adc_mux =
1087         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1088
1089 static const char *aif3adc_text[] = {
1090         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1091 };
1092
1093 static const struct soc_enum wm8994_aif3adc_enum =
1094         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1095
1096 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1097         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1098
1099 static const struct soc_enum wm8958_aif3adc_enum =
1100         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1101
1102 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1103         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1104
1105 static const char *mono_pcm_out_text[] = {
1106         "None", "AIF2ADCL", "AIF2ADCR",
1107 };
1108
1109 static const struct soc_enum mono_pcm_out_enum =
1110         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1111
1112 static const struct snd_kcontrol_new mono_pcm_out_mux =
1113         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1114
1115 static const char *aif2dac_src_text[] = {
1116         "AIF2", "AIF3",
1117 };
1118
1119 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1120 static const struct soc_enum aif2dacl_src_enum =
1121         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1122
1123 static const struct snd_kcontrol_new aif2dacl_src_mux =
1124         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1125
1126 static const struct soc_enum aif2dacr_src_enum =
1127         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1128
1129 static const struct snd_kcontrol_new aif2dacr_src_mux =
1130         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1131
1132 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1133 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1134         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1135 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1136         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1137
1138 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1139         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1140 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1141         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1142 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1143         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1144 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1145         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1146 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1147         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1148
1149 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1150                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1151                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1152 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1153                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1154                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1155 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1156                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1157 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1158                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1159
1160 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1161 };
1162
1163 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1164 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1165 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1166 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1167 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1168                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1169 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1170                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1171 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1172 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1173 };
1174
1175 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1176 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1177         dac_ev, SND_SOC_DAPM_PRE_PMU),
1178 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1179         dac_ev, SND_SOC_DAPM_PRE_PMU),
1180 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1181         dac_ev, SND_SOC_DAPM_PRE_PMU),
1182 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1183         dac_ev, SND_SOC_DAPM_PRE_PMU),
1184 };
1185
1186 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1187 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1188 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1189 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1190 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1191 };
1192
1193 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1194 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1195                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1196 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1197                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1198 };
1199
1200 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1201 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1202 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1203 };
1204
1205 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1206 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1207 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1208 SND_SOC_DAPM_INPUT("Clock"),
1209
1210 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1211                       SND_SOC_DAPM_PRE_PMU),
1212
1213 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1214                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1215
1216 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1217 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1218 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1219
1220 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1221                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1222 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1223                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1224 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1225                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1226                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1227 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1228                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1229                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1230
1231 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1232                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1233 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1234                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1235 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1236                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1237                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1238 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1239                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1240                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1241
1242 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1243                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1244 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1245                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1246
1247 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1248                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1249 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1250                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1251
1252 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1253                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1254 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1255                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1256
1257 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1258 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1259
1260 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1261                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1262 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1263                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1264
1265 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1266                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1267 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1268                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1269 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1270                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1271                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1272 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1273                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1274                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1275
1276 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1277 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1278 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1279 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1280
1281 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1282 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1283 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1284
1285 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1286 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1287
1288 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1289
1290 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1291 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1292 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1293 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1294
1295 /* Power is done with the muxes since the ADC power also controls the
1296  * downsampling chain, the chip will automatically manage the analogue
1297  * specific portions.
1298  */
1299 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1300 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1301
1302 SND_SOC_DAPM_POST("Debug log", post_ev),
1303 };
1304
1305 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1306 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1307 };
1308
1309 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1310 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1311 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1312 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1313 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1314 };
1315
1316 static const struct snd_soc_dapm_route intercon[] = {
1317         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1318         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1319
1320         { "DSP1CLK", NULL, "CLK_SYS" },
1321         { "DSP2CLK", NULL, "CLK_SYS" },
1322         { "DSPINTCLK", NULL, "CLK_SYS" },
1323
1324         { "AIF1ADC1L", NULL, "AIF1CLK" },
1325         { "AIF1ADC1L", NULL, "DSP1CLK" },
1326         { "AIF1ADC1R", NULL, "AIF1CLK" },
1327         { "AIF1ADC1R", NULL, "DSP1CLK" },
1328         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1329
1330         { "AIF1DAC1L", NULL, "AIF1CLK" },
1331         { "AIF1DAC1L", NULL, "DSP1CLK" },
1332         { "AIF1DAC1R", NULL, "AIF1CLK" },
1333         { "AIF1DAC1R", NULL, "DSP1CLK" },
1334         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1335
1336         { "AIF1ADC2L", NULL, "AIF1CLK" },
1337         { "AIF1ADC2L", NULL, "DSP1CLK" },
1338         { "AIF1ADC2R", NULL, "AIF1CLK" },
1339         { "AIF1ADC2R", NULL, "DSP1CLK" },
1340         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1341
1342         { "AIF1DAC2L", NULL, "AIF1CLK" },
1343         { "AIF1DAC2L", NULL, "DSP1CLK" },
1344         { "AIF1DAC2R", NULL, "AIF1CLK" },
1345         { "AIF1DAC2R", NULL, "DSP1CLK" },
1346         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1347
1348         { "AIF2ADCL", NULL, "AIF2CLK" },
1349         { "AIF2ADCL", NULL, "DSP2CLK" },
1350         { "AIF2ADCR", NULL, "AIF2CLK" },
1351         { "AIF2ADCR", NULL, "DSP2CLK" },
1352         { "AIF2ADCR", NULL, "DSPINTCLK" },
1353
1354         { "AIF2DACL", NULL, "AIF2CLK" },
1355         { "AIF2DACL", NULL, "DSP2CLK" },
1356         { "AIF2DACR", NULL, "AIF2CLK" },
1357         { "AIF2DACR", NULL, "DSP2CLK" },
1358         { "AIF2DACR", NULL, "DSPINTCLK" },
1359
1360         { "DMIC1L", NULL, "DMIC1DAT" },
1361         { "DMIC1L", NULL, "CLK_SYS" },
1362         { "DMIC1R", NULL, "DMIC1DAT" },
1363         { "DMIC1R", NULL, "CLK_SYS" },
1364         { "DMIC2L", NULL, "DMIC2DAT" },
1365         { "DMIC2L", NULL, "CLK_SYS" },
1366         { "DMIC2R", NULL, "DMIC2DAT" },
1367         { "DMIC2R", NULL, "CLK_SYS" },
1368
1369         { "ADCL", NULL, "AIF1CLK" },
1370         { "ADCL", NULL, "DSP1CLK" },
1371         { "ADCL", NULL, "DSPINTCLK" },
1372
1373         { "ADCR", NULL, "AIF1CLK" },
1374         { "ADCR", NULL, "DSP1CLK" },
1375         { "ADCR", NULL, "DSPINTCLK" },
1376
1377         { "ADCL Mux", "ADC", "ADCL" },
1378         { "ADCL Mux", "DMIC", "DMIC1L" },
1379         { "ADCR Mux", "ADC", "ADCR" },
1380         { "ADCR Mux", "DMIC", "DMIC1R" },
1381
1382         { "DAC1L", NULL, "AIF1CLK" },
1383         { "DAC1L", NULL, "DSP1CLK" },
1384         { "DAC1L", NULL, "DSPINTCLK" },
1385
1386         { "DAC1R", NULL, "AIF1CLK" },
1387         { "DAC1R", NULL, "DSP1CLK" },
1388         { "DAC1R", NULL, "DSPINTCLK" },
1389
1390         { "DAC2L", NULL, "AIF2CLK" },
1391         { "DAC2L", NULL, "DSP2CLK" },
1392         { "DAC2L", NULL, "DSPINTCLK" },
1393
1394         { "DAC2R", NULL, "AIF2DACR" },
1395         { "DAC2R", NULL, "AIF2CLK" },
1396         { "DAC2R", NULL, "DSP2CLK" },
1397         { "DAC2R", NULL, "DSPINTCLK" },
1398
1399         { "TOCLK", NULL, "CLK_SYS" },
1400
1401         /* AIF1 outputs */
1402         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1403         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1404         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1405
1406         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1407         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1408         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1409
1410         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1411         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1412         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1413
1414         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1415         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1416         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1417
1418         /* Pin level routing for AIF3 */
1419         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1420         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1421         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1422         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1423
1424         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1425         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1426         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1427         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1428         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1429         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1430         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1431
1432         /* DAC1 inputs */
1433         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1434         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1435         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1436         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1437         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1438
1439         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1440         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1441         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1442         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1443         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1444
1445         /* DAC2/AIF2 outputs  */
1446         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1447         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1448         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1449         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1450         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1451         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1452
1453         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1454         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1455         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1456         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1457         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1458         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1459
1460         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1461         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1462         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1463         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1464
1465         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1466
1467         /* AIF3 output */
1468         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1469         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1470         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1471         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1472         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1473         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1474         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1475         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1476
1477         /* Sidetone */
1478         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1479         { "Left Sidetone", "DMIC2", "DMIC2L" },
1480         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1481         { "Right Sidetone", "DMIC2", "DMIC2R" },
1482
1483         /* Output stages */
1484         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1485         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1486
1487         { "SPKL", "DAC1 Switch", "DAC1L" },
1488         { "SPKL", "DAC2 Switch", "DAC2L" },
1489
1490         { "SPKR", "DAC1 Switch", "DAC1R" },
1491         { "SPKR", "DAC2 Switch", "DAC2R" },
1492
1493         { "Left Headphone Mux", "DAC", "DAC1L" },
1494         { "Right Headphone Mux", "DAC", "DAC1R" },
1495 };
1496
1497 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1498         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1499         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1500         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1501         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1502         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1503         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1504         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1505         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1506 };
1507
1508 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1509         { "DAC1L", NULL, "DAC1L Mixer" },
1510         { "DAC1R", NULL, "DAC1R Mixer" },
1511         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1512         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1513 };
1514
1515 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1516         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1517         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1518         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1519         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1520         { "MICBIAS1", NULL, "CLK_SYS" },
1521         { "MICBIAS1", NULL, "MICBIAS Supply" },
1522         { "MICBIAS2", NULL, "CLK_SYS" },
1523         { "MICBIAS2", NULL, "MICBIAS Supply" },
1524 };
1525
1526 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1527         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1528         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1529 };
1530
1531 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1532         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1533         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1534
1535         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1536         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1537         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1538         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1539
1540         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1541         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1542
1543         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1544 };
1545
1546 /* The size in bits of the FLL divide multiplied by 10
1547  * to allow rounding later */
1548 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1549
1550 struct fll_div {
1551         u16 outdiv;
1552         u16 n;
1553         u16 k;
1554         u16 clk_ref_div;
1555         u16 fll_fratio;
1556 };
1557
1558 static int wm8994_get_fll_config(struct fll_div *fll,
1559                                  int freq_in, int freq_out)
1560 {
1561         u64 Kpart;
1562         unsigned int K, Ndiv, Nmod;
1563
1564         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1565
1566         /* Scale the input frequency down to <= 13.5MHz */
1567         fll->clk_ref_div = 0;
1568         while (freq_in > 13500000) {
1569                 fll->clk_ref_div++;
1570                 freq_in /= 2;
1571
1572                 if (fll->clk_ref_div > 3)
1573                         return -EINVAL;
1574         }
1575         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1576
1577         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1578         fll->outdiv = 3;
1579         while (freq_out * (fll->outdiv + 1) < 90000000) {
1580                 fll->outdiv++;
1581                 if (fll->outdiv > 63)
1582                         return -EINVAL;
1583         }
1584         freq_out *= fll->outdiv + 1;
1585         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1586
1587         if (freq_in > 1000000) {
1588                 fll->fll_fratio = 0;
1589         } else if (freq_in > 256000) {
1590                 fll->fll_fratio = 1;
1591                 freq_in *= 2;
1592         } else if (freq_in > 128000) {
1593                 fll->fll_fratio = 2;
1594                 freq_in *= 4;
1595         } else if (freq_in > 64000) {
1596                 fll->fll_fratio = 3;
1597                 freq_in *= 8;
1598         } else {
1599                 fll->fll_fratio = 4;
1600                 freq_in *= 16;
1601         }
1602         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1603
1604         /* Now, calculate N.K */
1605         Ndiv = freq_out / freq_in;
1606
1607         fll->n = Ndiv;
1608         Nmod = freq_out % freq_in;
1609         pr_debug("Nmod=%d\n", Nmod);
1610
1611         /* Calculate fractional part - scale up so we can round. */
1612         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1613
1614         do_div(Kpart, freq_in);
1615
1616         K = Kpart & 0xFFFFFFFF;
1617
1618         if ((K % 10) >= 5)
1619                 K += 5;
1620
1621         /* Move down to proper range now rounding is done */
1622         fll->k = K / 10;
1623
1624         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1625
1626         return 0;
1627 }
1628
1629 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1630                           unsigned int freq_in, unsigned int freq_out)
1631 {
1632         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1633         int reg_offset, ret;
1634         struct fll_div fll;
1635         u16 reg, aif1, aif2;
1636         unsigned long timeout;
1637
1638         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1639                 & WM8994_AIF1CLK_ENA;
1640
1641         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1642                 & WM8994_AIF2CLK_ENA;
1643
1644         switch (id) {
1645         case WM8994_FLL1:
1646                 reg_offset = 0;
1647                 id = 0;
1648                 break;
1649         case WM8994_FLL2:
1650                 reg_offset = 0x20;
1651                 id = 1;
1652                 break;
1653         default:
1654                 return -EINVAL;
1655         }
1656
1657         switch (src) {
1658         case 0:
1659                 /* Allow no source specification when stopping */
1660                 if (freq_out)
1661                         return -EINVAL;
1662                 src = wm8994->fll[id].src;
1663                 break;
1664         case WM8994_FLL_SRC_MCLK1:
1665         case WM8994_FLL_SRC_MCLK2:
1666         case WM8994_FLL_SRC_LRCLK:
1667         case WM8994_FLL_SRC_BCLK:
1668                 break;
1669         default:
1670                 return -EINVAL;
1671         }
1672
1673         /* Are we changing anything? */
1674         if (wm8994->fll[id].src == src &&
1675             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1676                 return 0;
1677
1678         /* If we're stopping the FLL redo the old config - no
1679          * registers will actually be written but we avoid GCC flow
1680          * analysis bugs spewing warnings.
1681          */
1682         if (freq_out)
1683                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1684         else
1685                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1686                                             wm8994->fll[id].out);
1687         if (ret < 0)
1688                 return ret;
1689
1690         /* Gate the AIF clocks while we reclock */
1691         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1692                             WM8994_AIF1CLK_ENA, 0);
1693         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1694                             WM8994_AIF2CLK_ENA, 0);
1695
1696         /* We always need to disable the FLL while reconfiguring */
1697         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1698                             WM8994_FLL1_ENA, 0);
1699
1700         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1701                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1702         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1703                             WM8994_FLL1_OUTDIV_MASK |
1704                             WM8994_FLL1_FRATIO_MASK, reg);
1705
1706         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1707
1708         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1709                             WM8994_FLL1_N_MASK,
1710                                     fll.n << WM8994_FLL1_N_SHIFT);
1711
1712         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1713                             WM8994_FLL1_REFCLK_DIV_MASK |
1714                             WM8994_FLL1_REFCLK_SRC_MASK,
1715                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1716                             (src - 1));
1717
1718         /* Clear any pending completion from a previous failure */
1719         try_wait_for_completion(&wm8994->fll_locked[id]);
1720
1721         /* Enable (with fractional mode if required) */
1722         if (freq_out) {
1723                 if (fll.k)
1724                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1725                 else
1726                         reg = WM8994_FLL1_ENA;
1727                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1728                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1729                                     reg);
1730
1731                 if (wm8994->fll_locked_irq) {
1732                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1733                                                               msecs_to_jiffies(10));
1734                         if (timeout == 0)
1735                                 dev_warn(codec->dev,
1736                                          "Timed out waiting for FLL lock\n");
1737                 } else {
1738                         msleep(5);
1739                 }
1740         }
1741
1742         wm8994->fll[id].in = freq_in;
1743         wm8994->fll[id].out = freq_out;
1744         wm8994->fll[id].src = src;
1745
1746         /* Enable any gated AIF clocks */
1747         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1748                             WM8994_AIF1CLK_ENA, aif1);
1749         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1750                             WM8994_AIF2CLK_ENA, aif2);
1751
1752         configure_clock(codec);
1753
1754         return 0;
1755 }
1756
1757 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1758 {
1759         struct completion *completion = data;
1760
1761         complete(completion);
1762
1763         return IRQ_HANDLED;
1764 }
1765
1766 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1767
1768 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1769                           unsigned int freq_in, unsigned int freq_out)
1770 {
1771         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1772 }
1773
1774 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1775                 int clk_id, unsigned int freq, int dir)
1776 {
1777         struct snd_soc_codec *codec = dai->codec;
1778         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1779         int i;
1780
1781         switch (dai->id) {
1782         case 1:
1783         case 2:
1784                 break;
1785
1786         default:
1787                 /* AIF3 shares clocking with AIF1/2 */
1788                 return -EINVAL;
1789         }
1790
1791         switch (clk_id) {
1792         case WM8994_SYSCLK_MCLK1:
1793                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1794                 wm8994->mclk[0] = freq;
1795                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1796                         dai->id, freq);
1797                 break;
1798
1799         case WM8994_SYSCLK_MCLK2:
1800                 /* TODO: Set GPIO AF */
1801                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1802                 wm8994->mclk[1] = freq;
1803                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1804                         dai->id, freq);
1805                 break;
1806
1807         case WM8994_SYSCLK_FLL1:
1808                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1809                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1810                 break;
1811
1812         case WM8994_SYSCLK_FLL2:
1813                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1814                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1815                 break;
1816
1817         case WM8994_SYSCLK_OPCLK:
1818                 /* Special case - a division (times 10) is given and
1819                  * no effect on main clocking.
1820                  */
1821                 if (freq) {
1822                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1823                                 if (opclk_divs[i] == freq)
1824                                         break;
1825                         if (i == ARRAY_SIZE(opclk_divs))
1826                                 return -EINVAL;
1827                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1828                                             WM8994_OPCLK_DIV_MASK, i);
1829                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1830                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1831                 } else {
1832                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1833                                             WM8994_OPCLK_ENA, 0);
1834                 }
1835
1836         default:
1837                 return -EINVAL;
1838         }
1839
1840         configure_clock(codec);
1841
1842         return 0;
1843 }
1844
1845 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1846                                  enum snd_soc_bias_level level)
1847 {
1848         struct wm8994 *control = codec->control_data;
1849         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1850
1851         switch (level) {
1852         case SND_SOC_BIAS_ON:
1853                 break;
1854
1855         case SND_SOC_BIAS_PREPARE:
1856                 /* VMID=2x40k */
1857                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1858                                     WM8994_VMID_SEL_MASK, 0x2);
1859                 break;
1860
1861         case SND_SOC_BIAS_STANDBY:
1862                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1863                         pm_runtime_get_sync(codec->dev);
1864
1865                         switch (control->type) {
1866                         case WM8994:
1867                                 if (wm8994->revision < 4) {
1868                                         /* Tweak DC servo and DSP
1869                                          * configuration for improved
1870                                          * performance. */
1871                                         snd_soc_write(codec, 0x102, 0x3);
1872                                         snd_soc_write(codec, 0x56, 0x3);
1873                                         snd_soc_write(codec, 0x817, 0);
1874                                         snd_soc_write(codec, 0x102, 0);
1875                                 }
1876                                 break;
1877
1878                         case WM8958:
1879                                 if (wm8994->revision == 0) {
1880                                         /* Optimise performance for rev A */
1881                                         snd_soc_write(codec, 0x102, 0x3);
1882                                         snd_soc_write(codec, 0xcb, 0x81);
1883                                         snd_soc_write(codec, 0x817, 0);
1884                                         snd_soc_write(codec, 0x102, 0);
1885
1886                                         snd_soc_update_bits(codec,
1887                                                             WM8958_CHARGE_PUMP_2,
1888                                                             WM8958_CP_DISCH,
1889                                                             WM8958_CP_DISCH);
1890                                 }
1891                                 break;
1892                         }
1893
1894                         /* Discharge LINEOUT1 & 2 */
1895                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1896                                             WM8994_LINEOUT1_DISCH |
1897                                             WM8994_LINEOUT2_DISCH,
1898                                             WM8994_LINEOUT1_DISCH |
1899                                             WM8994_LINEOUT2_DISCH);
1900
1901                         /* Startup bias, VMID ramp & buffer */
1902                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1903                                             WM8994_STARTUP_BIAS_ENA |
1904                                             WM8994_VMID_BUF_ENA |
1905                                             WM8994_VMID_RAMP_MASK,
1906                                             WM8994_STARTUP_BIAS_ENA |
1907                                             WM8994_VMID_BUF_ENA |
1908                                             (0x11 << WM8994_VMID_RAMP_SHIFT));
1909
1910                         /* Main bias enable, VMID=2x40k */
1911                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1912                                             WM8994_BIAS_ENA |
1913                                             WM8994_VMID_SEL_MASK,
1914                                             WM8994_BIAS_ENA | 0x2);
1915
1916                         msleep(20);
1917                 }
1918
1919                 /* VMID=2x500k */
1920                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1921                                     WM8994_VMID_SEL_MASK, 0x4);
1922
1923                 break;
1924
1925         case SND_SOC_BIAS_OFF:
1926                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1927                         /* Switch over to startup biases */
1928                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1929                                             WM8994_BIAS_SRC |
1930                                             WM8994_STARTUP_BIAS_ENA |
1931                                             WM8994_VMID_BUF_ENA |
1932                                             WM8994_VMID_RAMP_MASK,
1933                                             WM8994_BIAS_SRC |
1934                                             WM8994_STARTUP_BIAS_ENA |
1935                                             WM8994_VMID_BUF_ENA |
1936                                             (1 << WM8994_VMID_RAMP_SHIFT));
1937
1938                         /* Disable main biases */
1939                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1940                                             WM8994_BIAS_ENA |
1941                                             WM8994_VMID_SEL_MASK, 0);
1942
1943                         /* Discharge line */
1944                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1945                                             WM8994_LINEOUT1_DISCH |
1946                                             WM8994_LINEOUT2_DISCH,
1947                                             WM8994_LINEOUT1_DISCH |
1948                                             WM8994_LINEOUT2_DISCH);
1949
1950                         msleep(5);
1951
1952                         /* Switch off startup biases */
1953                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1954                                             WM8994_BIAS_SRC |
1955                                             WM8994_STARTUP_BIAS_ENA |
1956                                             WM8994_VMID_BUF_ENA |
1957                                             WM8994_VMID_RAMP_MASK, 0);
1958
1959                         wm8994->cur_fw = NULL;
1960
1961                         pm_runtime_put(codec->dev);
1962                 }
1963                 break;
1964         }
1965         codec->dapm.bias_level = level;
1966         return 0;
1967 }
1968
1969 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1970 {
1971         struct snd_soc_codec *codec = dai->codec;
1972         struct wm8994 *control = codec->control_data;
1973         int ms_reg;
1974         int aif1_reg;
1975         int ms = 0;
1976         int aif1 = 0;
1977
1978         switch (dai->id) {
1979         case 1:
1980                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1981                 aif1_reg = WM8994_AIF1_CONTROL_1;
1982                 break;
1983         case 2:
1984                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1985                 aif1_reg = WM8994_AIF2_CONTROL_1;
1986                 break;
1987         default:
1988                 return -EINVAL;
1989         }
1990
1991         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1992         case SND_SOC_DAIFMT_CBS_CFS:
1993                 break;
1994         case SND_SOC_DAIFMT_CBM_CFM:
1995                 ms = WM8994_AIF1_MSTR;
1996                 break;
1997         default:
1998                 return -EINVAL;
1999         }
2000
2001         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2002         case SND_SOC_DAIFMT_DSP_B:
2003                 aif1 |= WM8994_AIF1_LRCLK_INV;
2004         case SND_SOC_DAIFMT_DSP_A:
2005                 aif1 |= 0x18;
2006                 break;
2007         case SND_SOC_DAIFMT_I2S:
2008                 aif1 |= 0x10;
2009                 break;
2010         case SND_SOC_DAIFMT_RIGHT_J:
2011                 break;
2012         case SND_SOC_DAIFMT_LEFT_J:
2013                 aif1 |= 0x8;
2014                 break;
2015         default:
2016                 return -EINVAL;
2017         }
2018
2019         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2020         case SND_SOC_DAIFMT_DSP_A:
2021         case SND_SOC_DAIFMT_DSP_B:
2022                 /* frame inversion not valid for DSP modes */
2023                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2024                 case SND_SOC_DAIFMT_NB_NF:
2025                         break;
2026                 case SND_SOC_DAIFMT_IB_NF:
2027                         aif1 |= WM8994_AIF1_BCLK_INV;
2028                         break;
2029                 default:
2030                         return -EINVAL;
2031                 }
2032                 break;
2033
2034         case SND_SOC_DAIFMT_I2S:
2035         case SND_SOC_DAIFMT_RIGHT_J:
2036         case SND_SOC_DAIFMT_LEFT_J:
2037                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2038                 case SND_SOC_DAIFMT_NB_NF:
2039                         break;
2040                 case SND_SOC_DAIFMT_IB_IF:
2041                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2042                         break;
2043                 case SND_SOC_DAIFMT_IB_NF:
2044                         aif1 |= WM8994_AIF1_BCLK_INV;
2045                         break;
2046                 case SND_SOC_DAIFMT_NB_IF:
2047                         aif1 |= WM8994_AIF1_LRCLK_INV;
2048                         break;
2049                 default:
2050                         return -EINVAL;
2051                 }
2052                 break;
2053         default:
2054                 return -EINVAL;
2055         }
2056
2057         /* The AIF2 format configuration needs to be mirrored to AIF3
2058          * on WM8958 if it's in use so just do it all the time. */
2059         if (control->type == WM8958 && dai->id == 2)
2060                 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2061                                     WM8994_AIF1_LRCLK_INV |
2062                                     WM8958_AIF3_FMT_MASK, aif1);
2063
2064         snd_soc_update_bits(codec, aif1_reg,
2065                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2066                             WM8994_AIF1_FMT_MASK,
2067                             aif1);
2068         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2069                             ms);
2070
2071         return 0;
2072 }
2073
2074 static struct {
2075         int val, rate;
2076 } srs[] = {
2077         { 0,   8000 },
2078         { 1,  11025 },
2079         { 2,  12000 },
2080         { 3,  16000 },
2081         { 4,  22050 },
2082         { 5,  24000 },
2083         { 6,  32000 },
2084         { 7,  44100 },
2085         { 8,  48000 },
2086         { 9,  88200 },
2087         { 10, 96000 },
2088 };
2089
2090 static int fs_ratios[] = {
2091         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2092 };
2093
2094 static int bclk_divs[] = {
2095         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2096         640, 880, 960, 1280, 1760, 1920
2097 };
2098
2099 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2100                             struct snd_pcm_hw_params *params,
2101                             struct snd_soc_dai *dai)
2102 {
2103         struct snd_soc_codec *codec = dai->codec;
2104         struct wm8994 *control = codec->control_data;
2105         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2106         int aif1_reg;
2107         int aif2_reg;
2108         int bclk_reg;
2109         int lrclk_reg;
2110         int rate_reg;
2111         int aif1 = 0;
2112         int aif2 = 0;
2113         int bclk = 0;
2114         int lrclk = 0;
2115         int rate_val = 0;
2116         int id = dai->id - 1;
2117
2118         int i, cur_val, best_val, bclk_rate, best;
2119
2120         switch (dai->id) {
2121         case 1:
2122                 aif1_reg = WM8994_AIF1_CONTROL_1;
2123                 aif2_reg = WM8994_AIF1_CONTROL_2;
2124                 bclk_reg = WM8994_AIF1_BCLK;
2125                 rate_reg = WM8994_AIF1_RATE;
2126                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2127                     wm8994->lrclk_shared[0]) {
2128                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2129                 } else {
2130                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2131                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2132                 }
2133                 break;
2134         case 2:
2135                 aif1_reg = WM8994_AIF2_CONTROL_1;
2136                 aif2_reg = WM8994_AIF2_CONTROL_2;
2137                 bclk_reg = WM8994_AIF2_BCLK;
2138                 rate_reg = WM8994_AIF2_RATE;
2139                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2140                     wm8994->lrclk_shared[1]) {
2141                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2142                 } else {
2143                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2144                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2145                 }
2146                 break;
2147         case 3:
2148                 switch (control->type) {
2149                 case WM8958:
2150                         aif1_reg = WM8958_AIF3_CONTROL_1;
2151                         break;
2152                 default:
2153                         return 0;
2154                 }
2155         default:
2156                 return -EINVAL;
2157         }
2158
2159         bclk_rate = params_rate(params) * 2;
2160         switch (params_format(params)) {
2161         case SNDRV_PCM_FORMAT_S16_LE:
2162                 bclk_rate *= 16;
2163                 break;
2164         case SNDRV_PCM_FORMAT_S20_3LE:
2165                 bclk_rate *= 20;
2166                 aif1 |= 0x20;
2167                 break;
2168         case SNDRV_PCM_FORMAT_S24_LE:
2169                 bclk_rate *= 24;
2170                 aif1 |= 0x40;
2171                 break;
2172         case SNDRV_PCM_FORMAT_S32_LE:
2173                 bclk_rate *= 32;
2174                 aif1 |= 0x60;
2175                 break;
2176         default:
2177                 return -EINVAL;
2178         }
2179
2180         /* Try to find an appropriate sample rate; look for an exact match. */
2181         for (i = 0; i < ARRAY_SIZE(srs); i++)
2182                 if (srs[i].rate == params_rate(params))
2183                         break;
2184         if (i == ARRAY_SIZE(srs))
2185                 return -EINVAL;
2186         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2187
2188         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2189         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2190                 dai->id, wm8994->aifclk[id], bclk_rate);
2191
2192         if (params_channels(params) == 1 &&
2193             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2194                 aif2 |= WM8994_AIF1_MONO;
2195
2196         if (wm8994->aifclk[id] == 0) {
2197                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2198                 return -EINVAL;
2199         }
2200
2201         /* AIFCLK/fs ratio; look for a close match in either direction */
2202         best = 0;
2203         best_val = abs((fs_ratios[0] * params_rate(params))
2204                        - wm8994->aifclk[id]);
2205         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2206                 cur_val = abs((fs_ratios[i] * params_rate(params))
2207                               - wm8994->aifclk[id]);
2208                 if (cur_val >= best_val)
2209                         continue;
2210                 best = i;
2211                 best_val = cur_val;
2212         }
2213         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2214                 dai->id, fs_ratios[best]);
2215         rate_val |= best;
2216
2217         /* We may not get quite the right frequency if using
2218          * approximate clocks so look for the closest match that is
2219          * higher than the target (we need to ensure that there enough
2220          * BCLKs to clock out the samples).
2221          */
2222         best = 0;
2223         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2224                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2225                 if (cur_val < 0) /* BCLK table is sorted */
2226                         break;
2227                 best = i;
2228         }
2229         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2230         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2231                 bclk_divs[best], bclk_rate);
2232         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2233
2234         lrclk = bclk_rate / params_rate(params);
2235         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2236                 lrclk, bclk_rate / lrclk);
2237
2238         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2239         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2240         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2241         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2242                             lrclk);
2243         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2244                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2245
2246         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2247                 switch (dai->id) {
2248                 case 1:
2249                         wm8994->dac_rates[0] = params_rate(params);
2250                         wm8994_set_retune_mobile(codec, 0);
2251                         wm8994_set_retune_mobile(codec, 1);
2252                         break;
2253                 case 2:
2254                         wm8994->dac_rates[1] = params_rate(params);
2255                         wm8994_set_retune_mobile(codec, 2);
2256                         break;
2257                 }
2258         }
2259
2260         return 0;
2261 }
2262
2263 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2264                                  struct snd_pcm_hw_params *params,
2265                                  struct snd_soc_dai *dai)
2266 {
2267         struct snd_soc_codec *codec = dai->codec;
2268         struct wm8994 *control = codec->control_data;
2269         int aif1_reg;
2270         int aif1 = 0;
2271
2272         switch (dai->id) {
2273         case 3:
2274                 switch (control->type) {
2275                 case WM8958:
2276                         aif1_reg = WM8958_AIF3_CONTROL_1;
2277                         break;
2278                 default:
2279                         return 0;
2280                 }
2281         default:
2282                 return 0;
2283         }
2284
2285         switch (params_format(params)) {
2286         case SNDRV_PCM_FORMAT_S16_LE:
2287                 break;
2288         case SNDRV_PCM_FORMAT_S20_3LE:
2289                 aif1 |= 0x20;
2290                 break;
2291         case SNDRV_PCM_FORMAT_S24_LE:
2292                 aif1 |= 0x40;
2293                 break;
2294         case SNDRV_PCM_FORMAT_S32_LE:
2295                 aif1 |= 0x60;
2296                 break;
2297         default:
2298                 return -EINVAL;
2299         }
2300
2301         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2302 }
2303
2304 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2305                                 struct snd_soc_dai *dai)
2306 {
2307         struct snd_soc_codec *codec = dai->codec;
2308         int rate_reg = 0;
2309
2310         switch (dai->id) {
2311         case 1:
2312                 rate_reg = WM8994_AIF1_RATE;
2313                 break;
2314         case 2:
2315                 rate_reg = WM8994_AIF1_RATE;
2316                 break;
2317         default:
2318                 break;
2319         }
2320
2321         /* If the DAI is idle then configure the divider tree for the
2322          * lowest output rate to save a little power if the clock is
2323          * still active (eg, because it is system clock).
2324          */
2325         if (rate_reg && !dai->playback_active && !dai->capture_active)
2326                 snd_soc_update_bits(codec, rate_reg,
2327                                     WM8994_AIF1_SR_MASK |
2328                                     WM8994_AIF1CLK_RATE_MASK, 0x9);
2329 }
2330
2331 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2332 {
2333         struct snd_soc_codec *codec = codec_dai->codec;
2334         int mute_reg;
2335         int reg;
2336
2337         switch (codec_dai->id) {
2338         case 1:
2339                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2340                 break;
2341         case 2:
2342                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2343                 break;
2344         default:
2345                 return -EINVAL;
2346         }
2347
2348         if (mute)
2349                 reg = WM8994_AIF1DAC1_MUTE;
2350         else
2351                 reg = 0;
2352
2353         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2354
2355         return 0;
2356 }
2357
2358 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2359 {
2360         struct snd_soc_codec *codec = codec_dai->codec;
2361         int reg, val, mask;
2362
2363         switch (codec_dai->id) {
2364         case 1:
2365                 reg = WM8994_AIF1_MASTER_SLAVE;
2366                 mask = WM8994_AIF1_TRI;
2367                 break;
2368         case 2:
2369                 reg = WM8994_AIF2_MASTER_SLAVE;
2370                 mask = WM8994_AIF2_TRI;
2371                 break;
2372         case 3:
2373                 reg = WM8994_POWER_MANAGEMENT_6;
2374                 mask = WM8994_AIF3_TRI;
2375                 break;
2376         default:
2377                 return -EINVAL;
2378         }
2379
2380         if (tristate)
2381                 val = mask;
2382         else
2383                 val = 0;
2384
2385         return snd_soc_update_bits(codec, reg, mask, val);
2386 }
2387
2388 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2389
2390 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2391                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2392
2393 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2394         .set_sysclk     = wm8994_set_dai_sysclk,
2395         .set_fmt        = wm8994_set_dai_fmt,
2396         .hw_params      = wm8994_hw_params,
2397         .shutdown       = wm8994_aif_shutdown,
2398         .digital_mute   = wm8994_aif_mute,
2399         .set_pll        = wm8994_set_fll,
2400         .set_tristate   = wm8994_set_tristate,
2401 };
2402
2403 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2404         .set_sysclk     = wm8994_set_dai_sysclk,
2405         .set_fmt        = wm8994_set_dai_fmt,
2406         .hw_params      = wm8994_hw_params,
2407         .shutdown       = wm8994_aif_shutdown,
2408         .digital_mute   = wm8994_aif_mute,
2409         .set_pll        = wm8994_set_fll,
2410         .set_tristate   = wm8994_set_tristate,
2411 };
2412
2413 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2414         .hw_params      = wm8994_aif3_hw_params,
2415         .set_tristate   = wm8994_set_tristate,
2416 };
2417
2418 static struct snd_soc_dai_driver wm8994_dai[] = {
2419         {
2420                 .name = "wm8994-aif1",
2421                 .id = 1,
2422                 .playback = {
2423                         .stream_name = "AIF1 Playback",
2424                         .channels_min = 1,
2425                         .channels_max = 2,
2426                         .rates = WM8994_RATES,
2427                         .formats = WM8994_FORMATS,
2428                 },
2429                 .capture = {
2430                         .stream_name = "AIF1 Capture",
2431                         .channels_min = 1,
2432                         .channels_max = 2,
2433                         .rates = WM8994_RATES,
2434                         .formats = WM8994_FORMATS,
2435                  },
2436                 .ops = &wm8994_aif1_dai_ops,
2437         },
2438         {
2439                 .name = "wm8994-aif2",
2440                 .id = 2,
2441                 .playback = {
2442                         .stream_name = "AIF2 Playback",
2443                         .channels_min = 1,
2444                         .channels_max = 2,
2445                         .rates = WM8994_RATES,
2446                         .formats = WM8994_FORMATS,
2447                 },
2448                 .capture = {
2449                         .stream_name = "AIF2 Capture",
2450                         .channels_min = 1,
2451                         .channels_max = 2,
2452                         .rates = WM8994_RATES,
2453                         .formats = WM8994_FORMATS,
2454                 },
2455                 .ops = &wm8994_aif2_dai_ops,
2456         },
2457         {
2458                 .name = "wm8994-aif3",
2459                 .id = 3,
2460                 .playback = {
2461                         .stream_name = "AIF3 Playback",
2462                         .channels_min = 1,
2463                         .channels_max = 2,
2464                         .rates = WM8994_RATES,
2465                         .formats = WM8994_FORMATS,
2466                 },
2467                 .capture = {
2468                         .stream_name = "AIF3 Capture",
2469                         .channels_min = 1,
2470                         .channels_max = 2,
2471                         .rates = WM8994_RATES,
2472                         .formats = WM8994_FORMATS,
2473                 },
2474                 .ops = &wm8994_aif3_dai_ops,
2475         }
2476 };
2477
2478 #ifdef CONFIG_PM
2479 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2480 {
2481         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2482         struct wm8994 *control = codec->control_data;
2483         int i, ret;
2484
2485         switch (control->type) {
2486         case WM8994:
2487                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2488                 break;
2489         case WM8958:
2490                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2491                                     WM8958_MICD_ENA, 0);
2492                 break;
2493         }
2494
2495         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2496                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2497                        sizeof(struct wm8994_fll_config));
2498                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2499                 if (ret < 0)
2500                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2501                                  i + 1, ret);
2502         }
2503
2504         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2505
2506         return 0;
2507 }
2508
2509 static int wm8994_resume(struct snd_soc_codec *codec)
2510 {
2511         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2512         struct wm8994 *control = codec->control_data;
2513         int i, ret;
2514         unsigned int val, mask;
2515
2516         if (wm8994->revision < 4) {
2517                 /* force a HW read */
2518                 val = wm8994_reg_read(codec->control_data,
2519                                       WM8994_POWER_MANAGEMENT_5);
2520
2521                 /* modify the cache only */
2522                 codec->cache_only = 1;
2523                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2524                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2525                 val &= mask;
2526                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2527                                     mask, val);
2528                 codec->cache_only = 0;
2529         }
2530
2531         /* Restore the registers */
2532         ret = snd_soc_cache_sync(codec);
2533         if (ret != 0)
2534                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2535
2536         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2537
2538         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2539                 if (!wm8994->fll_suspend[i].out)
2540                         continue;
2541
2542                 ret = _wm8994_set_fll(codec, i + 1,
2543                                      wm8994->fll_suspend[i].src,
2544                                      wm8994->fll_suspend[i].in,
2545                                      wm8994->fll_suspend[i].out);
2546                 if (ret < 0)
2547                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2548                                  i + 1, ret);
2549         }
2550
2551         switch (control->type) {
2552         case WM8994:
2553                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2554                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2555                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2556                 break;
2557         case WM8958:
2558                 if (wm8994->jack_cb)
2559                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2560                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2561                 break;
2562         }
2563
2564         return 0;
2565 }
2566 #else
2567 #define wm8994_suspend NULL
2568 #define wm8994_resume NULL
2569 #endif
2570
2571 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2572 {
2573         struct snd_soc_codec *codec = wm8994->codec;
2574         struct wm8994_pdata *pdata = wm8994->pdata;
2575         struct snd_kcontrol_new controls[] = {
2576                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2577                              wm8994->retune_mobile_enum,
2578                              wm8994_get_retune_mobile_enum,
2579                              wm8994_put_retune_mobile_enum),
2580                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2581                              wm8994->retune_mobile_enum,
2582                              wm8994_get_retune_mobile_enum,
2583                              wm8994_put_retune_mobile_enum),
2584                 SOC_ENUM_EXT("AIF2 EQ Mode",
2585                              wm8994->retune_mobile_enum,
2586                              wm8994_get_retune_mobile_enum,
2587                              wm8994_put_retune_mobile_enum),
2588         };
2589         int ret, i, j;
2590         const char **t;
2591
2592         /* We need an array of texts for the enum API but the number
2593          * of texts is likely to be less than the number of
2594          * configurations due to the sample rate dependency of the
2595          * configurations. */
2596         wm8994->num_retune_mobile_texts = 0;
2597         wm8994->retune_mobile_texts = NULL;
2598         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2599                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2600                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2601                                    wm8994->retune_mobile_texts[j]) == 0)
2602                                 break;
2603                 }
2604
2605                 if (j != wm8994->num_retune_mobile_texts)
2606                         continue;
2607
2608                 /* Expand the array... */
2609                 t = krealloc(wm8994->retune_mobile_texts,
2610                              sizeof(char *) *
2611                              (wm8994->num_retune_mobile_texts + 1),
2612                              GFP_KERNEL);
2613                 if (t == NULL)
2614                         continue;
2615
2616                 /* ...store the new entry... */
2617                 t[wm8994->num_retune_mobile_texts] =
2618                         pdata->retune_mobile_cfgs[i].name;
2619
2620                 /* ...and remember the new version. */
2621                 wm8994->num_retune_mobile_texts++;
2622                 wm8994->retune_mobile_texts = t;
2623         }
2624
2625         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2626                 wm8994->num_retune_mobile_texts);
2627
2628         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2629         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2630
2631         ret = snd_soc_add_controls(wm8994->codec, controls,
2632                                    ARRAY_SIZE(controls));
2633         if (ret != 0)
2634                 dev_err(wm8994->codec->dev,
2635                         "Failed to add ReTune Mobile controls: %d\n", ret);
2636 }
2637
2638 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2639 {
2640         struct snd_soc_codec *codec = wm8994->codec;
2641         struct wm8994_pdata *pdata = wm8994->pdata;
2642         int ret, i;
2643
2644         if (!pdata)
2645                 return;
2646
2647         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2648                                       pdata->lineout2_diff,
2649                                       pdata->lineout1fb,
2650                                       pdata->lineout2fb,
2651                                       pdata->jd_scthr,
2652                                       pdata->jd_thr,
2653                                       pdata->micbias1_lvl,
2654                                       pdata->micbias2_lvl);
2655
2656         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2657
2658         if (pdata->num_drc_cfgs) {
2659                 struct snd_kcontrol_new controls[] = {
2660                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2661                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2662                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2663                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2664                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2665                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2666                 };
2667
2668                 /* We need an array of texts for the enum API */
2669                 wm8994->drc_texts = kmalloc(sizeof(char *)
2670                                             * pdata->num_drc_cfgs, GFP_KERNEL);
2671                 if (!wm8994->drc_texts) {
2672                         dev_err(wm8994->codec->dev,
2673                                 "Failed to allocate %d DRC config texts\n",
2674                                 pdata->num_drc_cfgs);
2675                         return;
2676                 }
2677
2678                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2679                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2680
2681                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2682                 wm8994->drc_enum.texts = wm8994->drc_texts;
2683
2684                 ret = snd_soc_add_controls(wm8994->codec, controls,
2685                                            ARRAY_SIZE(controls));
2686                 if (ret != 0)
2687                         dev_err(wm8994->codec->dev,
2688                                 "Failed to add DRC mode controls: %d\n", ret);
2689
2690                 for (i = 0; i < WM8994_NUM_DRC; i++)
2691                         wm8994_set_drc(codec, i);
2692         }
2693
2694         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2695                 pdata->num_retune_mobile_cfgs);
2696
2697         if (pdata->num_retune_mobile_cfgs)
2698                 wm8994_handle_retune_mobile_pdata(wm8994);
2699         else
2700                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2701                                      ARRAY_SIZE(wm8994_eq_controls));
2702
2703         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2704                 if (pdata->micbias[i]) {
2705                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
2706                                 pdata->micbias[i] & 0xffff);
2707                 }
2708         }
2709 }
2710
2711 /**
2712  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2713  *
2714  * @codec:   WM8994 codec
2715  * @jack:    jack to report detection events on
2716  * @micbias: microphone bias to detect on
2717  * @det:     value to report for presence detection
2718  * @shrt:    value to report for short detection
2719  *
2720  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2721  * being used to bring out signals to the processor then only platform
2722  * data configuration is needed for WM8994 and processor GPIOs should
2723  * be configured using snd_soc_jack_add_gpios() instead.
2724  *
2725  * Configuration of detection levels is available via the micbias1_lvl
2726  * and micbias2_lvl platform data members.
2727  */
2728 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2729                       int micbias, int det, int shrt)
2730 {
2731         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2732         struct wm8994_micdet *micdet;
2733         struct wm8994 *control = codec->control_data;
2734         int reg;
2735
2736         if (control->type != WM8994)
2737                 return -EINVAL;
2738
2739         switch (micbias) {
2740         case 1:
2741                 micdet = &wm8994->micdet[0];
2742                 break;
2743         case 2:
2744                 micdet = &wm8994->micdet[1];
2745                 break;
2746         default:
2747                 return -EINVAL;
2748         }
2749
2750         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2751                 micbias, det, shrt);
2752
2753         /* Store the configuration */
2754         micdet->jack = jack;
2755         micdet->det = det;
2756         micdet->shrt = shrt;
2757
2758         /* If either of the jacks is set up then enable detection */
2759         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2760                 reg = WM8994_MICD_ENA;
2761         else
2762                 reg = 0;
2763
2764         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2765
2766         return 0;
2767 }
2768 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2769
2770 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2771 {
2772         struct wm8994_priv *priv = data;
2773         struct snd_soc_codec *codec = priv->codec;
2774         int reg;
2775         int report;
2776
2777 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2778         trace_snd_soc_jack_irq(dev_name(codec->dev));
2779 #endif
2780
2781         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2782         if (reg < 0) {
2783                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2784                         reg);
2785                 return IRQ_HANDLED;
2786         }
2787
2788         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2789
2790         report = 0;
2791         if (reg & WM8994_MIC1_DET_STS)
2792                 report |= priv->micdet[0].det;
2793         if (reg & WM8994_MIC1_SHRT_STS)
2794                 report |= priv->micdet[0].shrt;
2795         snd_soc_jack_report(priv->micdet[0].jack, report,
2796                             priv->micdet[0].det | priv->micdet[0].shrt);
2797
2798         report = 0;
2799         if (reg & WM8994_MIC2_DET_STS)
2800                 report |= priv->micdet[1].det;
2801         if (reg & WM8994_MIC2_SHRT_STS)
2802                 report |= priv->micdet[1].shrt;
2803         snd_soc_jack_report(priv->micdet[1].jack, report,
2804                             priv->micdet[1].det | priv->micdet[1].shrt);
2805
2806         return IRQ_HANDLED;
2807 }
2808
2809 /* Default microphone detection handler for WM8958 - the user can
2810  * override this if they wish.
2811  */
2812 static void wm8958_default_micdet(u16 status, void *data)
2813 {
2814         struct snd_soc_codec *codec = data;
2815         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2816         int report = 0;
2817
2818         /* If nothing present then clear our statuses */
2819         if (!(status & WM8958_MICD_STS))
2820                 goto done;
2821
2822         report = SND_JACK_MICROPHONE;
2823
2824         /* Everything else is buttons; just assign slots */
2825         if (status & 0x1c)
2826                 report |= SND_JACK_BTN_0;
2827
2828 done:
2829         snd_soc_jack_report(wm8994->micdet[0].jack, report,
2830                             SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
2831 }
2832
2833 /**
2834  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2835  *
2836  * @codec:   WM8958 codec
2837  * @jack:    jack to report detection events on
2838  *
2839  * Enable microphone detection functionality for the WM8958.  By
2840  * default simple detection which supports the detection of up to 6
2841  * buttons plus video and microphone functionality is supported.
2842  *
2843  * The WM8958 has an advanced jack detection facility which is able to
2844  * support complex accessory detection, especially when used in
2845  * conjunction with external circuitry.  In order to provide maximum
2846  * flexiblity a callback is provided which allows a completely custom
2847  * detection algorithm.
2848  */
2849 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2850                       wm8958_micdet_cb cb, void *cb_data)
2851 {
2852         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2853         struct wm8994 *control = codec->control_data;
2854
2855         if (control->type != WM8958)
2856                 return -EINVAL;
2857
2858         if (jack) {
2859                 if (!cb) {
2860                         dev_dbg(codec->dev, "Using default micdet callback\n");
2861                         cb = wm8958_default_micdet;
2862                         cb_data = codec;
2863                 }
2864
2865                 wm8994->micdet[0].jack = jack;
2866                 wm8994->jack_cb = cb;
2867                 wm8994->jack_cb_data = cb_data;
2868
2869                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2870                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
2871         } else {
2872                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2873                                     WM8958_MICD_ENA, 0);
2874         }
2875
2876         return 0;
2877 }
2878 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2879
2880 static irqreturn_t wm8958_mic_irq(int irq, void *data)
2881 {
2882         struct wm8994_priv *wm8994 = data;
2883         struct snd_soc_codec *codec = wm8994->codec;
2884         int reg;
2885
2886         reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2887         if (reg < 0) {
2888                 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2889                         reg);
2890                 return IRQ_NONE;
2891         }
2892
2893         if (!(reg & WM8958_MICD_VALID)) {
2894                 dev_dbg(codec->dev, "Mic detect data not valid\n");
2895                 goto out;
2896         }
2897
2898 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2899         trace_snd_soc_jack_irq(dev_name(codec->dev));
2900 #endif
2901
2902         if (wm8994->jack_cb)
2903                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2904         else
2905                 dev_warn(codec->dev, "Accessory detection with no callback\n");
2906
2907 out:
2908         return IRQ_HANDLED;
2909 }
2910
2911 static irqreturn_t wm8994_fifo_error(int irq, void *data)
2912 {
2913         struct snd_soc_codec *codec = data;
2914
2915         dev_err(codec->dev, "FIFO error\n");
2916
2917         return IRQ_HANDLED;
2918 }
2919
2920 static int wm8994_codec_probe(struct snd_soc_codec *codec)
2921 {
2922         struct wm8994 *control;
2923         struct wm8994_priv *wm8994;
2924         struct snd_soc_dapm_context *dapm = &codec->dapm;
2925         int ret, i;
2926
2927         codec->control_data = dev_get_drvdata(codec->dev->parent);
2928         control = codec->control_data;
2929
2930         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2931         if (wm8994 == NULL)
2932                 return -ENOMEM;
2933         snd_soc_codec_set_drvdata(codec, wm8994);
2934
2935         wm8994->pdata = dev_get_platdata(codec->dev->parent);
2936         wm8994->codec = codec;
2937
2938         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2939                 init_completion(&wm8994->fll_locked[i]);
2940
2941         if (wm8994->pdata && wm8994->pdata->micdet_irq)
2942                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
2943         else if (wm8994->pdata && wm8994->pdata->irq_base)
2944                 wm8994->micdet_irq = wm8994->pdata->irq_base +
2945                                      WM8994_IRQ_MIC1_DET;
2946
2947         pm_runtime_enable(codec->dev);
2948         pm_runtime_resume(codec->dev);
2949
2950         /* Read our current status back from the chip - we don't want to
2951          * reset as this may interfere with the GPIO or LDO operation. */
2952         for (i = 0; i < WM8994_CACHE_SIZE; i++) {
2953                 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
2954                         continue;
2955
2956                 ret = wm8994_reg_read(codec->control_data, i);
2957                 if (ret <= 0)
2958                         continue;
2959
2960                 ret = snd_soc_cache_write(codec, i, ret);
2961                 if (ret != 0) {
2962                         dev_err(codec->dev,
2963                                 "Failed to initialise cache for 0x%x: %d\n",
2964                                 i, ret);
2965                         goto err;
2966                 }
2967         }
2968
2969         /* Set revision-specific configuration */
2970         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
2971         switch (control->type) {
2972         case WM8994:
2973                 switch (wm8994->revision) {
2974                 case 2:
2975                 case 3:
2976                         wm8994->hubs.dcs_codes = -5;
2977                         wm8994->hubs.hp_startup_mode = 1;
2978                         wm8994->hubs.dcs_readback_mode = 1;
2979                         wm8994->hubs.series_startup = 1;
2980                         break;
2981                 default:
2982                         wm8994->hubs.dcs_readback_mode = 2;
2983                         break;
2984                 }
2985
2986         case WM8958:
2987                 wm8994->hubs.dcs_readback_mode = 1;
2988                 break;
2989
2990         default:
2991                 break;
2992         }
2993
2994         wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR,
2995                            wm8994_fifo_error, "FIFO error", codec);
2996
2997         ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
2998                                  wm_hubs_dcs_done, "DC servo done",
2999                                  &wm8994->hubs);
3000         if (ret == 0)
3001                 wm8994->hubs.dcs_done_irq = true;
3002
3003         switch (control->type) {
3004         case WM8994:
3005                 if (wm8994->micdet_irq) {
3006                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3007                                                    wm8994_mic_irq,
3008                                                    IRQF_TRIGGER_RISING,
3009                                                    "Mic1 detect",
3010                                                    wm8994);
3011                         if (ret != 0)
3012                                 dev_warn(codec->dev,
3013                                          "Failed to request Mic1 detect IRQ: %d\n",
3014                                          ret);
3015                 }
3016
3017                 ret = wm8994_request_irq(codec->control_data,
3018                                          WM8994_IRQ_MIC1_SHRT,
3019                                          wm8994_mic_irq, "Mic 1 short",
3020                                          wm8994);
3021                 if (ret != 0)
3022                         dev_warn(codec->dev,
3023                                  "Failed to request Mic1 short IRQ: %d\n",
3024                                  ret);
3025
3026                 ret = wm8994_request_irq(codec->control_data,
3027                                          WM8994_IRQ_MIC2_DET,
3028                                          wm8994_mic_irq, "Mic 2 detect",
3029                                          wm8994);
3030                 if (ret != 0)
3031                         dev_warn(codec->dev,
3032                                  "Failed to request Mic2 detect IRQ: %d\n",
3033                                  ret);
3034
3035                 ret = wm8994_request_irq(codec->control_data,
3036                                          WM8994_IRQ_MIC2_SHRT,
3037                                          wm8994_mic_irq, "Mic 2 short",
3038                                          wm8994);
3039                 if (ret != 0)
3040                         dev_warn(codec->dev,
3041                                  "Failed to request Mic2 short IRQ: %d\n",
3042                                  ret);
3043                 break;
3044
3045         case WM8958:
3046                 if (wm8994->micdet_irq) {
3047                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3048                                                    wm8958_mic_irq,
3049                                                    IRQF_TRIGGER_RISING,
3050                                                    "Mic detect",
3051                                                    wm8994);
3052                         if (ret != 0)
3053                                 dev_warn(codec->dev,
3054                                          "Failed to request Mic detect IRQ: %d\n",
3055                                          ret);
3056                 }
3057         }
3058
3059         wm8994->fll_locked_irq = true;
3060         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3061                 ret = wm8994_request_irq(codec->control_data,
3062                                          WM8994_IRQ_FLL1_LOCK + i,
3063                                          wm8994_fll_locked_irq, "FLL lock",
3064                                          &wm8994->fll_locked[i]);
3065                 if (ret != 0)
3066                         wm8994->fll_locked_irq = false;
3067         }
3068
3069         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3070          * configured on init - if a system wants to do this dynamically
3071          * at runtime we can deal with that then.
3072          */
3073         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3074         if (ret < 0) {
3075                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3076                 goto err_irq;
3077         }
3078         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3079                 wm8994->lrclk_shared[0] = 1;
3080                 wm8994_dai[0].symmetric_rates = 1;
3081         } else {
3082                 wm8994->lrclk_shared[0] = 0;
3083         }
3084
3085         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3086         if (ret < 0) {
3087                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3088                 goto err_irq;
3089         }
3090         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3091                 wm8994->lrclk_shared[1] = 1;
3092                 wm8994_dai[1].symmetric_rates = 1;
3093         } else {
3094                 wm8994->lrclk_shared[1] = 0;
3095         }
3096
3097         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3098
3099         /* Latch volume updates (right only; we always do left then right). */
3100         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3101                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3102         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3103                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3104         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3105                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3106         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3107                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3108         snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3109                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3110         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3111                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3112         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3113                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3114         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3115                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3116         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3117                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3118         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3119                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3120         snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3121                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3122         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3123                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3124         snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3125                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3126         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3127                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3128         snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3129                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3130         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3131                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3132
3133         /* Set the low bit of the 3D stereo depth so TLV matches */
3134         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3135                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3136                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3137         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3138                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3139                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3140         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3141                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3142                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3143
3144         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3145          * use this; it only affects behaviour on idle TDM clock
3146          * cycles. */
3147         switch (control->type) {
3148         case WM8994:
3149         case WM8958:
3150                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3151                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3152                 break;
3153         default:
3154                 break;
3155         }
3156
3157         wm8994_update_class_w(codec);
3158
3159         wm8994_handle_pdata(wm8994);
3160
3161         wm_hubs_add_analogue_controls(codec);
3162         snd_soc_add_controls(codec, wm8994_snd_controls,
3163                              ARRAY_SIZE(wm8994_snd_controls));
3164         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3165                                   ARRAY_SIZE(wm8994_dapm_widgets));
3166
3167         switch (control->type) {
3168         case WM8994:
3169                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3170                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3171                 if (wm8994->revision < 4) {
3172                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3173                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3174                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3175                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3176                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3177                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3178                 } else {
3179                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3180                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3181                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3182                                                   ARRAY_SIZE(wm8994_adc_widgets));
3183                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3184                                                   ARRAY_SIZE(wm8994_dac_widgets));
3185                 }
3186                 break;
3187         case WM8958:
3188                 snd_soc_add_controls(codec, wm8958_snd_controls,
3189                                      ARRAY_SIZE(wm8958_snd_controls));
3190                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3191                                           ARRAY_SIZE(wm8958_dapm_widgets));
3192                 if (wm8994->revision < 1) {
3193                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3194                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3195                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3196                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3197                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3198                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3199                 } else {
3200                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3201                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3202                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3203                                                   ARRAY_SIZE(wm8994_adc_widgets));
3204                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3205                                                   ARRAY_SIZE(wm8994_dac_widgets));
3206                 }
3207                 break;
3208         }
3209
3210
3211         wm_hubs_add_analogue_routes(codec, 0, 0);
3212         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3213
3214         switch (control->type) {
3215         case WM8994:
3216                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3217                                         ARRAY_SIZE(wm8994_intercon));
3218
3219                 if (wm8994->revision < 4) {
3220                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3221                                                 ARRAY_SIZE(wm8994_revd_intercon));
3222                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3223                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3224                 } else {
3225                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3226                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3227                 }
3228                 break;
3229         case WM8958:
3230                 if (wm8994->revision < 1) {
3231                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3232                                                 ARRAY_SIZE(wm8994_revd_intercon));
3233                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3234                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3235                 } else {
3236                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3237                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3238                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3239                                                 ARRAY_SIZE(wm8958_intercon));
3240                 }
3241
3242                 wm8958_dsp2_init(codec);
3243                 break;
3244         }
3245
3246         return 0;
3247
3248 err_irq:
3249         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3250         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3251         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3252         if (wm8994->micdet_irq)
3253                 free_irq(wm8994->micdet_irq, wm8994);
3254         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3255                 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3256                                 &wm8994->fll_locked[i]);
3257         wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3258                         &wm8994->hubs);
3259         wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3260 err:
3261         kfree(wm8994);
3262         return ret;
3263 }
3264
3265 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3266 {
3267         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3268         struct wm8994 *control = codec->control_data;
3269         int i;
3270
3271         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3272
3273         pm_runtime_disable(codec->dev);
3274
3275         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3276                 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3277                                 &wm8994->fll_locked[i]);
3278
3279         wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3280                         &wm8994->hubs);
3281         wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3282
3283         switch (control->type) {
3284         case WM8994:
3285                 if (wm8994->micdet_irq)
3286                         free_irq(wm8994->micdet_irq, wm8994);
3287                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3288                                 wm8994);
3289                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3290                                 wm8994);
3291                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3292                                 wm8994);
3293                 break;
3294
3295         case WM8958:
3296                 if (wm8994->micdet_irq)
3297                         free_irq(wm8994->micdet_irq, wm8994);
3298                 break;
3299         }
3300         if (wm8994->mbc)
3301                 release_firmware(wm8994->mbc);
3302         if (wm8994->mbc_vss)
3303                 release_firmware(wm8994->mbc_vss);
3304         if (wm8994->enh_eq)
3305                 release_firmware(wm8994->enh_eq);
3306         kfree(wm8994->retune_mobile_texts);
3307         kfree(wm8994->drc_texts);
3308         kfree(wm8994);
3309
3310         return 0;
3311 }
3312
3313 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3314         .probe =        wm8994_codec_probe,
3315         .remove =       wm8994_codec_remove,
3316         .suspend =      wm8994_suspend,
3317         .resume =       wm8994_resume,
3318         .read =         wm8994_read,
3319         .write =        wm8994_write,
3320         .readable_register = wm8994_readable,
3321         .volatile_register = wm8994_volatile,
3322         .set_bias_level = wm8994_set_bias_level,
3323
3324         .reg_cache_size = WM8994_CACHE_SIZE,
3325         .reg_cache_default = wm8994_reg_defaults,
3326         .reg_word_size = 2,
3327         .compress_type = SND_SOC_RBTREE_COMPRESSION,
3328 };
3329
3330 static int __devinit wm8994_probe(struct platform_device *pdev)
3331 {
3332         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3333                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3334 }
3335
3336 static int __devexit wm8994_remove(struct platform_device *pdev)
3337 {
3338         snd_soc_unregister_codec(&pdev->dev);
3339         return 0;
3340 }
3341
3342 static struct platform_driver wm8994_codec_driver = {
3343         .driver = {
3344                    .name = "wm8994-codec",
3345                    .owner = THIS_MODULE,
3346                    },
3347         .probe = wm8994_probe,
3348         .remove = __devexit_p(wm8994_remove),
3349 };
3350
3351 static __init int wm8994_init(void)
3352 {
3353         return platform_driver_register(&wm8994_codec_driver);
3354 }
3355 module_init(wm8994_init);
3356
3357 static __exit void wm8994_exit(void)
3358 {
3359         platform_driver_unregister(&wm8994_codec_driver);
3360 }
3361 module_exit(wm8994_exit);
3362
3363
3364 MODULE_DESCRIPTION("ASoC WM8994 driver");
3365 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3366 MODULE_LICENSE("GPL");
3367 MODULE_ALIAS("platform:wm8994-codec");