Pileus Git - ~andy/linux/blob - sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009-12 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM1811_JACKDET_MODE_NONE  0x0000
  42 #define WM1811_JACKDET_MODE_JACK  0x0100
  43 #define WM1811_JACKDET_MODE_MIC   0x0080
  44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
  45
  46 #define WM8994_NUM_DRC 3
  47 #define WM8994_NUM_EQ  3
  48
  49 static struct {
  50         unsigned int reg;
  51         unsigned int mask;
  52 } wm8994_vu_bits[] = {
  53         { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  54         { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  55         { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  56         { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  57         { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
  58         { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
  59         { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  60         { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  61         { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  62         { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  63
  64         { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
  65         { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
  66         { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
  67         { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
  68         { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
  69         { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
  70         { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
  71         { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
  72         { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
  73         { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  74         { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
  75         { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  76         { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
  77         { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
  78         { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
  79         { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
  80 };
  81
  82 static int wm8994_drc_base[] = {
  83         WM8994_AIF1_DRC1_1,
  84         WM8994_AIF1_DRC2_1,
  85         WM8994_AIF2_DRC_1,
  86 };
  87
  88 static int wm8994_retune_mobile_base[] = {
  89         WM8994_AIF1_DAC1_EQ_GAINS_1,
  90         WM8994_AIF1_DAC2_EQ_GAINS_1,
  91         WM8994_AIF2_EQ_GAINS_1,
  92 };
  93
  94 static void wm8958_default_micdet(u16 status, void *data);
  95
  96 static const struct wm8958_micd_rate micdet_rates[] = {
  97         { 32768,       true,  1, 4 },
  98         { 32768,       false, 1, 1 },
  99         { 44100 * 256, true,  7, 10 },
 100         { 44100 * 256, false, 7, 10 },
 101 };
 102
 103 static const struct wm8958_micd_rate jackdet_rates[] = {
 104         { 32768,       true,  0, 1 },
 105         { 32768,       false, 0, 1 },
 106         { 44100 * 256, true,  10, 10 },
 107         { 44100 * 256, false, 7, 8 },
 108 };
 109
 110 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
 111 {
 112         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 113         int best, i, sysclk, val;
 114         bool idle;
 115         const struct wm8958_micd_rate *rates;
 116         int num_rates;
 117
 118         if (!(wm8994->pdata && wm8994->pdata->micd_rates) &&
 119             wm8994->jack_cb != wm8958_default_micdet)
 120                 return;
 121
 122         idle = !wm8994->jack_mic;
 123
 124         sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
 125         if (sysclk & WM8994_SYSCLK_SRC)
 126                 sysclk = wm8994->aifclk[1];
 127         else
 128                 sysclk = wm8994->aifclk[0];
 129
 130         if (wm8994->pdata && wm8994->pdata->micd_rates) {
 131                 rates = wm8994->pdata->micd_rates;
 132                 num_rates = wm8994->pdata->num_micd_rates;
 133         } else if (wm8994->jackdet) {
 134                 rates = jackdet_rates;
 135                 num_rates = ARRAY_SIZE(jackdet_rates);
 136         } else {
 137                 rates = micdet_rates;
 138                 num_rates = ARRAY_SIZE(micdet_rates);
 139         }
 140
 141         best = 0;
 142         for (i = 0; i < num_rates; i++) {
 143                 if (rates[i].idle != idle)
 144                         continue;
 145                 if (abs(rates[i].sysclk - sysclk) <
 146                     abs(rates[best].sysclk - sysclk))
 147                         best = i;
 148                 else if (rates[best].idle != idle)
 149                         best = i;
 150         }
 151
 152         val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
 153                 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
 154
 155         dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
 156                 rates[best].start, rates[best].rate, sysclk,
 157                 idle ? "idle" : "active");
 158
 159         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
 160                             WM8958_MICD_BIAS_STARTTIME_MASK |
 161                             WM8958_MICD_RATE_MASK, val);
 162 }
 163
 164 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 165 {
 166         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 167         int rate;
 168         int reg1 = 0;
 169         int offset;
 170
 171         if (aif)
 172                 offset = 4;
 173         else
 174                 offset = 0;
 175
 176         switch (wm8994->sysclk[aif]) {
 177         case WM8994_SYSCLK_MCLK1:
 178                 rate = wm8994->mclk[0];
 179                 break;
 180
 181         case WM8994_SYSCLK_MCLK2:
 182                 reg1 |= 0x8;
 183                 rate = wm8994->mclk[1];
 184                 break;
 185
 186         case WM8994_SYSCLK_FLL1:
 187                 reg1 |= 0x10;
 188                 rate = wm8994->fll[0].out;
 189                 break;
 190
 191         case WM8994_SYSCLK_FLL2:
 192                 reg1 |= 0x18;
 193                 rate = wm8994->fll[1].out;
 194                 break;
 195
 196         default:
 197                 return -EINVAL;
 198         }
 199
 200         if (rate >= 13500000) {
 201                 rate /= 2;
 202                 reg1 |= WM8994_AIF1CLK_DIV;
 203
 204                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 205                         aif + 1, rate);
 206         }
 207
 208         wm8994->aifclk[aif] = rate;
 209
 210         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 211                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 212                             reg1);
 213
 214         return 0;
 215 }
 216
 217 static int configure_clock(struct snd_soc_codec *codec)
 218 {
 219         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 220         int change, new;
 221
 222         /* Bring up the AIF clocks first */
 223         configure_aif_clock(codec, 0);
 224         configure_aif_clock(codec, 1);
 225
 226         /* Then switch CLK_SYS over to the higher of them; a change
 227          * can only happen as a result of a clocking change which can
 228          * only be made outside of DAPM so we can safely redo the
 229          * clocking.
 230          */
 231
 232         /* If they're equal it doesn't matter which is used */
 233         if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
 234                 wm8958_micd_set_rate(codec);
 235                 return 0;
 236         }
 237
 238         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 239                 new = WM8994_SYSCLK_SRC;
 240         else
 241                 new = 0;
 242
 243         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 244                                      WM8994_SYSCLK_SRC, new);
 245         if (change)
 246                 snd_soc_dapm_sync(&codec->dapm);
 247
 248         wm8958_micd_set_rate(codec);
 249
 250         return 0;
 251 }
 252
 253 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 254                          struct snd_soc_dapm_widget *sink)
 255 {
 256         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 257         const char *clk;
 258
 259         /* Check what we're currently using for CLK_SYS */
 260         if (reg & WM8994_SYSCLK_SRC)
 261                 clk = "AIF2CLK";
 262         else
 263                 clk = "AIF1CLK";
 264
 265         return strcmp(source->name, clk) == 0;
 266 }
 267
 268 static const char *sidetone_hpf_text[] = {
 269         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 270 };
 271
 272 static const struct soc_enum sidetone_hpf =
 273         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 274
 275 static const char *adc_hpf_text[] = {
 276         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 277 };
 278
 279 static const struct soc_enum aif1adc1_hpf =
 280         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 281
 282 static const struct soc_enum aif1adc2_hpf =
 283         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 284
 285 static const struct soc_enum aif2adc_hpf =
 286         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 287
 288 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 289 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 290 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 291 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 292 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 293 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 294 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 295
 296 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 297 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 298         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 299         .put = wm8994_put_drc_sw, \
 300         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 301
 302 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 303                              struct snd_ctl_elem_value *ucontrol)
 304 {
 305         struct soc_mixer_control *mc =
 306                 (struct soc_mixer_control *)kcontrol->private_value;
 307         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 308         int mask, ret;
 309
 310         /* Can't enable both ADC and DAC paths simultaneously */
 311         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 312                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 313                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 314         else
 315                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 316
 317         ret = snd_soc_read(codec, mc->reg);
 318         if (ret < 0)
 319                 return ret;
 320         if (ret & mask)
 321                 return -EINVAL;
 322
 323         return snd_soc_put_volsw(kcontrol, ucontrol);
 324 }
 325
 326 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 327 {
 328         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 329         struct wm8994_pdata *pdata = wm8994->pdata;
 330         int base = wm8994_drc_base[drc];
 331         int cfg = wm8994->drc_cfg[drc];
 332         int save, i;
 333
 334         /* Save any enables; the configuration should clear them. */
 335         save = snd_soc_read(codec, base);
 336         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 337                 WM8994_AIF1ADC1R_DRC_ENA;
 338
 339         for (i = 0; i < WM8994_DRC_REGS; i++)
 340                 snd_soc_update_bits(codec, base + i, 0xffff,
 341                                     pdata->drc_cfgs[cfg].regs[i]);
 342
 343         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 344                              WM8994_AIF1ADC1L_DRC_ENA |
 345                              WM8994_AIF1ADC1R_DRC_ENA, save);
 346 }
 347
 348 /* Icky as hell but saves code duplication */
 349 static int wm8994_get_drc(const char *name)
 350 {
 351         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 352                 return 0;
 353         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 354                 return 1;
 355         if (strcmp(name, "AIF2DRC Mode") == 0)
 356                 return 2;
 357         return -EINVAL;
 358 }
 359
 360 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 361                                struct snd_ctl_elem_value *ucontrol)
 362 {
 363         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 364         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 365         struct wm8994_pdata *pdata = wm8994->pdata;
 366         int drc = wm8994_get_drc(kcontrol->id.name);
 367         int value = ucontrol->value.integer.value[0];
 368
 369         if (drc < 0)
 370                 return drc;
 371
 372         if (value >= pdata->num_drc_cfgs)
 373                 return -EINVAL;
 374
 375         wm8994->drc_cfg[drc] = value;
 376
 377         wm8994_set_drc(codec, drc);
 378
 379         return 0;
 380 }
 381
 382 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 383                                struct snd_ctl_elem_value *ucontrol)
 384 {
 385         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 386         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 387         int drc = wm8994_get_drc(kcontrol->id.name);
 388
 389         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 390
 391         return 0;
 392 }
 393
 394 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 395 {
 396         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 397         struct wm8994_pdata *pdata = wm8994->pdata;
 398         int base = wm8994_retune_mobile_base[block];
 399         int iface, best, best_val, save, i, cfg;
 400
 401         if (!pdata || !wm8994->num_retune_mobile_texts)
 402                 return;
 403
 404         switch (block) {
 405         case 0:
 406         case 1:
 407                 iface = 0;
 408                 break;
 409         case 2:
 410                 iface = 1;
 411                 break;
 412         default:
 413                 return;
 414         }
 415
 416         /* Find the version of the currently selected configuration
 417          * with the nearest sample rate. */
 418         cfg = wm8994->retune_mobile_cfg[block];
 419         best = 0;
 420         best_val = INT_MAX;
 421         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 422                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 423                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 424                     abs(pdata->retune_mobile_cfgs[i].rate
 425                         - wm8994->dac_rates[iface]) < best_val) {
 426                         best = i;
 427                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 428                                        - wm8994->dac_rates[iface]);
 429                 }
 430         }
 431
 432         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 433                 block,
 434                 pdata->retune_mobile_cfgs[best].name,
 435                 pdata->retune_mobile_cfgs[best].rate,
 436                 wm8994->dac_rates[iface]);
 437
 438         /* The EQ will be disabled while reconfiguring it, remember the
 439          * current configuration.
 440          */
 441         save = snd_soc_read(codec, base);
 442         save &= WM8994_AIF1DAC1_EQ_ENA;
 443
 444         for (i = 0; i < WM8994_EQ_REGS; i++)
 445                 snd_soc_update_bits(codec, base + i, 0xffff,
 446                                 pdata->retune_mobile_cfgs[best].regs[i]);
 447
 448         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 449 }
 450
 451 /* Icky as hell but saves code duplication */
 452 static int wm8994_get_retune_mobile_block(const char *name)
 453 {
 454         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 455                 return 0;
 456         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 457                 return 1;
 458         if (strcmp(name, "AIF2 EQ Mode") == 0)
 459                 return 2;
 460         return -EINVAL;
 461 }
 462
 463 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 464                                          struct snd_ctl_elem_value *ucontrol)
 465 {
 466         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 467         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 468         struct wm8994_pdata *pdata = wm8994->pdata;
 469         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 470         int value = ucontrol->value.integer.value[0];
 471
 472         if (block < 0)
 473                 return block;
 474
 475         if (value >= pdata->num_retune_mobile_cfgs)
 476                 return -EINVAL;
 477
 478         wm8994->retune_mobile_cfg[block] = value;
 479
 480         wm8994_set_retune_mobile(codec, block);
 481
 482         return 0;
 483 }
 484
 485 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 486                                          struct snd_ctl_elem_value *ucontrol)
 487 {
 488         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 489         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 490         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 491
 492         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 493
 494         return 0;
 495 }
 496
 497 static const char *aif_chan_src_text[] = {
 498         "Left", "Right"
 499 };
 500
 501 static const struct soc_enum aif1adcl_src =
 502         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 503
 504 static const struct soc_enum aif1adcr_src =
 505         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 506
 507 static const struct soc_enum aif2adcl_src =
 508         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 509
 510 static const struct soc_enum aif2adcr_src =
 511         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 512
 513 static const struct soc_enum aif1dacl_src =
 514         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 515
 516 static const struct soc_enum aif1dacr_src =
 517         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 518
 519 static const struct soc_enum aif2dacl_src =
 520         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 521
 522 static const struct soc_enum aif2dacr_src =
 523         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 524
 525 static const char *osr_text[] = {
 526         "Low Power", "High Performance",
 527 };
 528
 529 static const struct soc_enum dac_osr =
 530         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 531
 532 static const struct soc_enum adc_osr =
 533         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 534
 535 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 536 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 537                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 538                  1, 119, 0, digital_tlv),
 539 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 540                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 541                  1, 119, 0, digital_tlv),
 542 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 543                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 544                  1, 119, 0, digital_tlv),
 545
 546 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 547 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 548 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 549 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 550
 551 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 552 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 553 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 554 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 555
 556 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 557                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 558 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 559                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 560 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 561                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 562
 563 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 564 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 565
 566 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 567 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 568 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 569
 570 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 571 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 572 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 573
 574 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 575 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 576 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 577
 578 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 579 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 580 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 581
 582 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 583                5, 12, 0, st_tlv),
 584 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 585                0, 12, 0, st_tlv),
 586 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 587                5, 12, 0, st_tlv),
 588 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 589                0, 12, 0, st_tlv),
 590 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 591 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 592
 593 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 594 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 595
 596 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 597 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 598
 599 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 600 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 601
 602 SOC_ENUM("ADC OSR", adc_osr),
 603 SOC_ENUM("DAC OSR", dac_osr),
 604
 605 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 606                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 607 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 608              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 609
 610 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 611                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 612 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 613              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 614
 615 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 616                6, 1, 1, wm_hubs_spkmix_tlv),
 617 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 618                2, 1, 1, wm_hubs_spkmix_tlv),
 619
 620 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 621                6, 1, 1, wm_hubs_spkmix_tlv),
 622 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 623                2, 1, 1, wm_hubs_spkmix_tlv),
 624
 625 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 626                10, 15, 0, wm8994_3d_tlv),
 627 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 628            8, 1, 0),
 629 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 630                10, 15, 0, wm8994_3d_tlv),
 631 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 632            8, 1, 0),
 633 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 634                10, 15, 0, wm8994_3d_tlv),
 635 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 636            8, 1, 0),
 637 };
 638
 639 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 640 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 641                eq_tlv),
 642 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 643                eq_tlv),
 644 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 645                eq_tlv),
 646 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 647                eq_tlv),
 648 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 649                eq_tlv),
 650
 651 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 652                eq_tlv),
 653 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 654                eq_tlv),
 655 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 656                eq_tlv),
 657 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 658                eq_tlv),
 659 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 660                eq_tlv),
 661
 662 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 663                eq_tlv),
 664 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 665                eq_tlv),
 666 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 667                eq_tlv),
 668 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 669                eq_tlv),
 670 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 671                eq_tlv),
 672 };
 673
 674 static const char *wm8958_ng_text[] = {
 675         "30ms", "125ms", "250ms", "500ms",
 676 };
 677
 678 static const struct soc_enum wm8958_aif1dac1_ng_hold =
 679         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
 680                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
 681
 682 static const struct soc_enum wm8958_aif1dac2_ng_hold =
 683         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
 684                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
 685
 686 static const struct soc_enum wm8958_aif2dac_ng_hold =
 687         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
 688                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
 689
 690 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 691 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 692
 693 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 694            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 695 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 696 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 697                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 698                7, 1, ng_tlv),
 699
 700 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 701            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 702 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 703 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 704                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 705                7, 1, ng_tlv),
 706
 707 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 708            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 709 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 710 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 711                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 712                7, 1, ng_tlv),
 713 };
 714
 715 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 716 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 717                mixin_boost_tlv),
 718 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 719                mixin_boost_tlv),
 720 };
 721
 722 /* We run all mode setting through a function to enforce audio mode */
 723 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
 724 {
 725         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 726
 727         if (!wm8994->jackdet || !wm8994->jack_cb)
 728                 return;
 729
 730         if (wm8994->active_refcount)
 731                 mode = WM1811_JACKDET_MODE_AUDIO;
 732
 733         if (mode == wm8994->jackdet_mode)
 734                 return;
 735
 736         wm8994->jackdet_mode = mode;
 737
 738         /* Always use audio mode to detect while the system is active */
 739         if (mode != WM1811_JACKDET_MODE_NONE)
 740                 mode = WM1811_JACKDET_MODE_AUDIO;
 741
 742         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 743                             WM1811_JACKDET_MODE_MASK, mode);
 744 }
 745
 746 static void active_reference(struct snd_soc_codec *codec)
 747 {
 748         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 749
 750         mutex_lock(&wm8994->accdet_lock);
 751
 752         wm8994->active_refcount++;
 753
 754         dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
 755                 wm8994->active_refcount);
 756
 757         /* If we're using jack detection go into audio mode */
 758         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
 759
 760         mutex_unlock(&wm8994->accdet_lock);
 761 }
 762
 763 static void active_dereference(struct snd_soc_codec *codec)
 764 {
 765         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 766         u16 mode;
 767
 768         mutex_lock(&wm8994->accdet_lock);
 769
 770         wm8994->active_refcount--;
 771
 772         dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
 773                 wm8994->active_refcount);
 774
 775         if (wm8994->active_refcount == 0) {
 776                 /* Go into appropriate detection only mode */
 777                 if (wm8994->jack_mic || wm8994->mic_detecting)
 778                         mode = WM1811_JACKDET_MODE_MIC;
 779                 else
 780                         mode = WM1811_JACKDET_MODE_JACK;
 781
 782                 wm1811_jackdet_set_mode(codec, mode);
 783         }
 784
 785         mutex_unlock(&wm8994->accdet_lock);
 786 }
 787
 788 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 789                          struct snd_kcontrol *kcontrol, int event)
 790 {
 791         struct snd_soc_codec *codec = w->codec;
 792         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 793
 794         switch (event) {
 795         case SND_SOC_DAPM_PRE_PMU:
 796                 return configure_clock(codec);
 797
 798         case SND_SOC_DAPM_POST_PMU:
 799                 /*
 800                  * JACKDET won't run until we start the clock and it
 801                  * only reports deltas, make sure we notify the state
 802                  * up the stack on startup.  Use a *very* generous
 803                  * timeout for paranoia, there's no urgency and we
 804                  * don't want false reports.
 805                  */
 806                 if (wm8994->jackdet && !wm8994->clk_has_run) {
 807                         schedule_delayed_work(&wm8994->jackdet_bootstrap,
 808                                               msecs_to_jiffies(1000));
 809                         wm8994->clk_has_run = true;
 810                 }
 811                 break;
 812
 813         case SND_SOC_DAPM_POST_PMD:
 814                 configure_clock(codec);
 815                 break;
 816         }
 817
 818         return 0;
 819 }
 820
 821 static void vmid_reference(struct snd_soc_codec *codec)
 822 {
 823         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 824
 825         pm_runtime_get_sync(codec->dev);
 826
 827         wm8994->vmid_refcount++;
 828
 829         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
 830                 wm8994->vmid_refcount);
 831
 832         if (wm8994->vmid_refcount == 1) {
 833                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 834                                     WM8994_LINEOUT1_DISCH |
 835                                     WM8994_LINEOUT2_DISCH, 0);
 836
 837                 wm_hubs_vmid_ena(codec);
 838
 839                 switch (wm8994->vmid_mode) {
 840                 default:
 841                         WARN_ON(NULL == "Invalid VMID mode");
 842                 case WM8994_VMID_NORMAL:
 843                         /* Startup bias, VMID ramp & buffer */
 844                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 845                                             WM8994_BIAS_SRC |
 846                                             WM8994_VMID_DISCH |
 847                                             WM8994_STARTUP_BIAS_ENA |
 848                                             WM8994_VMID_BUF_ENA |
 849                                             WM8994_VMID_RAMP_MASK,
 850                                             WM8994_BIAS_SRC |
 851                                             WM8994_STARTUP_BIAS_ENA |
 852                                             WM8994_VMID_BUF_ENA |
 853                                             (0x3 << WM8994_VMID_RAMP_SHIFT));
 854
 855                         /* Main bias enable, VMID=2x40k */
 856                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 857                                             WM8994_BIAS_ENA |
 858                                             WM8994_VMID_SEL_MASK,
 859                                             WM8994_BIAS_ENA | 0x2);
 860
 861                         msleep(50);
 862
 863                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 864                                             WM8994_VMID_RAMP_MASK |
 865                                             WM8994_BIAS_SRC,
 866                                             0);
 867                         break;
 868
 869                 case WM8994_VMID_FORCE:
 870                         /* Startup bias, slow VMID ramp & buffer */
 871                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 872                                             WM8994_BIAS_SRC |
 873                                             WM8994_VMID_DISCH |
 874                                             WM8994_STARTUP_BIAS_ENA |
 875                                             WM8994_VMID_BUF_ENA |
 876                                             WM8994_VMID_RAMP_MASK,
 877                                             WM8994_BIAS_SRC |
 878                                             WM8994_STARTUP_BIAS_ENA |
 879                                             WM8994_VMID_BUF_ENA |
 880                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
 881
 882                         /* Main bias enable, VMID=2x40k */
 883                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 884                                             WM8994_BIAS_ENA |
 885                                             WM8994_VMID_SEL_MASK,
 886                                             WM8994_BIAS_ENA | 0x2);
 887
 888                         msleep(400);
 889
 890                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 891                                             WM8994_VMID_RAMP_MASK |
 892                                             WM8994_BIAS_SRC,
 893                                             0);
 894                         break;
 895                 }
 896         }
 897 }
 898
 899 static void vmid_dereference(struct snd_soc_codec *codec)
 900 {
 901         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 902
 903         wm8994->vmid_refcount--;
 904
 905         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
 906                 wm8994->vmid_refcount);
 907
 908         if (wm8994->vmid_refcount == 0) {
 909                 if (wm8994->hubs.lineout1_se)
 910                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 911                                             WM8994_LINEOUT1N_ENA |
 912                                             WM8994_LINEOUT1P_ENA,
 913                                             WM8994_LINEOUT1N_ENA |
 914                                             WM8994_LINEOUT1P_ENA);
 915
 916                 if (wm8994->hubs.lineout2_se)
 917                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 918                                             WM8994_LINEOUT2N_ENA |
 919                                             WM8994_LINEOUT2P_ENA,
 920                                             WM8994_LINEOUT2N_ENA |
 921                                             WM8994_LINEOUT2P_ENA);
 922
 923                 /* Start discharging VMID */
 924                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 925                                     WM8994_BIAS_SRC |
 926                                     WM8994_VMID_DISCH,
 927                                     WM8994_BIAS_SRC |
 928                                     WM8994_VMID_DISCH);
 929
 930                 switch (wm8994->vmid_mode) {
 931                 case WM8994_VMID_FORCE:
 932                         msleep(350);
 933                         break;
 934                 default:
 935                         break;
 936                 }
 937
 938                 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
 939                                     WM8994_VROI, WM8994_VROI);
 940
 941                 /* Active discharge */
 942                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 943                                     WM8994_LINEOUT1_DISCH |
 944                                     WM8994_LINEOUT2_DISCH,
 945                                     WM8994_LINEOUT1_DISCH |
 946                                     WM8994_LINEOUT2_DISCH);
 947
 948                 msleep(150);
 949
 950                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 951                                     WM8994_LINEOUT1N_ENA |
 952                                     WM8994_LINEOUT1P_ENA |
 953                                     WM8994_LINEOUT2N_ENA |
 954                                     WM8994_LINEOUT2P_ENA, 0);
 955
 956                 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
 957                                     WM8994_VROI, 0);
 958
 959                 /* Switch off startup biases */
 960                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 961                                     WM8994_BIAS_SRC |
 962                                     WM8994_STARTUP_BIAS_ENA |
 963                                     WM8994_VMID_BUF_ENA |
 964                                     WM8994_VMID_RAMP_MASK, 0);
 965
 966                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 967                                     WM8994_BIAS_ENA | WM8994_VMID_SEL_MASK, 0);
 968
 969                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 970                                     WM8994_VMID_RAMP_MASK, 0);
 971         }
 972
 973         pm_runtime_put(codec->dev);
 974 }
 975
 976 static int vmid_event(struct snd_soc_dapm_widget *w,
 977                       struct snd_kcontrol *kcontrol, int event)
 978 {
 979         struct snd_soc_codec *codec = w->codec;
 980
 981         switch (event) {
 982         case SND_SOC_DAPM_PRE_PMU:
 983                 vmid_reference(codec);
 984                 break;
 985
 986         case SND_SOC_DAPM_POST_PMD:
 987                 vmid_dereference(codec);
 988                 break;
 989         }
 990
 991         return 0;
 992 }
 993
 994 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
 995 {
 996         int source = 0;  /* GCC flow analysis can't track enable */
 997         int reg, reg_r;
 998
 999         /* We also need the same AIF source for L/R and only one path */
1000         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1001         switch (reg) {
1002         case WM8994_AIF2DACL_TO_DAC1L:
1003                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1004                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1005                 break;
1006         case WM8994_AIF1DAC2L_TO_DAC1L:
1007                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1008                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1009                 break;
1010         case WM8994_AIF1DAC1L_TO_DAC1L:
1011                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1012                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1013                 break;
1014         default:
1015                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1016                 return false;
1017         }
1018
1019         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1020         if (reg_r != reg) {
1021                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1022                 return false;
1023         }
1024
1025         /* Set the source up */
1026         snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1027                             WM8994_CP_DYN_SRC_SEL_MASK, source);
1028
1029         return true;
1030 }
1031
1032 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1033                       struct snd_kcontrol *kcontrol, int event)
1034 {
1035         struct snd_soc_codec *codec = w->codec;
1036         struct wm8994 *control = codec->control_data;
1037         int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1038         int i;
1039         int dac;
1040         int adc;
1041         int val;
1042
1043         switch (control->type) {
1044         case WM8994:
1045         case WM8958:
1046                 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1047                 break;
1048         default:
1049                 break;
1050         }
1051
1052         switch (event) {
1053         case SND_SOC_DAPM_PRE_PMU:
1054                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1055                 if ((val & WM8994_AIF1ADCL_SRC) &&
1056                     (val & WM8994_AIF1ADCR_SRC))
1057                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1058                 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1059                          !(val & WM8994_AIF1ADCR_SRC))
1060                         adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1061                 else
1062                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1063                                 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1064
1065                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1066                 if ((val & WM8994_AIF1DACL_SRC) &&
1067                     (val & WM8994_AIF1DACR_SRC))
1068                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1069                 else if (!(val & WM8994_AIF1DACL_SRC) &&
1070                          !(val & WM8994_AIF1DACR_SRC))
1071                         dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1072                 else
1073                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1074                                 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1075
1076                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1077                                     mask, adc);
1078                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1079                                     mask, dac);
1080                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1081                                     WM8994_AIF1DSPCLK_ENA |
1082                                     WM8994_SYSDSPCLK_ENA,
1083                                     WM8994_AIF1DSPCLK_ENA |
1084                                     WM8994_SYSDSPCLK_ENA);
1085                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1086                                     WM8994_AIF1ADC1R_ENA |
1087                                     WM8994_AIF1ADC1L_ENA |
1088                                     WM8994_AIF1ADC2R_ENA |
1089                                     WM8994_AIF1ADC2L_ENA);
1090                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1091                                     WM8994_AIF1DAC1R_ENA |
1092                                     WM8994_AIF1DAC1L_ENA |
1093                                     WM8994_AIF1DAC2R_ENA |
1094                                     WM8994_AIF1DAC2L_ENA);
1095                 break;
1096
1097         case SND_SOC_DAPM_POST_PMU:
1098                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1099                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1100                                       snd_soc_read(codec,
1101                                                    wm8994_vu_bits[i].reg));
1102                 break;
1103
1104         case SND_SOC_DAPM_PRE_PMD:
1105         case SND_SOC_DAPM_POST_PMD:
1106                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1107                                     mask, 0);
1108                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1109                                     mask, 0);
1110
1111                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1112                 if (val & WM8994_AIF2DSPCLK_ENA)
1113                         val = WM8994_SYSDSPCLK_ENA;
1114                 else
1115                         val = 0;
1116                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1117                                     WM8994_SYSDSPCLK_ENA |
1118                                     WM8994_AIF1DSPCLK_ENA, val);
1119                 break;
1120         }
1121
1122         return 0;
1123 }
1124
1125 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1126                       struct snd_kcontrol *kcontrol, int event)
1127 {
1128         struct snd_soc_codec *codec = w->codec;
1129         int i;
1130         int dac;
1131         int adc;
1132         int val;
1133
1134         switch (event) {
1135         case SND_SOC_DAPM_PRE_PMU:
1136                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1137                 if ((val & WM8994_AIF2ADCL_SRC) &&
1138                     (val & WM8994_AIF2ADCR_SRC))
1139                         adc = WM8994_AIF2ADCR_ENA;
1140                 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1141                          !(val & WM8994_AIF2ADCR_SRC))
1142                         adc = WM8994_AIF2ADCL_ENA;
1143                 else
1144                         adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1145
1146
1147                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1148                 if ((val & WM8994_AIF2DACL_SRC) &&
1149                     (val & WM8994_AIF2DACR_SRC))
1150                         dac = WM8994_AIF2DACR_ENA;
1151                 else if (!(val & WM8994_AIF2DACL_SRC) &&
1152                          !(val & WM8994_AIF2DACR_SRC))
1153                         dac = WM8994_AIF2DACL_ENA;
1154                 else
1155                         dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1156
1157                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1158                                     WM8994_AIF2ADCL_ENA |
1159                                     WM8994_AIF2ADCR_ENA, adc);
1160                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1161                                     WM8994_AIF2DACL_ENA |
1162                                     WM8994_AIF2DACR_ENA, dac);
1163                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1164                                     WM8994_AIF2DSPCLK_ENA |
1165                                     WM8994_SYSDSPCLK_ENA,
1166                                     WM8994_AIF2DSPCLK_ENA |
1167                                     WM8994_SYSDSPCLK_ENA);
1168                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1169                                     WM8994_AIF2ADCL_ENA |
1170                                     WM8994_AIF2ADCR_ENA,
1171                                     WM8994_AIF2ADCL_ENA |
1172                                     WM8994_AIF2ADCR_ENA);
1173                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1174                                     WM8994_AIF2DACL_ENA |
1175                                     WM8994_AIF2DACR_ENA,
1176                                     WM8994_AIF2DACL_ENA |
1177                                     WM8994_AIF2DACR_ENA);
1178                 break;
1179
1180         case SND_SOC_DAPM_POST_PMU:
1181                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1182                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1183                                       snd_soc_read(codec,
1184                                                    wm8994_vu_bits[i].reg));
1185                 break;
1186
1187         case SND_SOC_DAPM_PRE_PMD:
1188         case SND_SOC_DAPM_POST_PMD:
1189                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1190                                     WM8994_AIF2DACL_ENA |
1191                                     WM8994_AIF2DACR_ENA, 0);
1192                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1193                                     WM8994_AIF2ADCL_ENA |
1194                                     WM8994_AIF2ADCR_ENA, 0);
1195
1196                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1197                 if (val & WM8994_AIF1DSPCLK_ENA)
1198                         val = WM8994_SYSDSPCLK_ENA;
1199                 else
1200                         val = 0;
1201                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1202                                     WM8994_SYSDSPCLK_ENA |
1203                                     WM8994_AIF2DSPCLK_ENA, val);
1204                 break;
1205         }
1206
1207         return 0;
1208 }
1209
1210 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1211                            struct snd_kcontrol *kcontrol, int event)
1212 {
1213         struct snd_soc_codec *codec = w->codec;
1214         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1215
1216         switch (event) {
1217         case SND_SOC_DAPM_PRE_PMU:
1218                 wm8994->aif1clk_enable = 1;
1219                 break;
1220         case SND_SOC_DAPM_POST_PMD:
1221                 wm8994->aif1clk_disable = 1;
1222                 break;
1223         }
1224
1225         return 0;
1226 }
1227
1228 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1229                            struct snd_kcontrol *kcontrol, int event)
1230 {
1231         struct snd_soc_codec *codec = w->codec;
1232         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1233
1234         switch (event) {
1235         case SND_SOC_DAPM_PRE_PMU:
1236                 wm8994->aif2clk_enable = 1;
1237                 break;
1238         case SND_SOC_DAPM_POST_PMD:
1239                 wm8994->aif2clk_disable = 1;
1240                 break;
1241         }
1242
1243         return 0;
1244 }
1245
1246 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1247                           struct snd_kcontrol *kcontrol, int event)
1248 {
1249         struct snd_soc_codec *codec = w->codec;
1250         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1251
1252         switch (event) {
1253         case SND_SOC_DAPM_PRE_PMU:
1254                 if (wm8994->aif1clk_enable) {
1255                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1256                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1257                                             WM8994_AIF1CLK_ENA_MASK,
1258                                             WM8994_AIF1CLK_ENA);
1259                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1260                         wm8994->aif1clk_enable = 0;
1261                 }
1262                 if (wm8994->aif2clk_enable) {
1263                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1264                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1265                                             WM8994_AIF2CLK_ENA_MASK,
1266                                             WM8994_AIF2CLK_ENA);
1267                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1268                         wm8994->aif2clk_enable = 0;
1269                 }
1270                 break;
1271         }
1272
1273         /* We may also have postponed startup of DSP, handle that. */
1274         wm8958_aif_ev(w, kcontrol, event);
1275
1276         return 0;
1277 }
1278
1279 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1280                            struct snd_kcontrol *kcontrol, int event)
1281 {
1282         struct snd_soc_codec *codec = w->codec;
1283         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1284
1285         switch (event) {
1286         case SND_SOC_DAPM_POST_PMD:
1287                 if (wm8994->aif1clk_disable) {
1288                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1289                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1290                                             WM8994_AIF1CLK_ENA_MASK, 0);
1291                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1292                         wm8994->aif1clk_disable = 0;
1293                 }
1294                 if (wm8994->aif2clk_disable) {
1295                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1296                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1297                                             WM8994_AIF2CLK_ENA_MASK, 0);
1298                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1299                         wm8994->aif2clk_disable = 0;
1300                 }
1301                 break;
1302         }
1303
1304         return 0;
1305 }
1306
1307 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1308                       struct snd_kcontrol *kcontrol, int event)
1309 {
1310         late_enable_ev(w, kcontrol, event);
1311         return 0;
1312 }
1313
1314 static int micbias_ev(struct snd_soc_dapm_widget *w,
1315                       struct snd_kcontrol *kcontrol, int event)
1316 {
1317         late_enable_ev(w, kcontrol, event);
1318         return 0;
1319 }
1320
1321 static int dac_ev(struct snd_soc_dapm_widget *w,
1322                   struct snd_kcontrol *kcontrol, int event)
1323 {
1324         struct snd_soc_codec *codec = w->codec;
1325         unsigned int mask = 1 << w->shift;
1326
1327         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1328                             mask, mask);
1329         return 0;
1330 }
1331
1332 static const char *adc_mux_text[] = {
1333         "ADC",
1334         "DMIC",
1335 };
1336
1337 static const struct soc_enum adc_enum =
1338         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1339
1340 static const struct snd_kcontrol_new adcl_mux =
1341         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1342
1343 static const struct snd_kcontrol_new adcr_mux =
1344         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1345
1346 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1347 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1348 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1349 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1350 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1351 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1352 };
1353
1354 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1355 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1356 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1357 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1358 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1359 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1360 };
1361
1362 /* Debugging; dump chip status after DAPM transitions */
1363 static int post_ev(struct snd_soc_dapm_widget *w,
1364             struct snd_kcontrol *kcontrol, int event)
1365 {
1366         struct snd_soc_codec *codec = w->codec;
1367         dev_dbg(codec->dev, "SRC status: %x\n",
1368                 snd_soc_read(codec,
1369                              WM8994_RATE_STATUS));
1370         return 0;
1371 }
1372
1373 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1374 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1375                 1, 1, 0),
1376 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1377                 0, 1, 0),
1378 };
1379
1380 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1381 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1382                 1, 1, 0),
1383 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1384                 0, 1, 0),
1385 };
1386
1387 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1388 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1389                 1, 1, 0),
1390 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1391                 0, 1, 0),
1392 };
1393
1394 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1395 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1396                 1, 1, 0),
1397 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1398                 0, 1, 0),
1399 };
1400
1401 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1402 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1403                 5, 1, 0),
1404 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1405                 4, 1, 0),
1406 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1407                 2, 1, 0),
1408 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1409                 1, 1, 0),
1410 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1411                 0, 1, 0),
1412 };
1413
1414 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1415 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1416                 5, 1, 0),
1417 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1418                 4, 1, 0),
1419 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1420                 2, 1, 0),
1421 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1422                 1, 1, 0),
1423 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1424                 0, 1, 0),
1425 };
1426
1427 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1428 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1429         .info = snd_soc_info_volsw, \
1430         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1431         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1432
1433 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1434                               struct snd_ctl_elem_value *ucontrol)
1435 {
1436         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1437         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1438         struct snd_soc_codec *codec = w->codec;
1439         int ret;
1440
1441         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1442
1443         wm_hubs_update_class_w(codec);
1444
1445         return ret;
1446 }
1447
1448 static const struct snd_kcontrol_new dac1l_mix[] = {
1449 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1450                       5, 1, 0),
1451 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1452                       4, 1, 0),
1453 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1454                       2, 1, 0),
1455 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1456                       1, 1, 0),
1457 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1458                       0, 1, 0),
1459 };
1460
1461 static const struct snd_kcontrol_new dac1r_mix[] = {
1462 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1463                       5, 1, 0),
1464 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1465                       4, 1, 0),
1466 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1467                       2, 1, 0),
1468 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1469                       1, 1, 0),
1470 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1471                       0, 1, 0),
1472 };
1473
1474 static const char *sidetone_text[] = {
1475         "ADC/DMIC1", "DMIC2",
1476 };
1477
1478 static const struct soc_enum sidetone1_enum =
1479         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1480
1481 static const struct snd_kcontrol_new sidetone1_mux =
1482         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1483
1484 static const struct soc_enum sidetone2_enum =
1485         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1486
1487 static const struct snd_kcontrol_new sidetone2_mux =
1488         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1489
1490 static const char *aif1dac_text[] = {
1491         "AIF1DACDAT", "AIF3DACDAT",
1492 };
1493
1494 static const struct soc_enum aif1dac_enum =
1495         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1496
1497 static const struct snd_kcontrol_new aif1dac_mux =
1498         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1499
1500 static const char *aif2dac_text[] = {
1501         "AIF2DACDAT", "AIF3DACDAT",
1502 };
1503
1504 static const struct soc_enum aif2dac_enum =
1505         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1506
1507 static const struct snd_kcontrol_new aif2dac_mux =
1508         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1509
1510 static const char *aif2adc_text[] = {
1511         "AIF2ADCDAT", "AIF3DACDAT",
1512 };
1513
1514 static const struct soc_enum aif2adc_enum =
1515         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1516
1517 static const struct snd_kcontrol_new aif2adc_mux =
1518         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1519
1520 static const char *aif3adc_text[] = {
1521         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1522 };
1523
1524 static const struct soc_enum wm8994_aif3adc_enum =
1525         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1526
1527 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1528         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1529
1530 static const struct soc_enum wm8958_aif3adc_enum =
1531         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1532
1533 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1534         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1535
1536 static const char *mono_pcm_out_text[] = {
1537         "None", "AIF2ADCL", "AIF2ADCR",
1538 };
1539
1540 static const struct soc_enum mono_pcm_out_enum =
1541         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1542
1543 static const struct snd_kcontrol_new mono_pcm_out_mux =
1544         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1545
1546 static const char *aif2dac_src_text[] = {
1547         "AIF2", "AIF3",
1548 };
1549
1550 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1551 static const struct soc_enum aif2dacl_src_enum =
1552         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1553
1554 static const struct snd_kcontrol_new aif2dacl_src_mux =
1555         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1556
1557 static const struct soc_enum aif2dacr_src_enum =
1558         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1559
1560 static const struct snd_kcontrol_new aif2dacr_src_mux =
1561         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1562
1563 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1564 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1565         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1566 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1567         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1568
1569 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1570         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1571 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1572         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1573 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1574         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1575 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1576         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1577 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1578         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1579
1580 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1581                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1582                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1583 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1584                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1585                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1586 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1587                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1588 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1589                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1590
1591 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1592 };
1593
1594 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1595 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1596                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1597                     SND_SOC_DAPM_PRE_PMD),
1598 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1599                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1600                     SND_SOC_DAPM_PRE_PMD),
1601 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1602 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1603                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1604 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1605                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1606 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1607 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1608 };
1609
1610 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1611 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1612         dac_ev, SND_SOC_DAPM_PRE_PMU),
1613 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1614         dac_ev, SND_SOC_DAPM_PRE_PMU),
1615 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1616         dac_ev, SND_SOC_DAPM_PRE_PMU),
1617 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1618         dac_ev, SND_SOC_DAPM_PRE_PMU),
1619 };
1620
1621 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1622 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1623 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1624 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1625 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1626 };
1627
1628 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1629 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1630                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1631 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1632                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1633 };
1634
1635 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1636 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1637 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1638 };
1639
1640 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1641 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1642 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1643 SND_SOC_DAPM_INPUT("Clock"),
1644
1645 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1646                       SND_SOC_DAPM_PRE_PMU),
1647 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1648                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1649
1650 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1651                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1652                     SND_SOC_DAPM_PRE_PMD),
1653
1654 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1655 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1656 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1657
1658 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1659                      0, SND_SOC_NOPM, 9, 0),
1660 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1661                      0, SND_SOC_NOPM, 8, 0),
1662 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1663                       SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1664                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1665 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1666                       SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1667                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1668
1669 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1670                      0, SND_SOC_NOPM, 11, 0),
1671 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1672                      0, SND_SOC_NOPM, 10, 0),
1673 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1674                       SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1675                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1676 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1677                       SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1678                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1679
1680 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1681                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1682 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1683                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1684
1685 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1686                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1687 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1688                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1689
1690 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1691                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1692 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1693                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1694
1695 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1696 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1697
1698 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1699                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1700 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1701                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1702
1703 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1704                      SND_SOC_NOPM, 13, 0),
1705 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1706                      SND_SOC_NOPM, 12, 0),
1707 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1708                       SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1709                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1710 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1711                       SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1712                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1713
1714 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1715 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1716 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1717 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT",  NULL, 0, SND_SOC_NOPM, 0, 0),
1718
1719 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1720 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1721 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1722
1723 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1724 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1725
1726 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1727
1728 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1729 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1730 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1731 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1732
1733 /* Power is done with the muxes since the ADC power also controls the
1734  * downsampling chain, the chip will automatically manage the analogue
1735  * specific portions.
1736  */
1737 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1738 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1739
1740 SND_SOC_DAPM_POST("Debug log", post_ev),
1741 };
1742
1743 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1744 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1745 };
1746
1747 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1748 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1749 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1750 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1751 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1752 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1753 };
1754
1755 static const struct snd_soc_dapm_route intercon[] = {
1756         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1757         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1758
1759         { "DSP1CLK", NULL, "CLK_SYS" },
1760         { "DSP2CLK", NULL, "CLK_SYS" },
1761         { "DSPINTCLK", NULL, "CLK_SYS" },
1762
1763         { "AIF1ADC1L", NULL, "AIF1CLK" },
1764         { "AIF1ADC1L", NULL, "DSP1CLK" },
1765         { "AIF1ADC1R", NULL, "AIF1CLK" },
1766         { "AIF1ADC1R", NULL, "DSP1CLK" },
1767         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1768
1769         { "AIF1DAC1L", NULL, "AIF1CLK" },
1770         { "AIF1DAC1L", NULL, "DSP1CLK" },
1771         { "AIF1DAC1R", NULL, "AIF1CLK" },
1772         { "AIF1DAC1R", NULL, "DSP1CLK" },
1773         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1774
1775         { "AIF1ADC2L", NULL, "AIF1CLK" },
1776         { "AIF1ADC2L", NULL, "DSP1CLK" },
1777         { "AIF1ADC2R", NULL, "AIF1CLK" },
1778         { "AIF1ADC2R", NULL, "DSP1CLK" },
1779         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1780
1781         { "AIF1DAC2L", NULL, "AIF1CLK" },
1782         { "AIF1DAC2L", NULL, "DSP1CLK" },
1783         { "AIF1DAC2R", NULL, "AIF1CLK" },
1784         { "AIF1DAC2R", NULL, "DSP1CLK" },
1785         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1786
1787         { "AIF2ADCL", NULL, "AIF2CLK" },
1788         { "AIF2ADCL", NULL, "DSP2CLK" },
1789         { "AIF2ADCR", NULL, "AIF2CLK" },
1790         { "AIF2ADCR", NULL, "DSP2CLK" },
1791         { "AIF2ADCR", NULL, "DSPINTCLK" },
1792
1793         { "AIF2DACL", NULL, "AIF2CLK" },
1794         { "AIF2DACL", NULL, "DSP2CLK" },
1795         { "AIF2DACR", NULL, "AIF2CLK" },
1796         { "AIF2DACR", NULL, "DSP2CLK" },
1797         { "AIF2DACR", NULL, "DSPINTCLK" },
1798
1799         { "DMIC1L", NULL, "DMIC1DAT" },
1800         { "DMIC1L", NULL, "CLK_SYS" },
1801         { "DMIC1R", NULL, "DMIC1DAT" },
1802         { "DMIC1R", NULL, "CLK_SYS" },
1803         { "DMIC2L", NULL, "DMIC2DAT" },
1804         { "DMIC2L", NULL, "CLK_SYS" },
1805         { "DMIC2R", NULL, "DMIC2DAT" },
1806         { "DMIC2R", NULL, "CLK_SYS" },
1807
1808         { "ADCL", NULL, "AIF1CLK" },
1809         { "ADCL", NULL, "DSP1CLK" },
1810         { "ADCL", NULL, "DSPINTCLK" },
1811
1812         { "ADCR", NULL, "AIF1CLK" },
1813         { "ADCR", NULL, "DSP1CLK" },
1814         { "ADCR", NULL, "DSPINTCLK" },
1815
1816         { "ADCL Mux", "ADC", "ADCL" },
1817         { "ADCL Mux", "DMIC", "DMIC1L" },
1818         { "ADCR Mux", "ADC", "ADCR" },
1819         { "ADCR Mux", "DMIC", "DMIC1R" },
1820
1821         { "DAC1L", NULL, "AIF1CLK" },
1822         { "DAC1L", NULL, "DSP1CLK" },
1823         { "DAC1L", NULL, "DSPINTCLK" },
1824
1825         { "DAC1R", NULL, "AIF1CLK" },
1826         { "DAC1R", NULL, "DSP1CLK" },
1827         { "DAC1R", NULL, "DSPINTCLK" },
1828
1829         { "DAC2L", NULL, "AIF2CLK" },
1830         { "DAC2L", NULL, "DSP2CLK" },
1831         { "DAC2L", NULL, "DSPINTCLK" },
1832
1833         { "DAC2R", NULL, "AIF2DACR" },
1834         { "DAC2R", NULL, "AIF2CLK" },
1835         { "DAC2R", NULL, "DSP2CLK" },
1836         { "DAC2R", NULL, "DSPINTCLK" },
1837
1838         { "TOCLK", NULL, "CLK_SYS" },
1839
1840         { "AIF1DACDAT", NULL, "AIF1 Playback" },
1841         { "AIF2DACDAT", NULL, "AIF2 Playback" },
1842         { "AIF3DACDAT", NULL, "AIF3 Playback" },
1843
1844         { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1845         { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1846         { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1847
1848         /* AIF1 outputs */
1849         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1850         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1851         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1852
1853         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1854         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1855         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1856
1857         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1858         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1859         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1860
1861         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1862         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1863         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1864
1865         /* Pin level routing for AIF3 */
1866         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1867         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1868         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1869         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1870
1871         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1872         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1873         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1874         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1875         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1876         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1877         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1878
1879         /* DAC1 inputs */
1880         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1881         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1882         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1883         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1884         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1885
1886         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1887         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1888         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1889         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1890         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1891
1892         /* DAC2/AIF2 outputs  */
1893         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1894         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1895         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1896         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1897         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1898         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1899
1900         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1901         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1902         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1903         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1904         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1905         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1906
1907         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1908         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1909         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1910         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1911
1912         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1913
1914         /* AIF3 output */
1915         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1916         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1917         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1918         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1919         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1920         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1921         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1922         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1923
1924         /* Sidetone */
1925         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1926         { "Left Sidetone", "DMIC2", "DMIC2L" },
1927         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1928         { "Right Sidetone", "DMIC2", "DMIC2R" },
1929
1930         /* Output stages */
1931         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1932         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1933
1934         { "SPKL", "DAC1 Switch", "DAC1L" },
1935         { "SPKL", "DAC2 Switch", "DAC2L" },
1936
1937         { "SPKR", "DAC1 Switch", "DAC1R" },
1938         { "SPKR", "DAC2 Switch", "DAC2R" },
1939
1940         { "Left Headphone Mux", "DAC", "DAC1L" },
1941         { "Right Headphone Mux", "DAC", "DAC1R" },
1942 };
1943
1944 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1945         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1946         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1947         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1948         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1949         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1950         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1951         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1952         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1953 };
1954
1955 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1956         { "DAC1L", NULL, "DAC1L Mixer" },
1957         { "DAC1R", NULL, "DAC1R Mixer" },
1958         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1959         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1960 };
1961
1962 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1963         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1964         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1965         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1966         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1967         { "MICBIAS1", NULL, "CLK_SYS" },
1968         { "MICBIAS1", NULL, "MICBIAS Supply" },
1969         { "MICBIAS2", NULL, "CLK_SYS" },
1970         { "MICBIAS2", NULL, "MICBIAS Supply" },
1971 };
1972
1973 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1974         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1975         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1976         { "MICBIAS1", NULL, "VMID" },
1977         { "MICBIAS2", NULL, "VMID" },
1978 };
1979
1980 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1981         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1982         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1983
1984         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1985         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1986         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1987         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1988
1989         { "AIF3DACDAT", NULL, "AIF3" },
1990         { "AIF3ADCDAT", NULL, "AIF3" },
1991
1992         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1993         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1994
1995         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1996 };
1997
1998 /* The size in bits of the FLL divide multiplied by 10
1999  * to allow rounding later */
2000 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2001
2002 struct fll_div {
2003         u16 outdiv;
2004         u16 n;
2005         u16 k;
2006         u16 clk_ref_div;
2007         u16 fll_fratio;
2008 };
2009
2010 static int wm8994_get_fll_config(struct fll_div *fll,
2011                                  int freq_in, int freq_out)
2012 {
2013         u64 Kpart;
2014         unsigned int K, Ndiv, Nmod;
2015
2016         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2017
2018         /* Scale the input frequency down to <= 13.5MHz */
2019         fll->clk_ref_div = 0;
2020         while (freq_in > 13500000) {
2021                 fll->clk_ref_div++;
2022                 freq_in /= 2;
2023
2024                 if (fll->clk_ref_div > 3)
2025                         return -EINVAL;
2026         }
2027         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2028
2029         /* Scale the output to give 90MHz<=Fvco<=100MHz */
2030         fll->outdiv = 3;
2031         while (freq_out * (fll->outdiv + 1) < 90000000) {
2032                 fll->outdiv++;
2033                 if (fll->outdiv > 63)
2034                         return -EINVAL;
2035         }
2036         freq_out *= fll->outdiv + 1;
2037         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2038
2039         if (freq_in > 1000000) {
2040                 fll->fll_fratio = 0;
2041         } else if (freq_in > 256000) {
2042                 fll->fll_fratio = 1;
2043                 freq_in *= 2;
2044         } else if (freq_in > 128000) {
2045                 fll->fll_fratio = 2;
2046                 freq_in *= 4;
2047         } else if (freq_in > 64000) {
2048                 fll->fll_fratio = 3;
2049                 freq_in *= 8;
2050         } else {
2051                 fll->fll_fratio = 4;
2052                 freq_in *= 16;
2053         }
2054         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2055
2056         /* Now, calculate N.K */
2057         Ndiv = freq_out / freq_in;
2058
2059         fll->n = Ndiv;
2060         Nmod = freq_out % freq_in;
2061         pr_debug("Nmod=%d\n", Nmod);
2062
2063         /* Calculate fractional part - scale up so we can round. */
2064         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2065
2066         do_div(Kpart, freq_in);
2067
2068         K = Kpart & 0xFFFFFFFF;
2069
2070         if ((K % 10) >= 5)
2071                 K += 5;
2072
2073         /* Move down to proper range now rounding is done */
2074         fll->k = K / 10;
2075
2076         pr_debug("N=%x K=%x\n", fll->n, fll->k);
2077
2078         return 0;
2079 }
2080
2081 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2082                           unsigned int freq_in, unsigned int freq_out)
2083 {
2084         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2085         struct wm8994 *control = wm8994->wm8994;
2086         int reg_offset, ret;
2087         struct fll_div fll;
2088         u16 reg, clk1, aif_reg, aif_src;
2089         unsigned long timeout;
2090         bool was_enabled;
2091
2092         switch (id) {
2093         case WM8994_FLL1:
2094                 reg_offset = 0;
2095                 id = 0;
2096                 aif_src = 0x10;
2097                 break;
2098         case WM8994_FLL2:
2099                 reg_offset = 0x20;
2100                 id = 1;
2101                 aif_src = 0x18;
2102                 break;
2103         default:
2104                 return -EINVAL;
2105         }
2106
2107         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2108         was_enabled = reg & WM8994_FLL1_ENA;
2109
2110         switch (src) {
2111         case 0:
2112                 /* Allow no source specification when stopping */
2113                 if (freq_out)
2114                         return -EINVAL;
2115                 src = wm8994->fll[id].src;
2116                 break;
2117         case WM8994_FLL_SRC_MCLK1:
2118         case WM8994_FLL_SRC_MCLK2:
2119         case WM8994_FLL_SRC_LRCLK:
2120         case WM8994_FLL_SRC_BCLK:
2121                 break;
2122         case WM8994_FLL_SRC_INTERNAL:
2123                 freq_in = 12000000;
2124                 freq_out = 12000000;
2125                 break;
2126         default:
2127                 return -EINVAL;
2128         }
2129
2130         /* Are we changing anything? */
2131         if (wm8994->fll[id].src == src &&
2132             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2133                 return 0;
2134
2135         /* If we're stopping the FLL redo the old config - no
2136          * registers will actually be written but we avoid GCC flow
2137          * analysis bugs spewing warnings.
2138          */
2139         if (freq_out)
2140                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2141         else
2142                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2143                                             wm8994->fll[id].out);
2144         if (ret < 0)
2145                 return ret;
2146
2147         /* Make sure that we're not providing SYSCLK right now */
2148         clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2149         if (clk1 & WM8994_SYSCLK_SRC)
2150                 aif_reg = WM8994_AIF2_CLOCKING_1;
2151         else
2152                 aif_reg = WM8994_AIF1_CLOCKING_1;
2153         reg = snd_soc_read(codec, aif_reg);
2154
2155         if ((reg & WM8994_AIF1CLK_ENA) &&
2156             (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2157                 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2158                         id + 1);
2159                 return -EBUSY;
2160         }
2161
2162         /* We always need to disable the FLL while reconfiguring */
2163         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2164                             WM8994_FLL1_ENA, 0);
2165
2166         if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2167             freq_in == freq_out && freq_out) {
2168                 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2169                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2170                                     WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2171                 goto out;
2172         }
2173
2174         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2175                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2176         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2177                             WM8994_FLL1_OUTDIV_MASK |
2178                             WM8994_FLL1_FRATIO_MASK, reg);
2179
2180         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2181                             WM8994_FLL1_K_MASK, fll.k);
2182
2183         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2184                             WM8994_FLL1_N_MASK,
2185                                     fll.n << WM8994_FLL1_N_SHIFT);
2186
2187         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2188                             WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2189                             WM8994_FLL1_REFCLK_DIV_MASK |
2190                             WM8994_FLL1_REFCLK_SRC_MASK,
2191                             ((src == WM8994_FLL_SRC_INTERNAL)
2192                              << WM8994_FLL1_FRC_NCO_SHIFT) |
2193                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2194                             (src - 1));
2195
2196         /* Clear any pending completion from a previous failure */
2197         try_wait_for_completion(&wm8994->fll_locked[id]);
2198
2199         /* Enable (with fractional mode if required) */
2200         if (freq_out) {
2201                 /* Enable VMID if we need it */
2202                 if (!was_enabled) {
2203                         active_reference(codec);
2204
2205                         switch (control->type) {
2206                         case WM8994:
2207                                 vmid_reference(codec);
2208                                 break;
2209                         case WM8958:
2210                                 if (wm8994->revision < 1)
2211                                         vmid_reference(codec);
2212                                 break;
2213                         default:
2214                                 break;
2215                         }
2216                 }
2217
2218                 reg = WM8994_FLL1_ENA;
2219
2220                 if (fll.k)
2221                         reg |= WM8994_FLL1_FRAC;
2222                 if (src == WM8994_FLL_SRC_INTERNAL)
2223                         reg |= WM8994_FLL1_OSC_ENA;
2224
2225                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2226                                     WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2227                                     WM8994_FLL1_FRAC, reg);
2228
2229                 if (wm8994->fll_locked_irq) {
2230                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2231                                                               msecs_to_jiffies(10));
2232                         if (timeout == 0)
2233                                 dev_warn(codec->dev,
2234                                          "Timed out waiting for FLL lock\n");
2235                 } else {
2236                         msleep(5);
2237                 }
2238         } else {
2239                 if (was_enabled) {
2240                         switch (control->type) {
2241                         case WM8994:
2242                                 vmid_dereference(codec);
2243                                 break;
2244                         case WM8958:
2245                                 if (wm8994->revision < 1)
2246                                         vmid_dereference(codec);
2247                                 break;
2248                         default:
2249                                 break;
2250                         }
2251
2252                         active_dereference(codec);
2253                 }
2254         }
2255
2256 out:
2257         wm8994->fll[id].in = freq_in;
2258         wm8994->fll[id].out = freq_out;
2259         wm8994->fll[id].src = src;
2260
2261         configure_clock(codec);
2262
2263         return 0;
2264 }
2265
2266 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2267 {
2268         struct completion *completion = data;
2269
2270         complete(completion);
2271
2272         return IRQ_HANDLED;
2273 }
2274
2275 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2276
2277 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2278                           unsigned int freq_in, unsigned int freq_out)
2279 {
2280         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2281 }
2282
2283 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2284                 int clk_id, unsigned int freq, int dir)
2285 {
2286         struct snd_soc_codec *codec = dai->codec;
2287         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2288         int i;
2289
2290         switch (dai->id) {
2291         case 1:
2292         case 2:
2293                 break;
2294
2295         default:
2296                 /* AIF3 shares clocking with AIF1/2 */
2297                 return -EINVAL;
2298         }
2299
2300         switch (clk_id) {
2301         case WM8994_SYSCLK_MCLK1:
2302                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2303                 wm8994->mclk[0] = freq;
2304                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2305                         dai->id, freq);
2306                 break;
2307
2308         case WM8994_SYSCLK_MCLK2:
2309                 /* TODO: Set GPIO AF */
2310                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2311                 wm8994->mclk[1] = freq;
2312                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2313                         dai->id, freq);
2314                 break;
2315
2316         case WM8994_SYSCLK_FLL1:
2317                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2318                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2319                 break;
2320
2321         case WM8994_SYSCLK_FLL2:
2322                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2323                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2324                 break;
2325
2326         case WM8994_SYSCLK_OPCLK:
2327                 /* Special case - a division (times 10) is given and
2328                  * no effect on main clocking.
2329                  */
2330                 if (freq) {
2331                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2332                                 if (opclk_divs[i] == freq)
2333                                         break;
2334                         if (i == ARRAY_SIZE(opclk_divs))
2335                                 return -EINVAL;
2336                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2337                                             WM8994_OPCLK_DIV_MASK, i);
2338                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2339                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2340                 } else {
2341                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2342                                             WM8994_OPCLK_ENA, 0);
2343                 }
2344
2345         default:
2346                 return -EINVAL;
2347         }
2348
2349         configure_clock(codec);
2350
2351         return 0;
2352 }
2353
2354 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2355                                  enum snd_soc_bias_level level)
2356 {
2357         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2358         struct wm8994 *control = wm8994->wm8994;
2359
2360         wm_hubs_set_bias_level(codec, level);
2361
2362         switch (level) {
2363         case SND_SOC_BIAS_ON:
2364                 break;
2365
2366         case SND_SOC_BIAS_PREPARE:
2367                 /* MICBIAS into regulating mode */
2368                 switch (control->type) {
2369                 case WM8958:
2370                 case WM1811:
2371                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2372                                             WM8958_MICB1_MODE, 0);
2373                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2374                                             WM8958_MICB2_MODE, 0);
2375                         break;
2376                 default:
2377                         break;
2378                 }
2379
2380                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2381                         active_reference(codec);
2382                 break;
2383
2384         case SND_SOC_BIAS_STANDBY:
2385                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2386                         switch (control->type) {
2387                         case WM8958:
2388                                 if (wm8994->revision == 0) {
2389                                         /* Optimise performance for rev A */
2390                                         snd_soc_update_bits(codec,
2391                                                             WM8958_CHARGE_PUMP_2,
2392                                                             WM8958_CP_DISCH,
2393                                                             WM8958_CP_DISCH);
2394                                 }
2395                                 break;
2396
2397                         default:
2398                                 break;
2399                         }
2400
2401                         /* Discharge LINEOUT1 & 2 */
2402                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2403                                             WM8994_LINEOUT1_DISCH |
2404                                             WM8994_LINEOUT2_DISCH,
2405                                             WM8994_LINEOUT1_DISCH |
2406                                             WM8994_LINEOUT2_DISCH);
2407                 }
2408
2409                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2410                         active_dereference(codec);
2411
2412                 /* MICBIAS into bypass mode on newer devices */
2413                 switch (control->type) {
2414                 case WM8958:
2415                 case WM1811:
2416                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2417                                             WM8958_MICB1_MODE,
2418                                             WM8958_MICB1_MODE);
2419                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2420                                             WM8958_MICB2_MODE,
2421                                             WM8958_MICB2_MODE);
2422                         break;
2423                 default:
2424                         break;
2425                 }
2426                 break;
2427
2428         case SND_SOC_BIAS_OFF:
2429                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2430                         wm8994->cur_fw = NULL;
2431                 break;
2432         }
2433
2434         codec->dapm.bias_level = level;
2435
2436         return 0;
2437 }
2438
2439 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2440 {
2441         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2442
2443         switch (mode) {
2444         case WM8994_VMID_NORMAL:
2445                 if (wm8994->hubs.lineout1_se) {
2446                         snd_soc_dapm_disable_pin(&codec->dapm,
2447                                                  "LINEOUT1N Driver");
2448                         snd_soc_dapm_disable_pin(&codec->dapm,
2449                                                  "LINEOUT1P Driver");
2450                 }
2451                 if (wm8994->hubs.lineout2_se) {
2452                         snd_soc_dapm_disable_pin(&codec->dapm,
2453                                                  "LINEOUT2N Driver");
2454                         snd_soc_dapm_disable_pin(&codec->dapm,
2455                                                  "LINEOUT2P Driver");
2456                 }
2457
2458                 /* Do the sync with the old mode to allow it to clean up */
2459                 snd_soc_dapm_sync(&codec->dapm);
2460                 wm8994->vmid_mode = mode;
2461                 break;
2462
2463         case WM8994_VMID_FORCE:
2464                 if (wm8994->hubs.lineout1_se) {
2465                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2466                                                       "LINEOUT1N Driver");
2467                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2468                                                       "LINEOUT1P Driver");
2469                 }
2470                 if (wm8994->hubs.lineout2_se) {
2471                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2472                                                       "LINEOUT2N Driver");
2473                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2474                                                       "LINEOUT2P Driver");
2475                 }
2476
2477                 wm8994->vmid_mode = mode;
2478                 snd_soc_dapm_sync(&codec->dapm);
2479                 break;
2480
2481         default:
2482                 return -EINVAL;
2483         }
2484
2485         return 0;
2486 }
2487
2488 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2489 {
2490         struct snd_soc_codec *codec = dai->codec;
2491         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2492         struct wm8994 *control = wm8994->wm8994;
2493         int ms_reg;
2494         int aif1_reg;
2495         int ms = 0;
2496         int aif1 = 0;
2497
2498         switch (dai->id) {
2499         case 1:
2500                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2501                 aif1_reg = WM8994_AIF1_CONTROL_1;
2502                 break;
2503         case 2:
2504                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2505                 aif1_reg = WM8994_AIF2_CONTROL_1;
2506                 break;
2507         default:
2508                 return -EINVAL;
2509         }
2510
2511         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2512         case SND_SOC_DAIFMT_CBS_CFS:
2513                 break;
2514         case SND_SOC_DAIFMT_CBM_CFM:
2515                 ms = WM8994_AIF1_MSTR;
2516                 break;
2517         default:
2518                 return -EINVAL;
2519         }
2520
2521         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2522         case SND_SOC_DAIFMT_DSP_B:
2523                 aif1 |= WM8994_AIF1_LRCLK_INV;
2524         case SND_SOC_DAIFMT_DSP_A:
2525                 aif1 |= 0x18;
2526                 break;
2527         case SND_SOC_DAIFMT_I2S:
2528                 aif1 |= 0x10;
2529                 break;
2530         case SND_SOC_DAIFMT_RIGHT_J:
2531                 break;
2532         case SND_SOC_DAIFMT_LEFT_J:
2533                 aif1 |= 0x8;
2534                 break;
2535         default:
2536                 return -EINVAL;
2537         }
2538
2539         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2540         case SND_SOC_DAIFMT_DSP_A:
2541         case SND_SOC_DAIFMT_DSP_B:
2542                 /* frame inversion not valid for DSP modes */
2543                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2544                 case SND_SOC_DAIFMT_NB_NF:
2545                         break;
2546                 case SND_SOC_DAIFMT_IB_NF:
2547                         aif1 |= WM8994_AIF1_BCLK_INV;
2548                         break;
2549                 default:
2550                         return -EINVAL;
2551                 }
2552                 break;
2553
2554         case SND_SOC_DAIFMT_I2S:
2555         case SND_SOC_DAIFMT_RIGHT_J:
2556         case SND_SOC_DAIFMT_LEFT_J:
2557                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2558                 case SND_SOC_DAIFMT_NB_NF:
2559                         break;
2560                 case SND_SOC_DAIFMT_IB_IF:
2561                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2562                         break;
2563                 case SND_SOC_DAIFMT_IB_NF:
2564                         aif1 |= WM8994_AIF1_BCLK_INV;
2565                         break;
2566                 case SND_SOC_DAIFMT_NB_IF:
2567                         aif1 |= WM8994_AIF1_LRCLK_INV;
2568                         break;
2569                 default:
2570                         return -EINVAL;
2571                 }
2572                 break;
2573         default:
2574                 return -EINVAL;
2575         }
2576
2577         /* The AIF2 format configuration needs to be mirrored to AIF3
2578          * on WM8958 if it's in use so just do it all the time. */
2579         switch (control->type) {
2580         case WM1811:
2581         case WM8958:
2582                 if (dai->id == 2)
2583                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2584                                             WM8994_AIF1_LRCLK_INV |
2585                                             WM8958_AIF3_FMT_MASK, aif1);
2586                 break;
2587
2588         default:
2589                 break;
2590         }
2591
2592         snd_soc_update_bits(codec, aif1_reg,
2593                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2594                             WM8994_AIF1_FMT_MASK,
2595                             aif1);
2596         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2597                             ms);
2598
2599         return 0;
2600 }
2601
2602 static struct {
2603         int val, rate;
2604 } srs[] = {
2605         { 0,   8000 },
2606         { 1,  11025 },
2607         { 2,  12000 },
2608         { 3,  16000 },
2609         { 4,  22050 },
2610         { 5,  24000 },
2611         { 6,  32000 },
2612         { 7,  44100 },
2613         { 8,  48000 },
2614         { 9,  88200 },
2615         { 10, 96000 },
2616 };
2617
2618 static int fs_ratios[] = {
2619         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2620 };
2621
2622 static int bclk_divs[] = {
2623         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2624         640, 880, 960, 1280, 1760, 1920
2625 };
2626
2627 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2628                             struct snd_pcm_hw_params *params,
2629                             struct snd_soc_dai *dai)
2630 {
2631         struct snd_soc_codec *codec = dai->codec;
2632         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2633         int aif1_reg;
2634         int aif2_reg;
2635         int bclk_reg;
2636         int lrclk_reg;
2637         int rate_reg;
2638         int aif1 = 0;
2639         int aif2 = 0;
2640         int bclk = 0;
2641         int lrclk = 0;
2642         int rate_val = 0;
2643         int id = dai->id - 1;
2644
2645         int i, cur_val, best_val, bclk_rate, best;
2646
2647         switch (dai->id) {
2648         case 1:
2649                 aif1_reg = WM8994_AIF1_CONTROL_1;
2650                 aif2_reg = WM8994_AIF1_CONTROL_2;
2651                 bclk_reg = WM8994_AIF1_BCLK;
2652                 rate_reg = WM8994_AIF1_RATE;
2653                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2654                     wm8994->lrclk_shared[0]) {
2655                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2656                 } else {
2657                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2658                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2659                 }
2660                 break;
2661         case 2:
2662                 aif1_reg = WM8994_AIF2_CONTROL_1;
2663                 aif2_reg = WM8994_AIF2_CONTROL_2;
2664                 bclk_reg = WM8994_AIF2_BCLK;
2665                 rate_reg = WM8994_AIF2_RATE;
2666                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2667                     wm8994->lrclk_shared[1]) {
2668                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2669                 } else {
2670                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2671                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2672                 }
2673                 break;
2674         default:
2675                 return -EINVAL;
2676         }
2677
2678         bclk_rate = params_rate(params) * 4;
2679         switch (params_format(params)) {
2680         case SNDRV_PCM_FORMAT_S16_LE:
2681                 bclk_rate *= 16;
2682                 break;
2683         case SNDRV_PCM_FORMAT_S20_3LE:
2684                 bclk_rate *= 20;
2685                 aif1 |= 0x20;
2686                 break;
2687         case SNDRV_PCM_FORMAT_S24_LE:
2688                 bclk_rate *= 24;
2689                 aif1 |= 0x40;
2690                 break;
2691         case SNDRV_PCM_FORMAT_S32_LE:
2692                 bclk_rate *= 32;
2693                 aif1 |= 0x60;
2694                 break;
2695         default:
2696                 return -EINVAL;
2697         }
2698
2699         /* Try to find an appropriate sample rate; look for an exact match. */
2700         for (i = 0; i < ARRAY_SIZE(srs); i++)
2701                 if (srs[i].rate == params_rate(params))
2702                         break;
2703         if (i == ARRAY_SIZE(srs))
2704                 return -EINVAL;
2705         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2706
2707         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2708         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2709                 dai->id, wm8994->aifclk[id], bclk_rate);
2710
2711         if (params_channels(params) == 1 &&
2712             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2713                 aif2 |= WM8994_AIF1_MONO;
2714
2715         if (wm8994->aifclk[id] == 0) {
2716                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2717                 return -EINVAL;
2718         }
2719
2720         /* AIFCLK/fs ratio; look for a close match in either direction */
2721         best = 0;
2722         best_val = abs((fs_ratios[0] * params_rate(params))
2723                        - wm8994->aifclk[id]);
2724         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2725                 cur_val = abs((fs_ratios[i] * params_rate(params))
2726                               - wm8994->aifclk[id]);
2727                 if (cur_val >= best_val)
2728                         continue;
2729                 best = i;
2730                 best_val = cur_val;
2731         }
2732         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2733                 dai->id, fs_ratios[best]);
2734         rate_val |= best;
2735
2736         /* We may not get quite the right frequency if using
2737          * approximate clocks so look for the closest match that is
2738          * higher than the target (we need to ensure that there enough
2739          * BCLKs to clock out the samples).
2740          */
2741         best = 0;
2742         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2743                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2744                 if (cur_val < 0) /* BCLK table is sorted */
2745                         break;
2746                 best = i;
2747         }
2748         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2749         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2750                 bclk_divs[best], bclk_rate);
2751         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2752
2753         lrclk = bclk_rate / params_rate(params);
2754         if (!lrclk) {
2755                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2756                         bclk_rate);
2757                 return -EINVAL;
2758         }
2759         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2760                 lrclk, bclk_rate / lrclk);
2761
2762         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2763         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2764         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2765         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2766                             lrclk);
2767         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2768                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2769
2770         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2771                 switch (dai->id) {
2772                 case 1:
2773                         wm8994->dac_rates[0] = params_rate(params);
2774                         wm8994_set_retune_mobile(codec, 0);
2775                         wm8994_set_retune_mobile(codec, 1);
2776                         break;
2777                 case 2:
2778                         wm8994->dac_rates[1] = params_rate(params);
2779                         wm8994_set_retune_mobile(codec, 2);
2780                         break;
2781                 }
2782         }
2783
2784         return 0;
2785 }
2786
2787 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2788                                  struct snd_pcm_hw_params *params,
2789                                  struct snd_soc_dai *dai)
2790 {
2791         struct snd_soc_codec *codec = dai->codec;
2792         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2793         struct wm8994 *control = wm8994->wm8994;
2794         int aif1_reg;
2795         int aif1 = 0;
2796
2797         switch (dai->id) {
2798         case 3:
2799                 switch (control->type) {
2800                 case WM1811:
2801                 case WM8958:
2802                         aif1_reg = WM8958_AIF3_CONTROL_1;
2803                         break;
2804                 default:
2805                         return 0;
2806                 }
2807         default:
2808                 return 0;
2809         }
2810
2811         switch (params_format(params)) {
2812         case SNDRV_PCM_FORMAT_S16_LE:
2813                 break;
2814         case SNDRV_PCM_FORMAT_S20_3LE:
2815                 aif1 |= 0x20;
2816                 break;
2817         case SNDRV_PCM_FORMAT_S24_LE:
2818                 aif1 |= 0x40;
2819                 break;
2820         case SNDRV_PCM_FORMAT_S32_LE:
2821                 aif1 |= 0x60;
2822                 break;
2823         default:
2824                 return -EINVAL;
2825         }
2826
2827         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2828 }
2829
2830 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2831 {
2832         struct snd_soc_codec *codec = codec_dai->codec;
2833         int mute_reg;
2834         int reg;
2835
2836         switch (codec_dai->id) {
2837         case 1:
2838                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2839                 break;
2840         case 2:
2841                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2842                 break;
2843         default:
2844                 return -EINVAL;
2845         }
2846
2847         if (mute)
2848                 reg = WM8994_AIF1DAC1_MUTE;
2849         else
2850                 reg = 0;
2851
2852         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2853
2854         return 0;
2855 }
2856
2857 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2858 {
2859         struct snd_soc_codec *codec = codec_dai->codec;
2860         int reg, val, mask;
2861
2862         switch (codec_dai->id) {
2863         case 1:
2864                 reg = WM8994_AIF1_MASTER_SLAVE;
2865                 mask = WM8994_AIF1_TRI;
2866                 break;
2867         case 2:
2868                 reg = WM8994_AIF2_MASTER_SLAVE;
2869                 mask = WM8994_AIF2_TRI;
2870                 break;
2871         default:
2872                 return -EINVAL;
2873         }
2874
2875         if (tristate)
2876                 val = mask;
2877         else
2878                 val = 0;
2879
2880         return snd_soc_update_bits(codec, reg, mask, val);
2881 }
2882
2883 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2884 {
2885         struct snd_soc_codec *codec = dai->codec;
2886
2887         /* Disable the pulls on the AIF if we're using it to save power. */
2888         snd_soc_update_bits(codec, WM8994_GPIO_3,
2889                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2890         snd_soc_update_bits(codec, WM8994_GPIO_4,
2891                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2892         snd_soc_update_bits(codec, WM8994_GPIO_5,
2893                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2894
2895         return 0;
2896 }
2897
2898 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2899
2900 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2901                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2902
2903 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2904         .set_sysclk     = wm8994_set_dai_sysclk,
2905         .set_fmt        = wm8994_set_dai_fmt,
2906         .hw_params      = wm8994_hw_params,
2907         .digital_mute   = wm8994_aif_mute,
2908         .set_pll        = wm8994_set_fll,
2909         .set_tristate   = wm8994_set_tristate,
2910 };
2911
2912 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2913         .set_sysclk     = wm8994_set_dai_sysclk,
2914         .set_fmt        = wm8994_set_dai_fmt,
2915         .hw_params      = wm8994_hw_params,
2916         .digital_mute   = wm8994_aif_mute,
2917         .set_pll        = wm8994_set_fll,
2918         .set_tristate   = wm8994_set_tristate,
2919 };
2920
2921 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2922         .hw_params      = wm8994_aif3_hw_params,
2923 };
2924
2925 static struct snd_soc_dai_driver wm8994_dai[] = {
2926         {
2927                 .name = "wm8994-aif1",
2928                 .id = 1,
2929                 .playback = {
2930                         .stream_name = "AIF1 Playback",
2931                         .channels_min = 1,
2932                         .channels_max = 2,
2933                         .rates = WM8994_RATES,
2934                         .formats = WM8994_FORMATS,
2935                         .sig_bits = 24,
2936                 },
2937                 .capture = {
2938                         .stream_name = "AIF1 Capture",
2939                         .channels_min = 1,
2940                         .channels_max = 2,
2941                         .rates = WM8994_RATES,
2942                         .formats = WM8994_FORMATS,
2943                         .sig_bits = 24,
2944                  },
2945                 .ops = &wm8994_aif1_dai_ops,
2946         },
2947         {
2948                 .name = "wm8994-aif2",
2949                 .id = 2,
2950                 .playback = {
2951                         .stream_name = "AIF2 Playback",
2952                         .channels_min = 1,
2953                         .channels_max = 2,
2954                         .rates = WM8994_RATES,
2955                         .formats = WM8994_FORMATS,
2956                         .sig_bits = 24,
2957                 },
2958                 .capture = {
2959                         .stream_name = "AIF2 Capture",
2960                         .channels_min = 1,
2961                         .channels_max = 2,
2962                         .rates = WM8994_RATES,
2963                         .formats = WM8994_FORMATS,
2964                         .sig_bits = 24,
2965                 },
2966                 .probe = wm8994_aif2_probe,
2967                 .ops = &wm8994_aif2_dai_ops,
2968         },
2969         {
2970                 .name = "wm8994-aif3",
2971                 .id = 3,
2972                 .playback = {
2973                         .stream_name = "AIF3 Playback",
2974                         .channels_min = 1,
2975                         .channels_max = 2,
2976                         .rates = WM8994_RATES,
2977                         .formats = WM8994_FORMATS,
2978                         .sig_bits = 24,
2979                 },
2980                 .capture = {
2981                         .stream_name = "AIF3 Capture",
2982                         .channels_min = 1,
2983                         .channels_max = 2,
2984                         .rates = WM8994_RATES,
2985                         .formats = WM8994_FORMATS,
2986                         .sig_bits = 24,
2987                  },
2988                 .ops = &wm8994_aif3_dai_ops,
2989         }
2990 };
2991
2992 #ifdef CONFIG_PM
2993 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
2994 {
2995         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2996         int i, ret;
2997
2998         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2999                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3000                        sizeof(struct wm8994_fll_config));
3001                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3002                 if (ret < 0)
3003                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3004                                  i + 1, ret);
3005         }
3006
3007         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3008
3009         return 0;
3010 }
3011
3012 static int wm8994_codec_resume(struct snd_soc_codec *codec)
3013 {
3014         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3015         struct wm8994 *control = wm8994->wm8994;
3016         int i, ret;
3017         unsigned int val, mask;
3018
3019         if (wm8994->revision < 4) {
3020                 /* force a HW read */
3021                 ret = regmap_read(control->regmap,
3022                                   WM8994_POWER_MANAGEMENT_5, &val);
3023
3024                 /* modify the cache only */
3025                 codec->cache_only = 1;
3026                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3027                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3028                 val &= mask;
3029                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3030                                     mask, val);
3031                 codec->cache_only = 0;
3032         }
3033
3034         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3035                 if (!wm8994->fll_suspend[i].out)
3036                         continue;
3037
3038                 ret = _wm8994_set_fll(codec, i + 1,
3039                                      wm8994->fll_suspend[i].src,
3040                                      wm8994->fll_suspend[i].in,
3041                                      wm8994->fll_suspend[i].out);
3042                 if (ret < 0)
3043                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3044                                  i + 1, ret);
3045         }
3046
3047         return 0;
3048 }
3049 #else
3050 #define wm8994_codec_suspend NULL
3051 #define wm8994_codec_resume NULL
3052 #endif
3053
3054 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3055 {
3056         struct snd_soc_codec *codec = wm8994->hubs.codec;
3057         struct wm8994_pdata *pdata = wm8994->pdata;
3058         struct snd_kcontrol_new controls[] = {
3059                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3060                              wm8994->retune_mobile_enum,
3061                              wm8994_get_retune_mobile_enum,
3062                              wm8994_put_retune_mobile_enum),
3063                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3064                              wm8994->retune_mobile_enum,
3065                              wm8994_get_retune_mobile_enum,
3066                              wm8994_put_retune_mobile_enum),
3067                 SOC_ENUM_EXT("AIF2 EQ Mode",
3068                              wm8994->retune_mobile_enum,
3069                              wm8994_get_retune_mobile_enum,
3070                              wm8994_put_retune_mobile_enum),
3071         };
3072         int ret, i, j;
3073         const char **t;
3074
3075         /* We need an array of texts for the enum API but the number
3076          * of texts is likely to be less than the number of
3077          * configurations due to the sample rate dependency of the
3078          * configurations. */
3079         wm8994->num_retune_mobile_texts = 0;
3080         wm8994->retune_mobile_texts = NULL;
3081         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3082                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3083                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
3084                                    wm8994->retune_mobile_texts[j]) == 0)
3085                                 break;
3086                 }
3087
3088                 if (j != wm8994->num_retune_mobile_texts)
3089                         continue;
3090
3091                 /* Expand the array... */
3092                 t = krealloc(wm8994->retune_mobile_texts,
3093                              sizeof(char *) *
3094                              (wm8994->num_retune_mobile_texts + 1),
3095                              GFP_KERNEL);
3096                 if (t == NULL)
3097                         continue;
3098
3099                 /* ...store the new entry... */
3100                 t[wm8994->num_retune_mobile_texts] =
3101                         pdata->retune_mobile_cfgs[i].name;
3102
3103                 /* ...and remember the new version. */
3104                 wm8994->num_retune_mobile_texts++;
3105                 wm8994->retune_mobile_texts = t;
3106         }
3107
3108         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3109                 wm8994->num_retune_mobile_texts);
3110
3111         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3112         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3113
3114         ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3115                                    ARRAY_SIZE(controls));
3116         if (ret != 0)
3117                 dev_err(wm8994->hubs.codec->dev,
3118                         "Failed to add ReTune Mobile controls: %d\n", ret);
3119 }
3120
3121 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3122 {
3123         struct snd_soc_codec *codec = wm8994->hubs.codec;
3124         struct wm8994_pdata *pdata = wm8994->pdata;
3125         int ret, i;
3126
3127         if (!pdata)
3128                 return;
3129
3130         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3131                                       pdata->lineout2_diff,
3132                                       pdata->lineout1fb,
3133                                       pdata->lineout2fb,
3134                                       pdata->jd_scthr,
3135                                       pdata->jd_thr,
3136                                       pdata->micbias1_lvl,
3137                                       pdata->micbias2_lvl);
3138
3139         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3140
3141         if (pdata->num_drc_cfgs) {
3142                 struct snd_kcontrol_new controls[] = {
3143                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3144                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3145                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3146                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3147                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3148                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3149                 };
3150
3151                 /* We need an array of texts for the enum API */
3152                 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3153                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3154                 if (!wm8994->drc_texts) {
3155                         dev_err(wm8994->hubs.codec->dev,
3156                                 "Failed to allocate %d DRC config texts\n",
3157                                 pdata->num_drc_cfgs);
3158                         return;
3159                 }
3160
3161                 for (i = 0; i < pdata->num_drc_cfgs; i++)
3162                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3163
3164                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3165                 wm8994->drc_enum.texts = wm8994->drc_texts;
3166
3167                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3168                                            ARRAY_SIZE(controls));
3169                 if (ret != 0)
3170                         dev_err(wm8994->hubs.codec->dev,
3171                                 "Failed to add DRC mode controls: %d\n", ret);
3172
3173                 for (i = 0; i < WM8994_NUM_DRC; i++)
3174                         wm8994_set_drc(codec, i);
3175         }
3176
3177         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3178                 pdata->num_retune_mobile_cfgs);
3179
3180         if (pdata->num_retune_mobile_cfgs)
3181                 wm8994_handle_retune_mobile_pdata(wm8994);
3182         else
3183                 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3184                                      ARRAY_SIZE(wm8994_eq_controls));
3185
3186         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3187                 if (pdata->micbias[i]) {
3188                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
3189                                 pdata->micbias[i] & 0xffff);
3190                 }
3191         }
3192 }
3193
3194 /**
3195  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3196  *
3197  * @codec:   WM8994 codec
3198  * @jack:    jack to report detection events on
3199  * @micbias: microphone bias to detect on
3200  *
3201  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
3202  * being used to bring out signals to the processor then only platform
3203  * data configuration is needed for WM8994 and processor GPIOs should
3204  * be configured using snd_soc_jack_add_gpios() instead.
3205  *
3206  * Configuration of detection levels is available via the micbias1_lvl
3207  * and micbias2_lvl platform data members.
3208  */
3209 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3210                       int micbias)
3211 {
3212         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3213         struct wm8994_micdet *micdet;
3214         struct wm8994 *control = wm8994->wm8994;
3215         int reg, ret;
3216
3217         if (control->type != WM8994) {
3218                 dev_warn(codec->dev, "Not a WM8994\n");
3219                 return -EINVAL;
3220         }
3221
3222         switch (micbias) {
3223         case 1:
3224                 micdet = &wm8994->micdet[0];
3225                 if (jack)
3226                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3227                                                             "MICBIAS1");
3228                 else
3229                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3230                                                        "MICBIAS1");
3231                 break;
3232         case 2:
3233                 micdet = &wm8994->micdet[1];
3234                 if (jack)
3235                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3236                                                             "MICBIAS1");
3237                 else
3238                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3239                                                        "MICBIAS1");
3240                 break;
3241         default:
3242                 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3243                 return -EINVAL;
3244         }
3245
3246         if (ret != 0)
3247                 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3248                          micbias, ret);
3249
3250         dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3251                 micbias, jack);
3252
3253         /* Store the configuration */
3254         micdet->jack = jack;
3255         micdet->detecting = true;
3256
3257         /* If either of the jacks is set up then enable detection */
3258         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3259                 reg = WM8994_MICD_ENA;
3260         else
3261                 reg = 0;
3262
3263         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3264
3265         snd_soc_dapm_sync(&codec->dapm);
3266
3267         return 0;
3268 }
3269 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3270
3271 static void wm8994_mic_work(struct work_struct *work)
3272 {
3273         struct wm8994_priv *priv = container_of(work,
3274                                                 struct wm8994_priv,
3275                                                 mic_work.work);
3276         struct regmap *regmap = priv->wm8994->regmap;
3277         struct device *dev = priv->wm8994->dev;
3278         unsigned int reg;
3279         int ret;
3280         int report;
3281
3282         pm_runtime_get_sync(dev);
3283
3284         ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3285         if (ret < 0) {
3286                 dev_err(dev, "Failed to read microphone status: %d\n",
3287                         ret);
3288                 pm_runtime_put(dev);
3289                 return;
3290         }
3291
3292         dev_dbg(dev, "Microphone status: %x\n", reg);
3293
3294         report = 0;
3295         if (reg & WM8994_MIC1_DET_STS) {
3296                 if (priv->micdet[0].detecting)
3297                         report = SND_JACK_HEADSET;
3298         }
3299         if (reg & WM8994_MIC1_SHRT_STS) {
3300                 if (priv->micdet[0].detecting)
3301                         report = SND_JACK_HEADPHONE;
3302                 else
3303                         report |= SND_JACK_BTN_0;
3304         }
3305         if (report)
3306                 priv->micdet[0].detecting = false;
3307         else
3308                 priv->micdet[0].detecting = true;
3309
3310         snd_soc_jack_report(priv->micdet[0].jack, report,
3311                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3312
3313         report = 0;
3314         if (reg & WM8994_MIC2_DET_STS) {
3315                 if (priv->micdet[1].detecting)
3316                         report = SND_JACK_HEADSET;
3317         }
3318         if (reg & WM8994_MIC2_SHRT_STS) {
3319                 if (priv->micdet[1].detecting)
3320                         report = SND_JACK_HEADPHONE;
3321                 else
3322                         report |= SND_JACK_BTN_0;
3323         }
3324         if (report)
3325                 priv->micdet[1].detecting = false;
3326         else
3327                 priv->micdet[1].detecting = true;
3328
3329         snd_soc_jack_report(priv->micdet[1].jack, report,
3330                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3331
3332         pm_runtime_put(dev);
3333 }
3334
3335 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3336 {
3337         struct wm8994_priv *priv = data;
3338         struct snd_soc_codec *codec = priv->hubs.codec;
3339
3340 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3341         trace_snd_soc_jack_irq(dev_name(codec->dev));
3342 #endif
3343
3344         pm_wakeup_event(codec->dev, 300);
3345
3346         schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
3347
3348         return IRQ_HANDLED;
3349 }
3350
3351 /* Default microphone detection handler for WM8958 - the user can
3352  * override this if they wish.
3353  */
3354 static void wm8958_default_micdet(u16 status, void *data)
3355 {
3356         struct snd_soc_codec *codec = data;
3357         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3358         int report;
3359
3360         dev_dbg(codec->dev, "MICDET %x\n", status);
3361
3362         /* Either nothing present or just starting detection */
3363         if (!(status & WM8958_MICD_STS)) {
3364                 if (!wm8994->jackdet) {
3365                         /* If nothing present then clear our statuses */
3366                         dev_dbg(codec->dev, "Detected open circuit\n");
3367                         wm8994->jack_mic = false;
3368                         wm8994->mic_detecting = true;
3369
3370                         wm8958_micd_set_rate(codec);
3371
3372                         snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3373                                             wm8994->btn_mask |
3374                                              SND_JACK_HEADSET);
3375                 }
3376                 return;
3377         }
3378
3379         /* If the measurement is showing a high impedence we've got a
3380          * microphone.
3381          */
3382         if (wm8994->mic_detecting && (status & 0x600)) {
3383                 dev_dbg(codec->dev, "Detected microphone\n");
3384
3385                 wm8994->mic_detecting = false;
3386                 wm8994->jack_mic = true;
3387
3388                 wm8958_micd_set_rate(codec);
3389
3390                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3391                                     SND_JACK_HEADSET);
3392         }
3393
3394
3395         if (wm8994->mic_detecting && status & 0xfc) {
3396                 dev_dbg(codec->dev, "Detected headphone\n");
3397                 wm8994->mic_detecting = false;
3398
3399                 wm8958_micd_set_rate(codec);
3400
3401                 /* If we have jackdet that will detect removal */
3402                 if (wm8994->jackdet) {
3403                         mutex_lock(&wm8994->accdet_lock);
3404
3405                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3406                                             WM8958_MICD_ENA, 0);
3407
3408                         wm1811_jackdet_set_mode(codec,
3409                                                 WM1811_JACKDET_MODE_JACK);
3410
3411                         mutex_unlock(&wm8994->accdet_lock);
3412
3413                         if (wm8994->pdata->jd_ext_cap)
3414                                 snd_soc_dapm_disable_pin(&codec->dapm,
3415                                                          "MICBIAS2");
3416                 }
3417
3418                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3419                                     SND_JACK_HEADSET);
3420         }
3421
3422         /* Report short circuit as a button */
3423         if (wm8994->jack_mic) {
3424                 report = 0;
3425                 if (status & 0x4)
3426                         report |= SND_JACK_BTN_0;
3427
3428                 if (status & 0x8)
3429                         report |= SND_JACK_BTN_1;
3430
3431                 if (status & 0x10)
3432                         report |= SND_JACK_BTN_2;
3433
3434                 if (status & 0x20)
3435                         report |= SND_JACK_BTN_3;
3436
3437                 if (status & 0x40)
3438                         report |= SND_JACK_BTN_4;
3439
3440                 if (status & 0x80)
3441                         report |= SND_JACK_BTN_5;
3442
3443                 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3444                                     wm8994->btn_mask);
3445         }
3446 }
3447
3448 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3449 {
3450         struct wm8994_priv *wm8994 = data;
3451         struct snd_soc_codec *codec = wm8994->hubs.codec;
3452         int reg;
3453         bool present;
3454
3455         pm_runtime_get_sync(codec->dev);
3456
3457         mutex_lock(&wm8994->accdet_lock);
3458
3459         reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3460         if (reg < 0) {
3461                 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3462                 mutex_unlock(&wm8994->accdet_lock);
3463                 pm_runtime_put(codec->dev);
3464                 return IRQ_NONE;
3465         }
3466
3467         dev_dbg(codec->dev, "JACKDET %x\n", reg);
3468
3469         present = reg & WM1811_JACKDET_LVL;
3470
3471         if (present) {
3472                 dev_dbg(codec->dev, "Jack detected\n");
3473
3474                 wm8958_micd_set_rate(codec);
3475
3476                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3477                                     WM8958_MICB2_DISCH, 0);
3478
3479                 /* Disable debounce while inserted */
3480                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3481                                     WM1811_JACKDET_DB, 0);
3482
3483                 /*
3484                  * Start off measument of microphone impedence to find
3485                  * out what's actually there.
3486                  */
3487                 wm8994->mic_detecting = true;
3488                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3489
3490                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3491                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3492         } else {
3493                 dev_dbg(codec->dev, "Jack not detected\n");
3494
3495                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3496                                     WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3497
3498                 /* Enable debounce while removed */
3499                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3500                                     WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3501
3502                 wm8994->mic_detecting = false;
3503                 wm8994->jack_mic = false;
3504                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3505                                     WM8958_MICD_ENA, 0);
3506                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3507         }
3508
3509         mutex_unlock(&wm8994->accdet_lock);
3510
3511         /* If required for an external cap force MICBIAS on */
3512         if (wm8994->pdata->jd_ext_cap) {
3513                 if (present)
3514                         snd_soc_dapm_force_enable_pin(&codec->dapm,
3515                                                       "MICBIAS2");
3516                 else
3517                         snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3518         }
3519
3520         if (present)
3521                 snd_soc_jack_report(wm8994->micdet[0].jack,
3522                                     SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3523         else
3524                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3525                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3526                                     wm8994->btn_mask);
3527
3528         /* Since we only report deltas force an update, ensures we
3529          * avoid bootstrapping issues with the core. */
3530         snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3531
3532         pm_runtime_put(codec->dev);
3533         return IRQ_HANDLED;
3534 }
3535
3536 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3537 {
3538         struct wm8994_priv *wm8994 = container_of(work,
3539                                                 struct wm8994_priv,
3540                                                 jackdet_bootstrap.work);
3541         wm1811_jackdet_irq(0, wm8994);
3542 }
3543
3544 /**
3545  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3546  *
3547  * @codec:   WM8958 codec
3548  * @jack:    jack to report detection events on
3549  *
3550  * Enable microphone detection functionality for the WM8958.  By
3551  * default simple detection which supports the detection of up to 6
3552  * buttons plus video and microphone functionality is supported.
3553  *
3554  * The WM8958 has an advanced jack detection facility which is able to
3555  * support complex accessory detection, especially when used in
3556  * conjunction with external circuitry.  In order to provide maximum
3557  * flexiblity a callback is provided which allows a completely custom
3558  * detection algorithm.
3559  */
3560 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3561                       wm8958_micdet_cb cb, void *cb_data)
3562 {
3563         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3564         struct wm8994 *control = wm8994->wm8994;
3565         u16 micd_lvl_sel;
3566
3567         switch (control->type) {
3568         case WM1811:
3569         case WM8958:
3570                 break;
3571         default:
3572                 return -EINVAL;
3573         }
3574
3575         if (jack) {
3576                 if (!cb) {
3577                         dev_dbg(codec->dev, "Using default micdet callback\n");
3578                         cb = wm8958_default_micdet;
3579                         cb_data = codec;
3580                 }
3581
3582                 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3583                 snd_soc_dapm_sync(&codec->dapm);
3584
3585                 wm8994->micdet[0].jack = jack;
3586                 wm8994->jack_cb = cb;
3587                 wm8994->jack_cb_data = cb_data;
3588
3589                 wm8994->mic_detecting = true;
3590                 wm8994->jack_mic = false;
3591
3592                 wm8958_micd_set_rate(codec);
3593
3594                 /* Detect microphones and short circuits by default */
3595                 if (wm8994->pdata->micd_lvl_sel)
3596                         micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3597                 else
3598                         micd_lvl_sel = 0x41;
3599
3600                 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3601                         SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3602                         SND_JACK_BTN_4 | SND_JACK_BTN_5;
3603
3604                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3605                                     WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3606
3607                 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3608
3609                 /*
3610                  * If we can use jack detection start off with that,
3611                  * otherwise jump straight to microphone detection.
3612                  */
3613                 if (wm8994->jackdet) {
3614                         /* Disable debounce for the initial detect */
3615                         snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3616                                             WM1811_JACKDET_DB, 0);
3617
3618                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
3619                                             WM8958_MICB2_DISCH,
3620                                             WM8958_MICB2_DISCH);
3621                         snd_soc_update_bits(codec, WM8994_LDO_1,
3622                                             WM8994_LDO1_DISCH, 0);
3623                         wm1811_jackdet_set_mode(codec,
3624                                                 WM1811_JACKDET_MODE_JACK);
3625                 } else {
3626                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3627                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
3628                 }
3629
3630         } else {
3631                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3632                                     WM8958_MICD_ENA, 0);
3633                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3634                 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3635                 snd_soc_dapm_sync(&codec->dapm);
3636         }
3637
3638         return 0;
3639 }
3640 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3641
3642 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3643 {
3644         struct wm8994_priv *wm8994 = data;
3645         struct snd_soc_codec *codec = wm8994->hubs.codec;
3646         int reg, count;
3647
3648         /*
3649          * Jack detection may have detected a removal simulataneously
3650          * with an update of the MICDET status; if so it will have
3651          * stopped detection and we can ignore this interrupt.
3652          */
3653         if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3654                 return IRQ_HANDLED;
3655
3656         pm_runtime_get_sync(codec->dev);
3657
3658         /* We may occasionally read a detection without an impedence
3659          * range being provided - if that happens loop again.
3660          */
3661         count = 10;
3662         do {
3663                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3664                 if (reg < 0) {
3665                         dev_err(codec->dev,
3666                                 "Failed to read mic detect status: %d\n",
3667                                 reg);
3668                         pm_runtime_put(codec->dev);
3669                         return IRQ_NONE;
3670                 }
3671
3672                 if (!(reg & WM8958_MICD_VALID)) {
3673                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3674                         goto out;
3675                 }
3676
3677                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3678                         break;
3679
3680                 msleep(1);
3681         } while (count--);
3682
3683         if (count == 0)
3684                 dev_warn(codec->dev, "No impedence range reported for jack\n");
3685
3686 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3687         trace_snd_soc_jack_irq(dev_name(codec->dev));
3688 #endif
3689
3690         if (wm8994->jack_cb)
3691                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3692         else
3693                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3694
3695 out:
3696         pm_runtime_put(codec->dev);
3697         return IRQ_HANDLED;
3698 }
3699
3700 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3701 {
3702         struct snd_soc_codec *codec = data;
3703
3704         dev_err(codec->dev, "FIFO error\n");
3705
3706         return IRQ_HANDLED;
3707 }
3708
3709 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3710 {
3711         struct snd_soc_codec *codec = data;
3712
3713         dev_err(codec->dev, "Thermal warning\n");
3714
3715         return IRQ_HANDLED;
3716 }
3717
3718 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3719 {
3720         struct snd_soc_codec *codec = data;
3721
3722         dev_crit(codec->dev, "Thermal shutdown\n");
3723
3724         return IRQ_HANDLED;
3725 }
3726
3727 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3728 {
3729         struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3730         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3731         struct snd_soc_dapm_context *dapm = &codec->dapm;
3732         unsigned int reg;
3733         int ret, i;
3734
3735         wm8994->hubs.codec = codec;
3736         codec->control_data = control->regmap;
3737
3738         snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3739
3740         mutex_init(&wm8994->accdet_lock);
3741         INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3742         INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3743                           wm1811_jackdet_bootstrap);
3744
3745         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3746                 init_completion(&wm8994->fll_locked[i]);
3747
3748         if (wm8994->pdata && wm8994->pdata->micdet_irq)
3749                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3750
3751         pm_runtime_enable(codec->dev);
3752         pm_runtime_idle(codec->dev);
3753
3754         /* By default use idle_bias_off, will override for WM8994 */
3755         codec->dapm.idle_bias_off = 1;
3756
3757         /* Set revision-specific configuration */
3758         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3759         switch (control->type) {
3760         case WM8994:
3761                 /* Single ended line outputs should have VMID on. */
3762                 if (!wm8994->pdata->lineout1_diff ||
3763                     !wm8994->pdata->lineout2_diff)
3764                         codec->dapm.idle_bias_off = 0;
3765
3766                 switch (wm8994->revision) {
3767                 case 2:
3768                 case 3:
3769                         wm8994->hubs.dcs_codes_l = -5;
3770                         wm8994->hubs.dcs_codes_r = -5;
3771                         wm8994->hubs.hp_startup_mode = 1;
3772                         wm8994->hubs.dcs_readback_mode = 1;
3773                         wm8994->hubs.series_startup = 1;
3774                         break;
3775                 default:
3776                         wm8994->hubs.dcs_readback_mode = 2;
3777                         break;
3778                 }
3779                 break;
3780
3781         case WM8958:
3782                 wm8994->hubs.dcs_readback_mode = 1;
3783                 wm8994->hubs.hp_startup_mode = 1;
3784
3785                 switch (wm8994->revision) {
3786                 case 0:
3787                         break;
3788                 default:
3789                         wm8994->fll_byp = true;
3790                         break;
3791                 }
3792                 break;
3793
3794         case WM1811:
3795                 wm8994->hubs.dcs_readback_mode = 2;
3796                 wm8994->hubs.no_series_update = 1;
3797                 wm8994->hubs.hp_startup_mode = 1;
3798                 wm8994->hubs.no_cache_dac_hp_direct = true;
3799                 wm8994->fll_byp = true;
3800
3801                 switch (wm8994->revision) {
3802                 case 0:
3803                 case 1:
3804                 case 2:
3805                 case 3:
3806                         wm8994->hubs.dcs_codes_l = -9;
3807                         wm8994->hubs.dcs_codes_r = -7;
3808                         break;
3809                 default:
3810                         break;
3811                 }
3812
3813                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3814                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3815                 break;
3816
3817         default:
3818                 break;
3819         }
3820
3821         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3822                            wm8994_fifo_error, "FIFO error", codec);
3823         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3824                            wm8994_temp_warn, "Thermal warning", codec);
3825         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3826                            wm8994_temp_shut, "Thermal shutdown", codec);
3827
3828         ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3829                                  wm_hubs_dcs_done, "DC servo done",
3830                                  &wm8994->hubs);
3831         if (ret == 0)
3832                 wm8994->hubs.dcs_done_irq = true;
3833
3834         switch (control->type) {
3835         case WM8994:
3836                 if (wm8994->micdet_irq) {
3837                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3838                                                    wm8994_mic_irq,
3839                                                    IRQF_TRIGGER_RISING,
3840                                                    "Mic1 detect",
3841                                                    wm8994);
3842                         if (ret != 0)
3843                                 dev_warn(codec->dev,
3844                                          "Failed to request Mic1 detect IRQ: %d\n",
3845                                          ret);
3846                 }
3847
3848                 ret = wm8994_request_irq(wm8994->wm8994,
3849                                          WM8994_IRQ_MIC1_SHRT,
3850                                          wm8994_mic_irq, "Mic 1 short",
3851                                          wm8994);
3852                 if (ret != 0)
3853                         dev_warn(codec->dev,
3854                                  "Failed to request Mic1 short IRQ: %d\n",
3855                                  ret);
3856
3857                 ret = wm8994_request_irq(wm8994->wm8994,
3858                                          WM8994_IRQ_MIC2_DET,
3859                                          wm8994_mic_irq, "Mic 2 detect",
3860                                          wm8994);
3861                 if (ret != 0)
3862                         dev_warn(codec->dev,
3863                                  "Failed to request Mic2 detect IRQ: %d\n",
3864                                  ret);
3865
3866                 ret = wm8994_request_irq(wm8994->wm8994,
3867                                          WM8994_IRQ_MIC2_SHRT,
3868                                          wm8994_mic_irq, "Mic 2 short",
3869                                          wm8994);
3870                 if (ret != 0)
3871                         dev_warn(codec->dev,
3872                                  "Failed to request Mic2 short IRQ: %d\n",
3873                                  ret);
3874                 break;
3875
3876         case WM8958:
3877         case WM1811:
3878                 if (wm8994->micdet_irq) {
3879                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3880                                                    wm8958_mic_irq,
3881                                                    IRQF_TRIGGER_RISING,
3882                                                    "Mic detect",
3883                                                    wm8994);
3884                         if (ret != 0)
3885                                 dev_warn(codec->dev,
3886                                          "Failed to request Mic detect IRQ: %d\n",
3887                                          ret);
3888                 } else {
3889                         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3890                                            wm8958_mic_irq, "Mic detect",
3891                                            wm8994);
3892                 }
3893         }
3894
3895         switch (control->type) {
3896         case WM1811:
3897                 if (wm8994->revision > 1) {
3898                         ret = wm8994_request_irq(wm8994->wm8994,
3899                                                  WM8994_IRQ_GPIO(6),
3900                                                  wm1811_jackdet_irq, "JACKDET",
3901                                                  wm8994);
3902                         if (ret == 0)
3903                                 wm8994->jackdet = true;
3904                 }
3905                 break;
3906         default:
3907                 break;
3908         }
3909
3910         wm8994->fll_locked_irq = true;
3911         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3912                 ret = wm8994_request_irq(wm8994->wm8994,
3913                                          WM8994_IRQ_FLL1_LOCK + i,
3914                                          wm8994_fll_locked_irq, "FLL lock",
3915                                          &wm8994->fll_locked[i]);
3916                 if (ret != 0)
3917                         wm8994->fll_locked_irq = false;
3918         }
3919
3920         /* Make sure we can read from the GPIOs if they're inputs */
3921         pm_runtime_get_sync(codec->dev);
3922
3923         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3924          * configured on init - if a system wants to do this dynamically
3925          * at runtime we can deal with that then.
3926          */
3927         ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3928         if (ret < 0) {
3929                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3930                 goto err_irq;
3931         }
3932         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3933                 wm8994->lrclk_shared[0] = 1;
3934                 wm8994_dai[0].symmetric_rates = 1;
3935         } else {
3936                 wm8994->lrclk_shared[0] = 0;
3937         }
3938
3939         ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3940         if (ret < 0) {
3941                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3942                 goto err_irq;
3943         }
3944         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3945                 wm8994->lrclk_shared[1] = 1;
3946                 wm8994_dai[1].symmetric_rates = 1;
3947         } else {
3948                 wm8994->lrclk_shared[1] = 0;
3949         }
3950
3951         pm_runtime_put(codec->dev);
3952
3953         /* Latch volume update bits */
3954         for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
3955                 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
3956                                     wm8994_vu_bits[i].mask,
3957                                     wm8994_vu_bits[i].mask);
3958
3959         /* Set the low bit of the 3D stereo depth so TLV matches */
3960         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3961                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3962                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3963         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3964                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3965                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3966         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3967                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3968                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3969
3970         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3971          * use this; it only affects behaviour on idle TDM clock
3972          * cycles. */
3973         switch (control->type) {
3974         case WM8994:
3975         case WM8958:
3976                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3977                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3978                 break;
3979         default:
3980                 break;
3981         }
3982
3983         /* Put MICBIAS into bypass mode by default on newer devices */
3984         switch (control->type) {
3985         case WM8958:
3986         case WM1811:
3987                 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3988                                     WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3989                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3990                                     WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3991                 break;
3992         default:
3993                 break;
3994         }
3995
3996         wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
3997         wm_hubs_update_class_w(codec);
3998
3999         wm8994_handle_pdata(wm8994);
4000
4001         wm_hubs_add_analogue_controls(codec);
4002         snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4003                              ARRAY_SIZE(wm8994_snd_controls));
4004         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4005                                   ARRAY_SIZE(wm8994_dapm_widgets));
4006
4007         switch (control->type) {
4008         case WM8994:
4009                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4010                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
4011                 if (wm8994->revision < 4) {
4012                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4013                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4014                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4015                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4016                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4017                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4018                 } else {
4019                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4020                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4021                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4022                                                   ARRAY_SIZE(wm8994_adc_widgets));
4023                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4024                                                   ARRAY_SIZE(wm8994_dac_widgets));
4025                 }
4026                 break;
4027         case WM8958:
4028                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4029                                      ARRAY_SIZE(wm8958_snd_controls));
4030                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4031                                           ARRAY_SIZE(wm8958_dapm_widgets));
4032                 if (wm8994->revision < 1) {
4033                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4034                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4035                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4036                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4037                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4038                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4039                 } else {
4040                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4041                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4042                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4043                                                   ARRAY_SIZE(wm8994_adc_widgets));
4044                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4045                                                   ARRAY_SIZE(wm8994_dac_widgets));
4046                 }
4047                 break;
4048
4049         case WM1811:
4050                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4051                                      ARRAY_SIZE(wm8958_snd_controls));
4052                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4053                                           ARRAY_SIZE(wm8958_dapm_widgets));
4054                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4055                                           ARRAY_SIZE(wm8994_lateclk_widgets));
4056                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4057                                           ARRAY_SIZE(wm8994_adc_widgets));
4058                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4059                                           ARRAY_SIZE(wm8994_dac_widgets));
4060                 break;
4061         }
4062
4063         wm_hubs_add_analogue_routes(codec, 0, 0);
4064         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4065
4066         switch (control->type) {
4067         case WM8994:
4068                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4069                                         ARRAY_SIZE(wm8994_intercon));
4070
4071                 if (wm8994->revision < 4) {
4072                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4073                                                 ARRAY_SIZE(wm8994_revd_intercon));
4074                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4075                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4076                 } else {
4077                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4078                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4079                 }
4080                 break;
4081         case WM8958:
4082                 if (wm8994->revision < 1) {
4083                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4084                                                 ARRAY_SIZE(wm8994_revd_intercon));
4085                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4086                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4087                 } else {
4088                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4089                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4090                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4091                                                 ARRAY_SIZE(wm8958_intercon));
4092                 }
4093
4094                 wm8958_dsp2_init(codec);
4095                 break;
4096         case WM1811:
4097                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4098                                         ARRAY_SIZE(wm8994_lateclk_intercon));
4099                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4100                                         ARRAY_SIZE(wm8958_intercon));
4101                 break;
4102         }
4103
4104         return 0;
4105
4106 err_irq:
4107         if (wm8994->jackdet)
4108                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4109         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4110         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4111         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4112         if (wm8994->micdet_irq)
4113                 free_irq(wm8994->micdet_irq, wm8994);
4114         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4115                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4116                                 &wm8994->fll_locked[i]);
4117         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4118                         &wm8994->hubs);
4119         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4120         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4121         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4122
4123         return ret;
4124 }
4125
4126 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4127 {
4128         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4129         struct wm8994 *control = wm8994->wm8994;
4130         int i;
4131
4132         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4133
4134         pm_runtime_disable(codec->dev);
4135
4136         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4137                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4138                                 &wm8994->fll_locked[i]);
4139
4140         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4141                         &wm8994->hubs);
4142         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4143         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4144         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4145
4146         if (wm8994->jackdet)
4147                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4148
4149         switch (control->type) {
4150         case WM8994:
4151                 if (wm8994->micdet_irq)
4152                         free_irq(wm8994->micdet_irq, wm8994);
4153                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4154                                 wm8994);
4155                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4156                                 wm8994);
4157                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4158                                 wm8994);
4159                 break;
4160
4161         case WM1811:
4162         case WM8958:
4163                 if (wm8994->micdet_irq)
4164                         free_irq(wm8994->micdet_irq, wm8994);
4165                 break;
4166         }
4167         release_firmware(wm8994->mbc);
4168         release_firmware(wm8994->mbc_vss);
4169         release_firmware(wm8994->enh_eq);
4170         kfree(wm8994->retune_mobile_texts);
4171         return 0;
4172 }
4173
4174 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4175         .probe =        wm8994_codec_probe,
4176         .remove =       wm8994_codec_remove,
4177         .suspend =      wm8994_codec_suspend,
4178         .resume =       wm8994_codec_resume,
4179         .set_bias_level = wm8994_set_bias_level,
4180 };
4181
4182 static int __devinit wm8994_probe(struct platform_device *pdev)
4183 {
4184         struct wm8994_priv *wm8994;
4185
4186         wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4187                               GFP_KERNEL);
4188         if (wm8994 == NULL)
4189                 return -ENOMEM;
4190         platform_set_drvdata(pdev, wm8994);
4191
4192         wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4193         wm8994->pdata = dev_get_platdata(pdev->dev.parent);
4194
4195         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4196                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
4197 }
4198
4199 static int __devexit wm8994_remove(struct platform_device *pdev)
4200 {
4201         snd_soc_unregister_codec(&pdev->dev);
4202         return 0;
4203 }
4204
4205 #ifdef CONFIG_PM_SLEEP
4206 static int wm8994_suspend(struct device *dev)
4207 {
4208         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4209
4210         /* Drop down to power saving mode when system is suspended */
4211         if (wm8994->jackdet && !wm8994->active_refcount)
4212                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4213                                    WM1811_JACKDET_MODE_MASK,
4214                                    wm8994->jackdet_mode);
4215
4216         return 0;
4217 }
4218
4219 static int wm8994_resume(struct device *dev)
4220 {
4221         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4222
4223         if (wm8994->jackdet && wm8994->jack_cb)
4224                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4225                                    WM1811_JACKDET_MODE_MASK,
4226                                    WM1811_JACKDET_MODE_AUDIO);
4227
4228         return 0;
4229 }
4230 #endif
4231
4232 static const struct dev_pm_ops wm8994_pm_ops = {
4233         SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4234 };
4235
4236 static struct platform_driver wm8994_codec_driver = {
4237         .driver = {
4238                 .name = "wm8994-codec",
4239                 .owner = THIS_MODULE,
4240                 .pm = &wm8994_pm_ops,
4241         },
4242         .probe = wm8994_probe,
4243         .remove = __devexit_p(wm8994_remove),
4244 };
4245
4246 module_platform_driver(wm8994_codec_driver);
4247
4248 MODULE_DESCRIPTION("ASoC WM8994 driver");
4249 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4250 MODULE_LICENSE("GPL");
4251 MODULE_ALIAS("platform:wm8994-codec");