Pileus Git - ~andy/linux/blob - sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM1811_JACKDET_MODE_NONE  0x0000
  42 #define WM1811_JACKDET_MODE_JACK  0x0100
  43 #define WM1811_JACKDET_MODE_MIC   0x0080
  44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
  45
  46 #define WM8994_NUM_DRC 3
  47 #define WM8994_NUM_EQ  3
  48
  49 static int wm8994_drc_base[] = {
  50         WM8994_AIF1_DRC1_1,
  51         WM8994_AIF1_DRC2_1,
  52         WM8994_AIF2_DRC_1,
  53 };
  54
  55 static int wm8994_retune_mobile_base[] = {
  56         WM8994_AIF1_DAC1_EQ_GAINS_1,
  57         WM8994_AIF1_DAC2_EQ_GAINS_1,
  58         WM8994_AIF2_EQ_GAINS_1,
  59 };
  60
  61 static void wm8958_default_micdet(u16 status, void *data);
  62
  63 static const struct wm8958_micd_rate micdet_rates[] = {
  64         { 32768,       true,  1, 4 },
  65         { 32768,       false, 1, 1 },
  66         { 44100 * 256, true,  7, 10 },
  67         { 44100 * 256, false, 7, 10 },
  68 };
  69
  70 static const struct wm8958_micd_rate jackdet_rates[] = {
  71         { 32768,       true,  0, 1 },
  72         { 32768,       false, 0, 1 },
  73         { 44100 * 256, true,  7, 10 },
  74         { 44100 * 256, false, 7, 10 },
  75 };
  76
  77 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
  78 {
  79         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  80         int best, i, sysclk, val;
  81         bool idle;
  82         const struct wm8958_micd_rate *rates;
  83         int num_rates;
  84
  85         if (wm8994->jack_cb != wm8958_default_micdet)
  86                 return;
  87
  88         idle = !wm8994->jack_mic;
  89
  90         sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
  91         if (sysclk & WM8994_SYSCLK_SRC)
  92                 sysclk = wm8994->aifclk[1];
  93         else
  94                 sysclk = wm8994->aifclk[0];
  95
  96         if (wm8994->pdata && wm8994->pdata->micd_rates) {
  97                 rates = wm8994->pdata->micd_rates;
  98                 num_rates = wm8994->pdata->num_micd_rates;
  99         } else if (wm8994->jackdet) {
 100                 rates = jackdet_rates;
 101                 num_rates = ARRAY_SIZE(jackdet_rates);
 102         } else {
 103                 rates = micdet_rates;
 104                 num_rates = ARRAY_SIZE(micdet_rates);
 105         }
 106
 107         best = 0;
 108         for (i = 0; i < num_rates; i++) {
 109                 if (rates[i].idle != idle)
 110                         continue;
 111                 if (abs(rates[i].sysclk - sysclk) <
 112                     abs(rates[best].sysclk - sysclk))
 113                         best = i;
 114                 else if (rates[best].idle != idle)
 115                         best = i;
 116         }
 117
 118         val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
 119                 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
 120
 121         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
 122                             WM8958_MICD_BIAS_STARTTIME_MASK |
 123                             WM8958_MICD_RATE_MASK, val);
 124 }
 125
 126 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 127 {
 128         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 129         int rate;
 130         int reg1 = 0;
 131         int offset;
 132
 133         if (aif)
 134                 offset = 4;
 135         else
 136                 offset = 0;
 137
 138         switch (wm8994->sysclk[aif]) {
 139         case WM8994_SYSCLK_MCLK1:
 140                 rate = wm8994->mclk[0];
 141                 break;
 142
 143         case WM8994_SYSCLK_MCLK2:
 144                 reg1 |= 0x8;
 145                 rate = wm8994->mclk[1];
 146                 break;
 147
 148         case WM8994_SYSCLK_FLL1:
 149                 reg1 |= 0x10;
 150                 rate = wm8994->fll[0].out;
 151                 break;
 152
 153         case WM8994_SYSCLK_FLL2:
 154                 reg1 |= 0x18;
 155                 rate = wm8994->fll[1].out;
 156                 break;
 157
 158         default:
 159                 return -EINVAL;
 160         }
 161
 162         if (rate >= 13500000) {
 163                 rate /= 2;
 164                 reg1 |= WM8994_AIF1CLK_DIV;
 165
 166                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 167                         aif + 1, rate);
 168         }
 169
 170         wm8994->aifclk[aif] = rate;
 171
 172         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 173                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 174                             reg1);
 175
 176         return 0;
 177 }
 178
 179 static int configure_clock(struct snd_soc_codec *codec)
 180 {
 181         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 182         int change, new;
 183
 184         /* Bring up the AIF clocks first */
 185         configure_aif_clock(codec, 0);
 186         configure_aif_clock(codec, 1);
 187
 188         /* Then switch CLK_SYS over to the higher of them; a change
 189          * can only happen as a result of a clocking change which can
 190          * only be made outside of DAPM so we can safely redo the
 191          * clocking.
 192          */
 193
 194         /* If they're equal it doesn't matter which is used */
 195         if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
 196                 wm8958_micd_set_rate(codec);
 197                 return 0;
 198         }
 199
 200         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 201                 new = WM8994_SYSCLK_SRC;
 202         else
 203                 new = 0;
 204
 205         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 206                                      WM8994_SYSCLK_SRC, new);
 207         if (change)
 208                 snd_soc_dapm_sync(&codec->dapm);
 209
 210         wm8958_micd_set_rate(codec);
 211
 212         return 0;
 213 }
 214
 215 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 216                          struct snd_soc_dapm_widget *sink)
 217 {
 218         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 219         const char *clk;
 220
 221         /* Check what we're currently using for CLK_SYS */
 222         if (reg & WM8994_SYSCLK_SRC)
 223                 clk = "AIF2CLK";
 224         else
 225                 clk = "AIF1CLK";
 226
 227         return strcmp(source->name, clk) == 0;
 228 }
 229
 230 static const char *sidetone_hpf_text[] = {
 231         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 232 };
 233
 234 static const struct soc_enum sidetone_hpf =
 235         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 236
 237 static const char *adc_hpf_text[] = {
 238         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 239 };
 240
 241 static const struct soc_enum aif1adc1_hpf =
 242         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 243
 244 static const struct soc_enum aif1adc2_hpf =
 245         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 246
 247 static const struct soc_enum aif2adc_hpf =
 248         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 249
 250 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 251 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 252 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 253 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 254 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 255 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 256 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 257
 258 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 259 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 260         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 261         .put = wm8994_put_drc_sw, \
 262         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 263
 264 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 265                              struct snd_ctl_elem_value *ucontrol)
 266 {
 267         struct soc_mixer_control *mc =
 268                 (struct soc_mixer_control *)kcontrol->private_value;
 269         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 270         int mask, ret;
 271
 272         /* Can't enable both ADC and DAC paths simultaneously */
 273         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 274                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 275                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 276         else
 277                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 278
 279         ret = snd_soc_read(codec, mc->reg);
 280         if (ret < 0)
 281                 return ret;
 282         if (ret & mask)
 283                 return -EINVAL;
 284
 285         return snd_soc_put_volsw(kcontrol, ucontrol);
 286 }
 287
 288 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 289 {
 290         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 291         struct wm8994_pdata *pdata = wm8994->pdata;
 292         int base = wm8994_drc_base[drc];
 293         int cfg = wm8994->drc_cfg[drc];
 294         int save, i;
 295
 296         /* Save any enables; the configuration should clear them. */
 297         save = snd_soc_read(codec, base);
 298         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 299                 WM8994_AIF1ADC1R_DRC_ENA;
 300
 301         for (i = 0; i < WM8994_DRC_REGS; i++)
 302                 snd_soc_update_bits(codec, base + i, 0xffff,
 303                                     pdata->drc_cfgs[cfg].regs[i]);
 304
 305         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 306                              WM8994_AIF1ADC1L_DRC_ENA |
 307                              WM8994_AIF1ADC1R_DRC_ENA, save);
 308 }
 309
 310 /* Icky as hell but saves code duplication */
 311 static int wm8994_get_drc(const char *name)
 312 {
 313         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 314                 return 0;
 315         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 316                 return 1;
 317         if (strcmp(name, "AIF2DRC Mode") == 0)
 318                 return 2;
 319         return -EINVAL;
 320 }
 321
 322 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 323                                struct snd_ctl_elem_value *ucontrol)
 324 {
 325         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 326         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 327         struct wm8994_pdata *pdata = wm8994->pdata;
 328         int drc = wm8994_get_drc(kcontrol->id.name);
 329         int value = ucontrol->value.integer.value[0];
 330
 331         if (drc < 0)
 332                 return drc;
 333
 334         if (value >= pdata->num_drc_cfgs)
 335                 return -EINVAL;
 336
 337         wm8994->drc_cfg[drc] = value;
 338
 339         wm8994_set_drc(codec, drc);
 340
 341         return 0;
 342 }
 343
 344 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 345                                struct snd_ctl_elem_value *ucontrol)
 346 {
 347         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 348         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 349         int drc = wm8994_get_drc(kcontrol->id.name);
 350
 351         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 352
 353         return 0;
 354 }
 355
 356 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 357 {
 358         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 359         struct wm8994_pdata *pdata = wm8994->pdata;
 360         int base = wm8994_retune_mobile_base[block];
 361         int iface, best, best_val, save, i, cfg;
 362
 363         if (!pdata || !wm8994->num_retune_mobile_texts)
 364                 return;
 365
 366         switch (block) {
 367         case 0:
 368         case 1:
 369                 iface = 0;
 370                 break;
 371         case 2:
 372                 iface = 1;
 373                 break;
 374         default:
 375                 return;
 376         }
 377
 378         /* Find the version of the currently selected configuration
 379          * with the nearest sample rate. */
 380         cfg = wm8994->retune_mobile_cfg[block];
 381         best = 0;
 382         best_val = INT_MAX;
 383         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 384                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 385                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 386                     abs(pdata->retune_mobile_cfgs[i].rate
 387                         - wm8994->dac_rates[iface]) < best_val) {
 388                         best = i;
 389                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 390                                        - wm8994->dac_rates[iface]);
 391                 }
 392         }
 393
 394         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 395                 block,
 396                 pdata->retune_mobile_cfgs[best].name,
 397                 pdata->retune_mobile_cfgs[best].rate,
 398                 wm8994->dac_rates[iface]);
 399
 400         /* The EQ will be disabled while reconfiguring it, remember the
 401          * current configuration.
 402          */
 403         save = snd_soc_read(codec, base);
 404         save &= WM8994_AIF1DAC1_EQ_ENA;
 405
 406         for (i = 0; i < WM8994_EQ_REGS; i++)
 407                 snd_soc_update_bits(codec, base + i, 0xffff,
 408                                 pdata->retune_mobile_cfgs[best].regs[i]);
 409
 410         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 411 }
 412
 413 /* Icky as hell but saves code duplication */
 414 static int wm8994_get_retune_mobile_block(const char *name)
 415 {
 416         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 417                 return 0;
 418         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 419                 return 1;
 420         if (strcmp(name, "AIF2 EQ Mode") == 0)
 421                 return 2;
 422         return -EINVAL;
 423 }
 424
 425 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 426                                          struct snd_ctl_elem_value *ucontrol)
 427 {
 428         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 429         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 430         struct wm8994_pdata *pdata = wm8994->pdata;
 431         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 432         int value = ucontrol->value.integer.value[0];
 433
 434         if (block < 0)
 435                 return block;
 436
 437         if (value >= pdata->num_retune_mobile_cfgs)
 438                 return -EINVAL;
 439
 440         wm8994->retune_mobile_cfg[block] = value;
 441
 442         wm8994_set_retune_mobile(codec, block);
 443
 444         return 0;
 445 }
 446
 447 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 448                                          struct snd_ctl_elem_value *ucontrol)
 449 {
 450         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 451         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 452         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 453
 454         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 455
 456         return 0;
 457 }
 458
 459 static const char *aif_chan_src_text[] = {
 460         "Left", "Right"
 461 };
 462
 463 static const struct soc_enum aif1adcl_src =
 464         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 465
 466 static const struct soc_enum aif1adcr_src =
 467         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 468
 469 static const struct soc_enum aif2adcl_src =
 470         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 471
 472 static const struct soc_enum aif2adcr_src =
 473         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 474
 475 static const struct soc_enum aif1dacl_src =
 476         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 477
 478 static const struct soc_enum aif1dacr_src =
 479         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 480
 481 static const struct soc_enum aif2dacl_src =
 482         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 483
 484 static const struct soc_enum aif2dacr_src =
 485         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 486
 487 static const char *osr_text[] = {
 488         "Low Power", "High Performance",
 489 };
 490
 491 static const struct soc_enum dac_osr =
 492         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 493
 494 static const struct soc_enum adc_osr =
 495         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 496
 497 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 498 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 499                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 500                  1, 119, 0, digital_tlv),
 501 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 502                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 503                  1, 119, 0, digital_tlv),
 504 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 505                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 506                  1, 119, 0, digital_tlv),
 507
 508 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 509 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 510 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 511 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 512
 513 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 514 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 515 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 516 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 517
 518 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 519                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 520 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 521                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 522 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 523                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 524
 525 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 526 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 527
 528 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 529 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 530 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 531
 532 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 533 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 534 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 535
 536 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 537 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 538 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 539
 540 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 541 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 542 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 543
 544 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 545                5, 12, 0, st_tlv),
 546 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 547                0, 12, 0, st_tlv),
 548 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 549                5, 12, 0, st_tlv),
 550 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 551                0, 12, 0, st_tlv),
 552 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 553 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 554
 555 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 556 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 557
 558 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 559 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 560
 561 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 562 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 563
 564 SOC_ENUM("ADC OSR", adc_osr),
 565 SOC_ENUM("DAC OSR", dac_osr),
 566
 567 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 568                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 569 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 570              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 571
 572 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 573                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 574 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 575              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 576
 577 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 578                6, 1, 1, wm_hubs_spkmix_tlv),
 579 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 580                2, 1, 1, wm_hubs_spkmix_tlv),
 581
 582 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 583                6, 1, 1, wm_hubs_spkmix_tlv),
 584 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 585                2, 1, 1, wm_hubs_spkmix_tlv),
 586
 587 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 588                10, 15, 0, wm8994_3d_tlv),
 589 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 590            8, 1, 0),
 591 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 592                10, 15, 0, wm8994_3d_tlv),
 593 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 594            8, 1, 0),
 595 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 596                10, 15, 0, wm8994_3d_tlv),
 597 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 598            8, 1, 0),
 599 };
 600
 601 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 602 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 603                eq_tlv),
 604 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 605                eq_tlv),
 606 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 607                eq_tlv),
 608 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 609                eq_tlv),
 610 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 611                eq_tlv),
 612
 613 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 614                eq_tlv),
 615 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 616                eq_tlv),
 617 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 618                eq_tlv),
 619 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 620                eq_tlv),
 621 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 622                eq_tlv),
 623
 624 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 625                eq_tlv),
 626 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 627                eq_tlv),
 628 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 629                eq_tlv),
 630 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 631                eq_tlv),
 632 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 633                eq_tlv),
 634 };
 635
 636 static const char *wm8958_ng_text[] = {
 637         "30ms", "125ms", "250ms", "500ms",
 638 };
 639
 640 static const struct soc_enum wm8958_aif1dac1_ng_hold =
 641         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
 642                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
 643
 644 static const struct soc_enum wm8958_aif1dac2_ng_hold =
 645         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
 646                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
 647
 648 static const struct soc_enum wm8958_aif2dac_ng_hold =
 649         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
 650                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
 651
 652 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 653 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 654
 655 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 656            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 657 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 658 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 659                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 660                7, 1, ng_tlv),
 661
 662 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 663            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 664 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 665 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 666                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 667                7, 1, ng_tlv),
 668
 669 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 670            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 671 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 672 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 673                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 674                7, 1, ng_tlv),
 675 };
 676
 677 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 678 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 679                mixin_boost_tlv),
 680 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 681                mixin_boost_tlv),
 682 };
 683
 684 /* We run all mode setting through a function to enforce audio mode */
 685 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
 686 {
 687         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 688
 689         if (wm8994->active_refcount)
 690                 mode = WM1811_JACKDET_MODE_AUDIO;
 691
 692         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 693                             WM1811_JACKDET_MODE_MASK, mode);
 694
 695         if (mode == WM1811_JACKDET_MODE_MIC)
 696                 msleep(2);
 697 }
 698
 699 static void active_reference(struct snd_soc_codec *codec)
 700 {
 701         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 702
 703         mutex_lock(&wm8994->accdet_lock);
 704
 705         wm8994->active_refcount++;
 706
 707         dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
 708                 wm8994->active_refcount);
 709
 710         if (wm8994->active_refcount == 1) {
 711                 /* If we're using jack detection go into audio mode */
 712                 if (wm8994->jackdet && wm8994->jack_cb) {
 713                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 714                                             WM1811_JACKDET_MODE_MASK,
 715                                             WM1811_JACKDET_MODE_AUDIO);
 716                         msleep(2);
 717                 }
 718         }
 719
 720         mutex_unlock(&wm8994->accdet_lock);
 721 }
 722
 723 static void active_dereference(struct snd_soc_codec *codec)
 724 {
 725         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 726         u16 mode;
 727
 728         mutex_lock(&wm8994->accdet_lock);
 729
 730         wm8994->active_refcount--;
 731
 732         dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
 733                 wm8994->active_refcount);
 734
 735         if (wm8994->active_refcount == 0) {
 736                 /* Go into appropriate detection only mode */
 737                 if (wm8994->jackdet && wm8994->jack_cb) {
 738                         if (wm8994->jack_mic || wm8994->mic_detecting)
 739                                 mode = WM1811_JACKDET_MODE_MIC;
 740                         else
 741                                 mode = WM1811_JACKDET_MODE_JACK;
 742
 743                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 744                                             WM1811_JACKDET_MODE_MASK,
 745                                             mode);
 746                 }
 747         }
 748
 749         mutex_unlock(&wm8994->accdet_lock);
 750 }
 751
 752 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 753                          struct snd_kcontrol *kcontrol, int event)
 754 {
 755         struct snd_soc_codec *codec = w->codec;
 756
 757         switch (event) {
 758         case SND_SOC_DAPM_PRE_PMU:
 759                 return configure_clock(codec);
 760
 761         case SND_SOC_DAPM_POST_PMD:
 762                 configure_clock(codec);
 763                 break;
 764         }
 765
 766         return 0;
 767 }
 768
 769 static void vmid_reference(struct snd_soc_codec *codec)
 770 {
 771         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 772
 773         pm_runtime_get_sync(codec->dev);
 774
 775         wm8994->vmid_refcount++;
 776
 777         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
 778                 wm8994->vmid_refcount);
 779
 780         if (wm8994->vmid_refcount == 1) {
 781                 /* Startup bias, VMID ramp & buffer */
 782                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 783                                     WM8994_STARTUP_BIAS_ENA |
 784                                     WM8994_VMID_BUF_ENA |
 785                                     WM8994_VMID_RAMP_MASK,
 786                                     WM8994_STARTUP_BIAS_ENA |
 787                                     WM8994_VMID_BUF_ENA |
 788                                     (0x3 << WM8994_VMID_RAMP_SHIFT));
 789
 790                 wm_hubs_vmid_ena(codec);
 791
 792                 /* Remove discharge for line out */
 793                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 794                                     WM8994_LINEOUT1_DISCH |
 795                                     WM8994_LINEOUT2_DISCH, 0);
 796
 797                 /* Main bias enable, VMID=2x40k */
 798                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 799                                     WM8994_BIAS_ENA |
 800                                     WM8994_VMID_SEL_MASK,
 801                                     WM8994_BIAS_ENA | 0x2);
 802
 803                 msleep(20);
 804         }
 805 }
 806
 807 static void vmid_dereference(struct snd_soc_codec *codec)
 808 {
 809         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 810
 811         wm8994->vmid_refcount--;
 812
 813         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
 814                 wm8994->vmid_refcount);
 815
 816         if (wm8994->vmid_refcount == 0) {
 817                 /* Switch over to startup biases */
 818                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 819                                     WM8994_BIAS_SRC |
 820                                     WM8994_STARTUP_BIAS_ENA |
 821                                     WM8994_VMID_BUF_ENA |
 822                                     WM8994_VMID_RAMP_MASK,
 823                                     WM8994_BIAS_SRC |
 824                                     WM8994_STARTUP_BIAS_ENA |
 825                                     WM8994_VMID_BUF_ENA |
 826                                     (1 << WM8994_VMID_RAMP_SHIFT));
 827
 828                 /* Disable main biases */
 829                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 830                                     WM8994_BIAS_ENA |
 831                                     WM8994_VMID_SEL_MASK, 0);
 832
 833                 /* Discharge line */
 834                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 835                                     WM8994_LINEOUT1_DISCH |
 836                                     WM8994_LINEOUT2_DISCH,
 837                                     WM8994_LINEOUT1_DISCH |
 838                                     WM8994_LINEOUT2_DISCH);
 839
 840                 msleep(5);
 841
 842                 /* Switch off startup biases */
 843                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 844                                     WM8994_BIAS_SRC |
 845                                     WM8994_STARTUP_BIAS_ENA |
 846                                     WM8994_VMID_BUF_ENA |
 847                                     WM8994_VMID_RAMP_MASK, 0);
 848         }
 849
 850         pm_runtime_put(codec->dev);
 851 }
 852
 853 static int vmid_event(struct snd_soc_dapm_widget *w,
 854                       struct snd_kcontrol *kcontrol, int event)
 855 {
 856         struct snd_soc_codec *codec = w->codec;
 857
 858         switch (event) {
 859         case SND_SOC_DAPM_PRE_PMU:
 860                 vmid_reference(codec);
 861                 break;
 862
 863         case SND_SOC_DAPM_POST_PMD:
 864                 vmid_dereference(codec);
 865                 break;
 866         }
 867
 868         return 0;
 869 }
 870
 871 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 872 {
 873         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 874         int enable = 1;
 875         int source = 0;  /* GCC flow analysis can't track enable */
 876         int reg, reg_r;
 877
 878         /* Only support direct DAC->headphone paths */
 879         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 880         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 881                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 882                 enable = 0;
 883         }
 884
 885         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 886         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 887                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 888                 enable = 0;
 889         }
 890
 891         /* We also need the same setting for L/R and only one path */
 892         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 893         switch (reg) {
 894         case WM8994_AIF2DACL_TO_DAC1L:
 895                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 896                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 897                 break;
 898         case WM8994_AIF1DAC2L_TO_DAC1L:
 899                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 900                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 901                 break;
 902         case WM8994_AIF1DAC1L_TO_DAC1L:
 903                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 904                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 905                 break;
 906         default:
 907                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 908                 enable = 0;
 909                 break;
 910         }
 911
 912         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 913         if (reg_r != reg) {
 914                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 915                 enable = 0;
 916         }
 917
 918         if (enable) {
 919                 dev_dbg(codec->dev, "Class W enabled\n");
 920                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 921                                     WM8994_CP_DYN_PWR |
 922                                     WM8994_CP_DYN_SRC_SEL_MASK,
 923                                     source | WM8994_CP_DYN_PWR);
 924                 wm8994->hubs.class_w = true;
 925
 926         } else {
 927                 dev_dbg(codec->dev, "Class W disabled\n");
 928                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 929                                     WM8994_CP_DYN_PWR, 0);
 930                 wm8994->hubs.class_w = false;
 931         }
 932 }
 933
 934 static int late_enable_ev(struct snd_soc_dapm_widget *w,
 935                           struct snd_kcontrol *kcontrol, int event)
 936 {
 937         struct snd_soc_codec *codec = w->codec;
 938         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 939
 940         switch (event) {
 941         case SND_SOC_DAPM_PRE_PMU:
 942                 if (wm8994->aif1clk_enable) {
 943                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 944                                             WM8994_AIF1CLK_ENA_MASK,
 945                                             WM8994_AIF1CLK_ENA);
 946                         wm8994->aif1clk_enable = 0;
 947                 }
 948                 if (wm8994->aif2clk_enable) {
 949                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 950                                             WM8994_AIF2CLK_ENA_MASK,
 951                                             WM8994_AIF2CLK_ENA);
 952                         wm8994->aif2clk_enable = 0;
 953                 }
 954                 break;
 955         }
 956
 957         /* We may also have postponed startup of DSP, handle that. */
 958         wm8958_aif_ev(w, kcontrol, event);
 959
 960         return 0;
 961 }
 962
 963 static int late_disable_ev(struct snd_soc_dapm_widget *w,
 964                            struct snd_kcontrol *kcontrol, int event)
 965 {
 966         struct snd_soc_codec *codec = w->codec;
 967         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 968
 969         switch (event) {
 970         case SND_SOC_DAPM_POST_PMD:
 971                 if (wm8994->aif1clk_disable) {
 972                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 973                                             WM8994_AIF1CLK_ENA_MASK, 0);
 974                         wm8994->aif1clk_disable = 0;
 975                 }
 976                 if (wm8994->aif2clk_disable) {
 977                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 978                                             WM8994_AIF2CLK_ENA_MASK, 0);
 979                         wm8994->aif2clk_disable = 0;
 980                 }
 981                 break;
 982         }
 983
 984         return 0;
 985 }
 986
 987 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
 988                       struct snd_kcontrol *kcontrol, int event)
 989 {
 990         struct snd_soc_codec *codec = w->codec;
 991         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 992
 993         switch (event) {
 994         case SND_SOC_DAPM_PRE_PMU:
 995                 wm8994->aif1clk_enable = 1;
 996                 break;
 997         case SND_SOC_DAPM_POST_PMD:
 998                 wm8994->aif1clk_disable = 1;
 999                 break;
1000         }
1001
1002         return 0;
1003 }
1004
1005 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1006                       struct snd_kcontrol *kcontrol, int event)
1007 {
1008         struct snd_soc_codec *codec = w->codec;
1009         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1010
1011         switch (event) {
1012         case SND_SOC_DAPM_PRE_PMU:
1013                 wm8994->aif2clk_enable = 1;
1014                 break;
1015         case SND_SOC_DAPM_POST_PMD:
1016                 wm8994->aif2clk_disable = 1;
1017                 break;
1018         }
1019
1020         return 0;
1021 }
1022
1023 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1024                       struct snd_kcontrol *kcontrol, int event)
1025 {
1026         late_enable_ev(w, kcontrol, event);
1027         return 0;
1028 }
1029
1030 static int micbias_ev(struct snd_soc_dapm_widget *w,
1031                       struct snd_kcontrol *kcontrol, int event)
1032 {
1033         late_enable_ev(w, kcontrol, event);
1034         return 0;
1035 }
1036
1037 static int dac_ev(struct snd_soc_dapm_widget *w,
1038                   struct snd_kcontrol *kcontrol, int event)
1039 {
1040         struct snd_soc_codec *codec = w->codec;
1041         unsigned int mask = 1 << w->shift;
1042
1043         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1044                             mask, mask);
1045         return 0;
1046 }
1047
1048 static const char *hp_mux_text[] = {
1049         "Mixer",
1050         "DAC",
1051 };
1052
1053 #define WM8994_HP_ENUM(xname, xenum) \
1054 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1055         .info = snd_soc_info_enum_double, \
1056         .get = snd_soc_dapm_get_enum_double, \
1057         .put = wm8994_put_hp_enum, \
1058         .private_value = (unsigned long)&xenum }
1059
1060 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1061                               struct snd_ctl_elem_value *ucontrol)
1062 {
1063         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1064         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1065         struct snd_soc_codec *codec = w->codec;
1066         int ret;
1067
1068         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1069
1070         wm8994_update_class_w(codec);
1071
1072         return ret;
1073 }
1074
1075 static const struct soc_enum hpl_enum =
1076         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1077
1078 static const struct snd_kcontrol_new hpl_mux =
1079         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1080
1081 static const struct soc_enum hpr_enum =
1082         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1083
1084 static const struct snd_kcontrol_new hpr_mux =
1085         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1086
1087 static const char *adc_mux_text[] = {
1088         "ADC",
1089         "DMIC",
1090 };
1091
1092 static const struct soc_enum adc_enum =
1093         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1094
1095 static const struct snd_kcontrol_new adcl_mux =
1096         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1097
1098 static const struct snd_kcontrol_new adcr_mux =
1099         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1100
1101 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1102 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1103 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1104 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1105 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1106 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1107 };
1108
1109 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1110 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1111 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1112 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1113 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1114 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1115 };
1116
1117 /* Debugging; dump chip status after DAPM transitions */
1118 static int post_ev(struct snd_soc_dapm_widget *w,
1119             struct snd_kcontrol *kcontrol, int event)
1120 {
1121         struct snd_soc_codec *codec = w->codec;
1122         dev_dbg(codec->dev, "SRC status: %x\n",
1123                 snd_soc_read(codec,
1124                              WM8994_RATE_STATUS));
1125         return 0;
1126 }
1127
1128 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1129 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1130                 1, 1, 0),
1131 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1132                 0, 1, 0),
1133 };
1134
1135 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1136 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1137                 1, 1, 0),
1138 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1139                 0, 1, 0),
1140 };
1141
1142 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1143 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1144                 1, 1, 0),
1145 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1146                 0, 1, 0),
1147 };
1148
1149 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1150 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1151                 1, 1, 0),
1152 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1153                 0, 1, 0),
1154 };
1155
1156 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1157 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1158                 5, 1, 0),
1159 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1160                 4, 1, 0),
1161 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1162                 2, 1, 0),
1163 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1164                 1, 1, 0),
1165 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1166                 0, 1, 0),
1167 };
1168
1169 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1170 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1171                 5, 1, 0),
1172 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1173                 4, 1, 0),
1174 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1175                 2, 1, 0),
1176 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1177                 1, 1, 0),
1178 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1179                 0, 1, 0),
1180 };
1181
1182 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1183 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1184         .info = snd_soc_info_volsw, \
1185         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1186         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1187
1188 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1189                               struct snd_ctl_elem_value *ucontrol)
1190 {
1191         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1192         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1193         struct snd_soc_codec *codec = w->codec;
1194         int ret;
1195
1196         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1197
1198         wm8994_update_class_w(codec);
1199
1200         return ret;
1201 }
1202
1203 static const struct snd_kcontrol_new dac1l_mix[] = {
1204 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1205                       5, 1, 0),
1206 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1207                       4, 1, 0),
1208 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1209                       2, 1, 0),
1210 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1211                       1, 1, 0),
1212 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1213                       0, 1, 0),
1214 };
1215
1216 static const struct snd_kcontrol_new dac1r_mix[] = {
1217 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1218                       5, 1, 0),
1219 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1220                       4, 1, 0),
1221 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1222                       2, 1, 0),
1223 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1224                       1, 1, 0),
1225 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1226                       0, 1, 0),
1227 };
1228
1229 static const char *sidetone_text[] = {
1230         "ADC/DMIC1", "DMIC2",
1231 };
1232
1233 static const struct soc_enum sidetone1_enum =
1234         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1235
1236 static const struct snd_kcontrol_new sidetone1_mux =
1237         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1238
1239 static const struct soc_enum sidetone2_enum =
1240         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1241
1242 static const struct snd_kcontrol_new sidetone2_mux =
1243         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1244
1245 static const char *aif1dac_text[] = {
1246         "AIF1DACDAT", "AIF3DACDAT",
1247 };
1248
1249 static const struct soc_enum aif1dac_enum =
1250         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1251
1252 static const struct snd_kcontrol_new aif1dac_mux =
1253         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1254
1255 static const char *aif2dac_text[] = {
1256         "AIF2DACDAT", "AIF3DACDAT",
1257 };
1258
1259 static const struct soc_enum aif2dac_enum =
1260         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1261
1262 static const struct snd_kcontrol_new aif2dac_mux =
1263         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1264
1265 static const char *aif2adc_text[] = {
1266         "AIF2ADCDAT", "AIF3DACDAT",
1267 };
1268
1269 static const struct soc_enum aif2adc_enum =
1270         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1271
1272 static const struct snd_kcontrol_new aif2adc_mux =
1273         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1274
1275 static const char *aif3adc_text[] = {
1276         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1277 };
1278
1279 static const struct soc_enum wm8994_aif3adc_enum =
1280         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1281
1282 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1283         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1284
1285 static const struct soc_enum wm8958_aif3adc_enum =
1286         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1287
1288 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1289         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1290
1291 static const char *mono_pcm_out_text[] = {
1292         "None", "AIF2ADCL", "AIF2ADCR",
1293 };
1294
1295 static const struct soc_enum mono_pcm_out_enum =
1296         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1297
1298 static const struct snd_kcontrol_new mono_pcm_out_mux =
1299         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1300
1301 static const char *aif2dac_src_text[] = {
1302         "AIF2", "AIF3",
1303 };
1304
1305 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1306 static const struct soc_enum aif2dacl_src_enum =
1307         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1308
1309 static const struct snd_kcontrol_new aif2dacl_src_mux =
1310         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1311
1312 static const struct soc_enum aif2dacr_src_enum =
1313         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1314
1315 static const struct snd_kcontrol_new aif2dacr_src_mux =
1316         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1317
1318 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1319 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1320         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1321 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1322         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1323
1324 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1325         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1326 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1327         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1328 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1329         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1330 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1331         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1332 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1333         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1334
1335 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1336                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1337                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1338 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1339                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1340                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1341 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1342                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1343 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1344                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1345
1346 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1347 };
1348
1349 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1350 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1351 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1352 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1353 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1354                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1355 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1356                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1357 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1358 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1359 };
1360
1361 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1362 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1363         dac_ev, SND_SOC_DAPM_PRE_PMU),
1364 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1365         dac_ev, SND_SOC_DAPM_PRE_PMU),
1366 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1367         dac_ev, SND_SOC_DAPM_PRE_PMU),
1368 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1369         dac_ev, SND_SOC_DAPM_PRE_PMU),
1370 };
1371
1372 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1373 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1374 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1375 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1376 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1377 };
1378
1379 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1380 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1381                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1382 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1383                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1384 };
1385
1386 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1387 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1388 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1389 };
1390
1391 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1392 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1393 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1394 SND_SOC_DAPM_INPUT("Clock"),
1395
1396 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1397                       SND_SOC_DAPM_PRE_PMU),
1398 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1399                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1400
1401 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1402                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1403
1404 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1405 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1406 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1407
1408 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1409                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1410 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1411                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1412 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1413                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1414                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1415 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1416                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1417                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1418
1419 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1420                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1421 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1422                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1423 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1424                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1425                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1426 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1427                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1428                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1429
1430 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1431                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1432 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1433                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1434
1435 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1436                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1437 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1438                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1439
1440 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1441                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1442 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1443                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1444
1445 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1446 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1447
1448 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1449                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1450 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1451                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1452
1453 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1454                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1455 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1456                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1457 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1458                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1459                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1460 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1461                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1462                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1463
1464 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1465 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1466 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1467 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1468
1469 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1470 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1471 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1472
1473 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1474 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1475
1476 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1477
1478 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1479 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1480 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1481 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1482
1483 /* Power is done with the muxes since the ADC power also controls the
1484  * downsampling chain, the chip will automatically manage the analogue
1485  * specific portions.
1486  */
1487 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1488 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1489
1490 SND_SOC_DAPM_POST("Debug log", post_ev),
1491 };
1492
1493 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1494 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1495 };
1496
1497 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1498 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1499 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1500 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1501 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1502 };
1503
1504 static const struct snd_soc_dapm_route intercon[] = {
1505         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1506         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1507
1508         { "DSP1CLK", NULL, "CLK_SYS" },
1509         { "DSP2CLK", NULL, "CLK_SYS" },
1510         { "DSPINTCLK", NULL, "CLK_SYS" },
1511
1512         { "AIF1ADC1L", NULL, "AIF1CLK" },
1513         { "AIF1ADC1L", NULL, "DSP1CLK" },
1514         { "AIF1ADC1R", NULL, "AIF1CLK" },
1515         { "AIF1ADC1R", NULL, "DSP1CLK" },
1516         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1517
1518         { "AIF1DAC1L", NULL, "AIF1CLK" },
1519         { "AIF1DAC1L", NULL, "DSP1CLK" },
1520         { "AIF1DAC1R", NULL, "AIF1CLK" },
1521         { "AIF1DAC1R", NULL, "DSP1CLK" },
1522         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1523
1524         { "AIF1ADC2L", NULL, "AIF1CLK" },
1525         { "AIF1ADC2L", NULL, "DSP1CLK" },
1526         { "AIF1ADC2R", NULL, "AIF1CLK" },
1527         { "AIF1ADC2R", NULL, "DSP1CLK" },
1528         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1529
1530         { "AIF1DAC2L", NULL, "AIF1CLK" },
1531         { "AIF1DAC2L", NULL, "DSP1CLK" },
1532         { "AIF1DAC2R", NULL, "AIF1CLK" },
1533         { "AIF1DAC2R", NULL, "DSP1CLK" },
1534         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1535
1536         { "AIF2ADCL", NULL, "AIF2CLK" },
1537         { "AIF2ADCL", NULL, "DSP2CLK" },
1538         { "AIF2ADCR", NULL, "AIF2CLK" },
1539         { "AIF2ADCR", NULL, "DSP2CLK" },
1540         { "AIF2ADCR", NULL, "DSPINTCLK" },
1541
1542         { "AIF2DACL", NULL, "AIF2CLK" },
1543         { "AIF2DACL", NULL, "DSP2CLK" },
1544         { "AIF2DACR", NULL, "AIF2CLK" },
1545         { "AIF2DACR", NULL, "DSP2CLK" },
1546         { "AIF2DACR", NULL, "DSPINTCLK" },
1547
1548         { "DMIC1L", NULL, "DMIC1DAT" },
1549         { "DMIC1L", NULL, "CLK_SYS" },
1550         { "DMIC1R", NULL, "DMIC1DAT" },
1551         { "DMIC1R", NULL, "CLK_SYS" },
1552         { "DMIC2L", NULL, "DMIC2DAT" },
1553         { "DMIC2L", NULL, "CLK_SYS" },
1554         { "DMIC2R", NULL, "DMIC2DAT" },
1555         { "DMIC2R", NULL, "CLK_SYS" },
1556
1557         { "ADCL", NULL, "AIF1CLK" },
1558         { "ADCL", NULL, "DSP1CLK" },
1559         { "ADCL", NULL, "DSPINTCLK" },
1560
1561         { "ADCR", NULL, "AIF1CLK" },
1562         { "ADCR", NULL, "DSP1CLK" },
1563         { "ADCR", NULL, "DSPINTCLK" },
1564
1565         { "ADCL Mux", "ADC", "ADCL" },
1566         { "ADCL Mux", "DMIC", "DMIC1L" },
1567         { "ADCR Mux", "ADC", "ADCR" },
1568         { "ADCR Mux", "DMIC", "DMIC1R" },
1569
1570         { "DAC1L", NULL, "AIF1CLK" },
1571         { "DAC1L", NULL, "DSP1CLK" },
1572         { "DAC1L", NULL, "DSPINTCLK" },
1573
1574         { "DAC1R", NULL, "AIF1CLK" },
1575         { "DAC1R", NULL, "DSP1CLK" },
1576         { "DAC1R", NULL, "DSPINTCLK" },
1577
1578         { "DAC2L", NULL, "AIF2CLK" },
1579         { "DAC2L", NULL, "DSP2CLK" },
1580         { "DAC2L", NULL, "DSPINTCLK" },
1581
1582         { "DAC2R", NULL, "AIF2DACR" },
1583         { "DAC2R", NULL, "AIF2CLK" },
1584         { "DAC2R", NULL, "DSP2CLK" },
1585         { "DAC2R", NULL, "DSPINTCLK" },
1586
1587         { "TOCLK", NULL, "CLK_SYS" },
1588
1589         /* AIF1 outputs */
1590         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1591         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1592         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1593
1594         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1595         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1596         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1597
1598         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1599         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1600         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1601
1602         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1603         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1604         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1605
1606         /* Pin level routing for AIF3 */
1607         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1608         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1609         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1610         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1611
1612         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1613         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1614         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1615         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1616         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1617         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1618         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1619
1620         /* DAC1 inputs */
1621         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1622         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1623         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1624         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1625         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1626
1627         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1628         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1629         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1630         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1631         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1632
1633         /* DAC2/AIF2 outputs  */
1634         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1635         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1636         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1637         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1638         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1639         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1640
1641         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1642         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1643         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1644         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1645         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1646         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1647
1648         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1649         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1650         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1651         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1652
1653         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1654
1655         /* AIF3 output */
1656         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1657         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1658         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1659         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1660         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1661         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1662         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1663         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1664
1665         /* Sidetone */
1666         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1667         { "Left Sidetone", "DMIC2", "DMIC2L" },
1668         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1669         { "Right Sidetone", "DMIC2", "DMIC2R" },
1670
1671         /* Output stages */
1672         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1673         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1674
1675         { "SPKL", "DAC1 Switch", "DAC1L" },
1676         { "SPKL", "DAC2 Switch", "DAC2L" },
1677
1678         { "SPKR", "DAC1 Switch", "DAC1R" },
1679         { "SPKR", "DAC2 Switch", "DAC2R" },
1680
1681         { "Left Headphone Mux", "DAC", "DAC1L" },
1682         { "Right Headphone Mux", "DAC", "DAC1R" },
1683 };
1684
1685 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1686         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1687         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1688         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1689         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1690         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1691         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1692         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1693         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1694 };
1695
1696 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1697         { "DAC1L", NULL, "DAC1L Mixer" },
1698         { "DAC1R", NULL, "DAC1R Mixer" },
1699         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1700         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1701 };
1702
1703 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1704         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1705         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1706         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1707         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1708         { "MICBIAS1", NULL, "CLK_SYS" },
1709         { "MICBIAS1", NULL, "MICBIAS Supply" },
1710         { "MICBIAS2", NULL, "CLK_SYS" },
1711         { "MICBIAS2", NULL, "MICBIAS Supply" },
1712 };
1713
1714 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1715         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1716         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1717         { "MICBIAS1", NULL, "VMID" },
1718         { "MICBIAS2", NULL, "VMID" },
1719 };
1720
1721 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1722         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1723         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1724
1725         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1726         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1727         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1728         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1729
1730         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1731         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1732
1733         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1734 };
1735
1736 /* The size in bits of the FLL divide multiplied by 10
1737  * to allow rounding later */
1738 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1739
1740 struct fll_div {
1741         u16 outdiv;
1742         u16 n;
1743         u16 k;
1744         u16 clk_ref_div;
1745         u16 fll_fratio;
1746 };
1747
1748 static int wm8994_get_fll_config(struct fll_div *fll,
1749                                  int freq_in, int freq_out)
1750 {
1751         u64 Kpart;
1752         unsigned int K, Ndiv, Nmod;
1753
1754         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1755
1756         /* Scale the input frequency down to <= 13.5MHz */
1757         fll->clk_ref_div = 0;
1758         while (freq_in > 13500000) {
1759                 fll->clk_ref_div++;
1760                 freq_in /= 2;
1761
1762                 if (fll->clk_ref_div > 3)
1763                         return -EINVAL;
1764         }
1765         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1766
1767         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1768         fll->outdiv = 3;
1769         while (freq_out * (fll->outdiv + 1) < 90000000) {
1770                 fll->outdiv++;
1771                 if (fll->outdiv > 63)
1772                         return -EINVAL;
1773         }
1774         freq_out *= fll->outdiv + 1;
1775         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1776
1777         if (freq_in > 1000000) {
1778                 fll->fll_fratio = 0;
1779         } else if (freq_in > 256000) {
1780                 fll->fll_fratio = 1;
1781                 freq_in *= 2;
1782         } else if (freq_in > 128000) {
1783                 fll->fll_fratio = 2;
1784                 freq_in *= 4;
1785         } else if (freq_in > 64000) {
1786                 fll->fll_fratio = 3;
1787                 freq_in *= 8;
1788         } else {
1789                 fll->fll_fratio = 4;
1790                 freq_in *= 16;
1791         }
1792         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1793
1794         /* Now, calculate N.K */
1795         Ndiv = freq_out / freq_in;
1796
1797         fll->n = Ndiv;
1798         Nmod = freq_out % freq_in;
1799         pr_debug("Nmod=%d\n", Nmod);
1800
1801         /* Calculate fractional part - scale up so we can round. */
1802         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1803
1804         do_div(Kpart, freq_in);
1805
1806         K = Kpart & 0xFFFFFFFF;
1807
1808         if ((K % 10) >= 5)
1809                 K += 5;
1810
1811         /* Move down to proper range now rounding is done */
1812         fll->k = K / 10;
1813
1814         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1815
1816         return 0;
1817 }
1818
1819 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1820                           unsigned int freq_in, unsigned int freq_out)
1821 {
1822         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1823         struct wm8994 *control = wm8994->wm8994;
1824         int reg_offset, ret;
1825         struct fll_div fll;
1826         u16 reg, aif1, aif2;
1827         unsigned long timeout;
1828         bool was_enabled;
1829
1830         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1831                 & WM8994_AIF1CLK_ENA;
1832
1833         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1834                 & WM8994_AIF2CLK_ENA;
1835
1836         switch (id) {
1837         case WM8994_FLL1:
1838                 reg_offset = 0;
1839                 id = 0;
1840                 break;
1841         case WM8994_FLL2:
1842                 reg_offset = 0x20;
1843                 id = 1;
1844                 break;
1845         default:
1846                 return -EINVAL;
1847         }
1848
1849         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1850         was_enabled = reg & WM8994_FLL1_ENA;
1851
1852         switch (src) {
1853         case 0:
1854                 /* Allow no source specification when stopping */
1855                 if (freq_out)
1856                         return -EINVAL;
1857                 src = wm8994->fll[id].src;
1858                 break;
1859         case WM8994_FLL_SRC_MCLK1:
1860         case WM8994_FLL_SRC_MCLK2:
1861         case WM8994_FLL_SRC_LRCLK:
1862         case WM8994_FLL_SRC_BCLK:
1863                 break;
1864         default:
1865                 return -EINVAL;
1866         }
1867
1868         /* Are we changing anything? */
1869         if (wm8994->fll[id].src == src &&
1870             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1871                 return 0;
1872
1873         /* If we're stopping the FLL redo the old config - no
1874          * registers will actually be written but we avoid GCC flow
1875          * analysis bugs spewing warnings.
1876          */
1877         if (freq_out)
1878                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1879         else
1880                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1881                                             wm8994->fll[id].out);
1882         if (ret < 0)
1883                 return ret;
1884
1885         /* Gate the AIF clocks while we reclock */
1886         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1887                             WM8994_AIF1CLK_ENA, 0);
1888         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1889                             WM8994_AIF2CLK_ENA, 0);
1890
1891         /* We always need to disable the FLL while reconfiguring */
1892         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1893                             WM8994_FLL1_ENA, 0);
1894
1895         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1896                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1897         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1898                             WM8994_FLL1_OUTDIV_MASK |
1899                             WM8994_FLL1_FRATIO_MASK, reg);
1900
1901         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1902
1903         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1904                             WM8994_FLL1_N_MASK,
1905                                     fll.n << WM8994_FLL1_N_SHIFT);
1906
1907         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1908                             WM8994_FLL1_REFCLK_DIV_MASK |
1909                             WM8994_FLL1_REFCLK_SRC_MASK,
1910                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1911                             (src - 1));
1912
1913         /* Clear any pending completion from a previous failure */
1914         try_wait_for_completion(&wm8994->fll_locked[id]);
1915
1916         /* Enable (with fractional mode if required) */
1917         if (freq_out) {
1918                 /* Enable VMID if we need it */
1919                 if (!was_enabled) {
1920                         active_reference(codec);
1921
1922                         switch (control->type) {
1923                         case WM8994:
1924                                 vmid_reference(codec);
1925                                 break;
1926                         case WM8958:
1927                                 if (wm8994->revision < 1)
1928                                         vmid_reference(codec);
1929                                 break;
1930                         default:
1931                                 break;
1932                         }
1933                 }
1934
1935                 if (fll.k)
1936                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1937                 else
1938                         reg = WM8994_FLL1_ENA;
1939                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1940                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1941                                     reg);
1942
1943                 if (wm8994->fll_locked_irq) {
1944                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1945                                                               msecs_to_jiffies(10));
1946                         if (timeout == 0)
1947                                 dev_warn(codec->dev,
1948                                          "Timed out waiting for FLL lock\n");
1949                 } else {
1950                         msleep(5);
1951                 }
1952         } else {
1953                 if (was_enabled) {
1954                         switch (control->type) {
1955                         case WM8994:
1956                                 vmid_dereference(codec);
1957                                 break;
1958                         case WM8958:
1959                                 if (wm8994->revision < 1)
1960                                         vmid_dereference(codec);
1961                                 break;
1962                         default:
1963                                 break;
1964                         }
1965
1966                         active_dereference(codec);
1967                 }
1968         }
1969
1970         wm8994->fll[id].in = freq_in;
1971         wm8994->fll[id].out = freq_out;
1972         wm8994->fll[id].src = src;
1973
1974         /* Enable any gated AIF clocks */
1975         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1976                             WM8994_AIF1CLK_ENA, aif1);
1977         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1978                             WM8994_AIF2CLK_ENA, aif2);
1979
1980         configure_clock(codec);
1981
1982         return 0;
1983 }
1984
1985 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1986 {
1987         struct completion *completion = data;
1988
1989         complete(completion);
1990
1991         return IRQ_HANDLED;
1992 }
1993
1994 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1995
1996 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1997                           unsigned int freq_in, unsigned int freq_out)
1998 {
1999         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2000 }
2001
2002 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2003                 int clk_id, unsigned int freq, int dir)
2004 {
2005         struct snd_soc_codec *codec = dai->codec;
2006         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2007         int i;
2008
2009         switch (dai->id) {
2010         case 1:
2011         case 2:
2012                 break;
2013
2014         default:
2015                 /* AIF3 shares clocking with AIF1/2 */
2016                 return -EINVAL;
2017         }
2018
2019         switch (clk_id) {
2020         case WM8994_SYSCLK_MCLK1:
2021                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2022                 wm8994->mclk[0] = freq;
2023                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2024                         dai->id, freq);
2025                 break;
2026
2027         case WM8994_SYSCLK_MCLK2:
2028                 /* TODO: Set GPIO AF */
2029                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2030                 wm8994->mclk[1] = freq;
2031                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2032                         dai->id, freq);
2033                 break;
2034
2035         case WM8994_SYSCLK_FLL1:
2036                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2037                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2038                 break;
2039
2040         case WM8994_SYSCLK_FLL2:
2041                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2042                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2043                 break;
2044
2045         case WM8994_SYSCLK_OPCLK:
2046                 /* Special case - a division (times 10) is given and
2047                  * no effect on main clocking.
2048                  */
2049                 if (freq) {
2050                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2051                                 if (opclk_divs[i] == freq)
2052                                         break;
2053                         if (i == ARRAY_SIZE(opclk_divs))
2054                                 return -EINVAL;
2055                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2056                                             WM8994_OPCLK_DIV_MASK, i);
2057                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2058                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2059                 } else {
2060                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2061                                             WM8994_OPCLK_ENA, 0);
2062                 }
2063
2064         default:
2065                 return -EINVAL;
2066         }
2067
2068         configure_clock(codec);
2069
2070         return 0;
2071 }
2072
2073 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2074                                  enum snd_soc_bias_level level)
2075 {
2076         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2077         struct wm8994 *control = wm8994->wm8994;
2078
2079         wm_hubs_set_bias_level(codec, level);
2080
2081         switch (level) {
2082         case SND_SOC_BIAS_ON:
2083                 break;
2084
2085         case SND_SOC_BIAS_PREPARE:
2086                 /* MICBIAS into regulating mode */
2087                 switch (control->type) {
2088                 case WM8958:
2089                 case WM1811:
2090                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2091                                             WM8958_MICB1_MODE, 0);
2092                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2093                                             WM8958_MICB2_MODE, 0);
2094                         break;
2095                 default:
2096                         break;
2097                 }
2098
2099                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2100                         active_reference(codec);
2101                 break;
2102
2103         case SND_SOC_BIAS_STANDBY:
2104                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2105                         switch (control->type) {
2106                         case WM8994:
2107                                 if (wm8994->revision < 4) {
2108                                         /* Tweak DC servo and DSP
2109                                          * configuration for improved
2110                                          * performance. */
2111                                         snd_soc_write(codec, 0x102, 0x3);
2112                                         snd_soc_write(codec, 0x56, 0x3);
2113                                         snd_soc_write(codec, 0x817, 0);
2114                                         snd_soc_write(codec, 0x102, 0);
2115                                 }
2116                                 break;
2117
2118                         case WM8958:
2119                                 if (wm8994->revision == 0) {
2120                                         /* Optimise performance for rev A */
2121                                         snd_soc_write(codec, 0x102, 0x3);
2122                                         snd_soc_write(codec, 0xcb, 0x81);
2123                                         snd_soc_write(codec, 0x817, 0);
2124                                         snd_soc_write(codec, 0x102, 0);
2125
2126                                         snd_soc_update_bits(codec,
2127                                                             WM8958_CHARGE_PUMP_2,
2128                                                             WM8958_CP_DISCH,
2129                                                             WM8958_CP_DISCH);
2130                                 }
2131                                 break;
2132
2133                         case WM1811:
2134                                 if (wm8994->revision < 2) {
2135                                         snd_soc_write(codec, 0x102, 0x3);
2136                                         snd_soc_write(codec, 0x5d, 0x7e);
2137                                         snd_soc_write(codec, 0x5e, 0x0);
2138                                         snd_soc_write(codec, 0x102, 0x0);
2139                                 }
2140                                 break;
2141                         }
2142
2143                         /* Discharge LINEOUT1 & 2 */
2144                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2145                                             WM8994_LINEOUT1_DISCH |
2146                                             WM8994_LINEOUT2_DISCH,
2147                                             WM8994_LINEOUT1_DISCH |
2148                                             WM8994_LINEOUT2_DISCH);
2149                 }
2150
2151                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2152                         active_dereference(codec);
2153
2154                 /* MICBIAS into bypass mode on newer devices */
2155                 switch (control->type) {
2156                 case WM8958:
2157                 case WM1811:
2158                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2159                                             WM8958_MICB1_MODE,
2160                                             WM8958_MICB1_MODE);
2161                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2162                                             WM8958_MICB2_MODE,
2163                                             WM8958_MICB2_MODE);
2164                         break;
2165                 default:
2166                         break;
2167                 }
2168                 break;
2169
2170         case SND_SOC_BIAS_OFF:
2171                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2172                         wm8994->cur_fw = NULL;
2173                 break;
2174         }
2175
2176         codec->dapm.bias_level = level;
2177
2178         return 0;
2179 }
2180
2181 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2182 {
2183         struct snd_soc_codec *codec = dai->codec;
2184         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2185         struct wm8994 *control = wm8994->wm8994;
2186         int ms_reg;
2187         int aif1_reg;
2188         int ms = 0;
2189         int aif1 = 0;
2190
2191         switch (dai->id) {
2192         case 1:
2193                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2194                 aif1_reg = WM8994_AIF1_CONTROL_1;
2195                 break;
2196         case 2:
2197                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2198                 aif1_reg = WM8994_AIF2_CONTROL_1;
2199                 break;
2200         default:
2201                 return -EINVAL;
2202         }
2203
2204         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2205         case SND_SOC_DAIFMT_CBS_CFS:
2206                 break;
2207         case SND_SOC_DAIFMT_CBM_CFM:
2208                 ms = WM8994_AIF1_MSTR;
2209                 break;
2210         default:
2211                 return -EINVAL;
2212         }
2213
2214         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2215         case SND_SOC_DAIFMT_DSP_B:
2216                 aif1 |= WM8994_AIF1_LRCLK_INV;
2217         case SND_SOC_DAIFMT_DSP_A:
2218                 aif1 |= 0x18;
2219                 break;
2220         case SND_SOC_DAIFMT_I2S:
2221                 aif1 |= 0x10;
2222                 break;
2223         case SND_SOC_DAIFMT_RIGHT_J:
2224                 break;
2225         case SND_SOC_DAIFMT_LEFT_J:
2226                 aif1 |= 0x8;
2227                 break;
2228         default:
2229                 return -EINVAL;
2230         }
2231
2232         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2233         case SND_SOC_DAIFMT_DSP_A:
2234         case SND_SOC_DAIFMT_DSP_B:
2235                 /* frame inversion not valid for DSP modes */
2236                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2237                 case SND_SOC_DAIFMT_NB_NF:
2238                         break;
2239                 case SND_SOC_DAIFMT_IB_NF:
2240                         aif1 |= WM8994_AIF1_BCLK_INV;
2241                         break;
2242                 default:
2243                         return -EINVAL;
2244                 }
2245                 break;
2246
2247         case SND_SOC_DAIFMT_I2S:
2248         case SND_SOC_DAIFMT_RIGHT_J:
2249         case SND_SOC_DAIFMT_LEFT_J:
2250                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2251                 case SND_SOC_DAIFMT_NB_NF:
2252                         break;
2253                 case SND_SOC_DAIFMT_IB_IF:
2254                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2255                         break;
2256                 case SND_SOC_DAIFMT_IB_NF:
2257                         aif1 |= WM8994_AIF1_BCLK_INV;
2258                         break;
2259                 case SND_SOC_DAIFMT_NB_IF:
2260                         aif1 |= WM8994_AIF1_LRCLK_INV;
2261                         break;
2262                 default:
2263                         return -EINVAL;
2264                 }
2265                 break;
2266         default:
2267                 return -EINVAL;
2268         }
2269
2270         /* The AIF2 format configuration needs to be mirrored to AIF3
2271          * on WM8958 if it's in use so just do it all the time. */
2272         switch (control->type) {
2273         case WM1811:
2274         case WM8958:
2275                 if (dai->id == 2)
2276                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2277                                             WM8994_AIF1_LRCLK_INV |
2278                                             WM8958_AIF3_FMT_MASK, aif1);
2279                 break;
2280
2281         default:
2282                 break;
2283         }
2284
2285         snd_soc_update_bits(codec, aif1_reg,
2286                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2287                             WM8994_AIF1_FMT_MASK,
2288                             aif1);
2289         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2290                             ms);
2291
2292         return 0;
2293 }
2294
2295 static struct {
2296         int val, rate;
2297 } srs[] = {
2298         { 0,   8000 },
2299         { 1,  11025 },
2300         { 2,  12000 },
2301         { 3,  16000 },
2302         { 4,  22050 },
2303         { 5,  24000 },
2304         { 6,  32000 },
2305         { 7,  44100 },
2306         { 8,  48000 },
2307         { 9,  88200 },
2308         { 10, 96000 },
2309 };
2310
2311 static int fs_ratios[] = {
2312         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2313 };
2314
2315 static int bclk_divs[] = {
2316         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2317         640, 880, 960, 1280, 1760, 1920
2318 };
2319
2320 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2321                             struct snd_pcm_hw_params *params,
2322                             struct snd_soc_dai *dai)
2323 {
2324         struct snd_soc_codec *codec = dai->codec;
2325         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2326         int aif1_reg;
2327         int aif2_reg;
2328         int bclk_reg;
2329         int lrclk_reg;
2330         int rate_reg;
2331         int aif1 = 0;
2332         int aif2 = 0;
2333         int bclk = 0;
2334         int lrclk = 0;
2335         int rate_val = 0;
2336         int id = dai->id - 1;
2337
2338         int i, cur_val, best_val, bclk_rate, best;
2339
2340         switch (dai->id) {
2341         case 1:
2342                 aif1_reg = WM8994_AIF1_CONTROL_1;
2343                 aif2_reg = WM8994_AIF1_CONTROL_2;
2344                 bclk_reg = WM8994_AIF1_BCLK;
2345                 rate_reg = WM8994_AIF1_RATE;
2346                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2347                     wm8994->lrclk_shared[0]) {
2348                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2349                 } else {
2350                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2351                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2352                 }
2353                 break;
2354         case 2:
2355                 aif1_reg = WM8994_AIF2_CONTROL_1;
2356                 aif2_reg = WM8994_AIF2_CONTROL_2;
2357                 bclk_reg = WM8994_AIF2_BCLK;
2358                 rate_reg = WM8994_AIF2_RATE;
2359                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2360                     wm8994->lrclk_shared[1]) {
2361                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2362                 } else {
2363                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2364                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2365                 }
2366                 break;
2367         default:
2368                 return -EINVAL;
2369         }
2370
2371         bclk_rate = params_rate(params) * 2;
2372         switch (params_format(params)) {
2373         case SNDRV_PCM_FORMAT_S16_LE:
2374                 bclk_rate *= 16;
2375                 break;
2376         case SNDRV_PCM_FORMAT_S20_3LE:
2377                 bclk_rate *= 20;
2378                 aif1 |= 0x20;
2379                 break;
2380         case SNDRV_PCM_FORMAT_S24_LE:
2381                 bclk_rate *= 24;
2382                 aif1 |= 0x40;
2383                 break;
2384         case SNDRV_PCM_FORMAT_S32_LE:
2385                 bclk_rate *= 32;
2386                 aif1 |= 0x60;
2387                 break;
2388         default:
2389                 return -EINVAL;
2390         }
2391
2392         /* Try to find an appropriate sample rate; look for an exact match. */
2393         for (i = 0; i < ARRAY_SIZE(srs); i++)
2394                 if (srs[i].rate == params_rate(params))
2395                         break;
2396         if (i == ARRAY_SIZE(srs))
2397                 return -EINVAL;
2398         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2399
2400         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2401         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2402                 dai->id, wm8994->aifclk[id], bclk_rate);
2403
2404         if (params_channels(params) == 1 &&
2405             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2406                 aif2 |= WM8994_AIF1_MONO;
2407
2408         if (wm8994->aifclk[id] == 0) {
2409                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2410                 return -EINVAL;
2411         }
2412
2413         /* AIFCLK/fs ratio; look for a close match in either direction */
2414         best = 0;
2415         best_val = abs((fs_ratios[0] * params_rate(params))
2416                        - wm8994->aifclk[id]);
2417         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2418                 cur_val = abs((fs_ratios[i] * params_rate(params))
2419                               - wm8994->aifclk[id]);
2420                 if (cur_val >= best_val)
2421                         continue;
2422                 best = i;
2423                 best_val = cur_val;
2424         }
2425         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2426                 dai->id, fs_ratios[best]);
2427         rate_val |= best;
2428
2429         /* We may not get quite the right frequency if using
2430          * approximate clocks so look for the closest match that is
2431          * higher than the target (we need to ensure that there enough
2432          * BCLKs to clock out the samples).
2433          */
2434         best = 0;
2435         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2436                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2437                 if (cur_val < 0) /* BCLK table is sorted */
2438                         break;
2439                 best = i;
2440         }
2441         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2442         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2443                 bclk_divs[best], bclk_rate);
2444         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2445
2446         lrclk = bclk_rate / params_rate(params);
2447         if (!lrclk) {
2448                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2449                         bclk_rate);
2450                 return -EINVAL;
2451         }
2452         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2453                 lrclk, bclk_rate / lrclk);
2454
2455         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2456         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2457         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2458         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2459                             lrclk);
2460         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2461                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2462
2463         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2464                 switch (dai->id) {
2465                 case 1:
2466                         wm8994->dac_rates[0] = params_rate(params);
2467                         wm8994_set_retune_mobile(codec, 0);
2468                         wm8994_set_retune_mobile(codec, 1);
2469                         break;
2470                 case 2:
2471                         wm8994->dac_rates[1] = params_rate(params);
2472                         wm8994_set_retune_mobile(codec, 2);
2473                         break;
2474                 }
2475         }
2476
2477         return 0;
2478 }
2479
2480 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2481                                  struct snd_pcm_hw_params *params,
2482                                  struct snd_soc_dai *dai)
2483 {
2484         struct snd_soc_codec *codec = dai->codec;
2485         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2486         struct wm8994 *control = wm8994->wm8994;
2487         int aif1_reg;
2488         int aif1 = 0;
2489
2490         switch (dai->id) {
2491         case 3:
2492                 switch (control->type) {
2493                 case WM1811:
2494                 case WM8958:
2495                         aif1_reg = WM8958_AIF3_CONTROL_1;
2496                         break;
2497                 default:
2498                         return 0;
2499                 }
2500         default:
2501                 return 0;
2502         }
2503
2504         switch (params_format(params)) {
2505         case SNDRV_PCM_FORMAT_S16_LE:
2506                 break;
2507         case SNDRV_PCM_FORMAT_S20_3LE:
2508                 aif1 |= 0x20;
2509                 break;
2510         case SNDRV_PCM_FORMAT_S24_LE:
2511                 aif1 |= 0x40;
2512                 break;
2513         case SNDRV_PCM_FORMAT_S32_LE:
2514                 aif1 |= 0x60;
2515                 break;
2516         default:
2517                 return -EINVAL;
2518         }
2519
2520         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2521 }
2522
2523 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2524                                 struct snd_soc_dai *dai)
2525 {
2526         struct snd_soc_codec *codec = dai->codec;
2527         int rate_reg = 0;
2528
2529         switch (dai->id) {
2530         case 1:
2531                 rate_reg = WM8994_AIF1_RATE;
2532                 break;
2533         case 2:
2534                 rate_reg = WM8994_AIF2_RATE;
2535                 break;
2536         default:
2537                 break;
2538         }
2539
2540         /* If the DAI is idle then configure the divider tree for the
2541          * lowest output rate to save a little power if the clock is
2542          * still active (eg, because it is system clock).
2543          */
2544         if (rate_reg && !dai->playback_active && !dai->capture_active)
2545                 snd_soc_update_bits(codec, rate_reg,
2546                                     WM8994_AIF1_SR_MASK |
2547                                     WM8994_AIF1CLK_RATE_MASK, 0x9);
2548 }
2549
2550 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2551 {
2552         struct snd_soc_codec *codec = codec_dai->codec;
2553         int mute_reg;
2554         int reg;
2555
2556         switch (codec_dai->id) {
2557         case 1:
2558                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2559                 break;
2560         case 2:
2561                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2562                 break;
2563         default:
2564                 return -EINVAL;
2565         }
2566
2567         if (mute)
2568                 reg = WM8994_AIF1DAC1_MUTE;
2569         else
2570                 reg = 0;
2571
2572         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2573
2574         return 0;
2575 }
2576
2577 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2578 {
2579         struct snd_soc_codec *codec = codec_dai->codec;
2580         int reg, val, mask;
2581
2582         switch (codec_dai->id) {
2583         case 1:
2584                 reg = WM8994_AIF1_MASTER_SLAVE;
2585                 mask = WM8994_AIF1_TRI;
2586                 break;
2587         case 2:
2588                 reg = WM8994_AIF2_MASTER_SLAVE;
2589                 mask = WM8994_AIF2_TRI;
2590                 break;
2591         case 3:
2592                 reg = WM8994_POWER_MANAGEMENT_6;
2593                 mask = WM8994_AIF3_TRI;
2594                 break;
2595         default:
2596                 return -EINVAL;
2597         }
2598
2599         if (tristate)
2600                 val = mask;
2601         else
2602                 val = 0;
2603
2604         return snd_soc_update_bits(codec, reg, mask, val);
2605 }
2606
2607 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2608 {
2609         struct snd_soc_codec *codec = dai->codec;
2610
2611         /* Disable the pulls on the AIF if we're using it to save power. */
2612         snd_soc_update_bits(codec, WM8994_GPIO_3,
2613                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2614         snd_soc_update_bits(codec, WM8994_GPIO_4,
2615                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2616         snd_soc_update_bits(codec, WM8994_GPIO_5,
2617                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2618
2619         return 0;
2620 }
2621
2622 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2623
2624 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2625                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2626
2627 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2628         .set_sysclk     = wm8994_set_dai_sysclk,
2629         .set_fmt        = wm8994_set_dai_fmt,
2630         .hw_params      = wm8994_hw_params,
2631         .shutdown       = wm8994_aif_shutdown,
2632         .digital_mute   = wm8994_aif_mute,
2633         .set_pll        = wm8994_set_fll,
2634         .set_tristate   = wm8994_set_tristate,
2635 };
2636
2637 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2638         .set_sysclk     = wm8994_set_dai_sysclk,
2639         .set_fmt        = wm8994_set_dai_fmt,
2640         .hw_params      = wm8994_hw_params,
2641         .shutdown       = wm8994_aif_shutdown,
2642         .digital_mute   = wm8994_aif_mute,
2643         .set_pll        = wm8994_set_fll,
2644         .set_tristate   = wm8994_set_tristate,
2645 };
2646
2647 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2648         .hw_params      = wm8994_aif3_hw_params,
2649         .set_tristate   = wm8994_set_tristate,
2650 };
2651
2652 static struct snd_soc_dai_driver wm8994_dai[] = {
2653         {
2654                 .name = "wm8994-aif1",
2655                 .id = 1,
2656                 .playback = {
2657                         .stream_name = "AIF1 Playback",
2658                         .channels_min = 1,
2659                         .channels_max = 2,
2660                         .rates = WM8994_RATES,
2661                         .formats = WM8994_FORMATS,
2662                         .sig_bits = 24,
2663                 },
2664                 .capture = {
2665                         .stream_name = "AIF1 Capture",
2666                         .channels_min = 1,
2667                         .channels_max = 2,
2668                         .rates = WM8994_RATES,
2669                         .formats = WM8994_FORMATS,
2670                         .sig_bits = 24,
2671                  },
2672                 .ops = &wm8994_aif1_dai_ops,
2673         },
2674         {
2675                 .name = "wm8994-aif2",
2676                 .id = 2,
2677                 .playback = {
2678                         .stream_name = "AIF2 Playback",
2679                         .channels_min = 1,
2680                         .channels_max = 2,
2681                         .rates = WM8994_RATES,
2682                         .formats = WM8994_FORMATS,
2683                         .sig_bits = 24,
2684                 },
2685                 .capture = {
2686                         .stream_name = "AIF2 Capture",
2687                         .channels_min = 1,
2688                         .channels_max = 2,
2689                         .rates = WM8994_RATES,
2690                         .formats = WM8994_FORMATS,
2691                         .sig_bits = 24,
2692                 },
2693                 .probe = wm8994_aif2_probe,
2694                 .ops = &wm8994_aif2_dai_ops,
2695         },
2696         {
2697                 .name = "wm8994-aif3",
2698                 .id = 3,
2699                 .playback = {
2700                         .stream_name = "AIF3 Playback",
2701                         .channels_min = 1,
2702                         .channels_max = 2,
2703                         .rates = WM8994_RATES,
2704                         .formats = WM8994_FORMATS,
2705                         .sig_bits = 24,
2706                 },
2707                 .capture = {
2708                         .stream_name = "AIF3 Capture",
2709                         .channels_min = 1,
2710                         .channels_max = 2,
2711                         .rates = WM8994_RATES,
2712                         .formats = WM8994_FORMATS,
2713                         .sig_bits = 24,
2714                  },
2715                 .ops = &wm8994_aif3_dai_ops,
2716         }
2717 };
2718
2719 #ifdef CONFIG_PM
2720 static int wm8994_suspend(struct snd_soc_codec *codec)
2721 {
2722         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2723         struct wm8994 *control = wm8994->wm8994;
2724         int i, ret;
2725
2726         switch (control->type) {
2727         case WM8994:
2728                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2729                 break;
2730         case WM1811:
2731                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2732                                     WM1811_JACKDET_MODE_MASK, 0);
2733                 /* Fall through */
2734         case WM8958:
2735                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2736                                     WM8958_MICD_ENA, 0);
2737                 break;
2738         }
2739
2740         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2741                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2742                        sizeof(struct wm8994_fll_config));
2743                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2744                 if (ret < 0)
2745                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2746                                  i + 1, ret);
2747         }
2748
2749         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2750
2751         return 0;
2752 }
2753
2754 static int wm8994_resume(struct snd_soc_codec *codec)
2755 {
2756         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2757         struct wm8994 *control = wm8994->wm8994;
2758         int i, ret;
2759         unsigned int val, mask;
2760
2761         if (wm8994->revision < 4) {
2762                 /* force a HW read */
2763                 ret = regmap_read(control->regmap,
2764                                   WM8994_POWER_MANAGEMENT_5, &val);
2765
2766                 /* modify the cache only */
2767                 codec->cache_only = 1;
2768                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2769                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2770                 val &= mask;
2771                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2772                                     mask, val);
2773                 codec->cache_only = 0;
2774         }
2775
2776         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2777                 if (!wm8994->fll_suspend[i].out)
2778                         continue;
2779
2780                 ret = _wm8994_set_fll(codec, i + 1,
2781                                      wm8994->fll_suspend[i].src,
2782                                      wm8994->fll_suspend[i].in,
2783                                      wm8994->fll_suspend[i].out);
2784                 if (ret < 0)
2785                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2786                                  i + 1, ret);
2787         }
2788
2789         switch (control->type) {
2790         case WM8994:
2791                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2792                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2793                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2794                 break;
2795         case WM1811:
2796                 if (wm8994->jackdet && wm8994->jack_cb) {
2797                         /* Restart from idle */
2798                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2799                                             WM1811_JACKDET_MODE_MASK,
2800                                             WM1811_JACKDET_MODE_JACK);
2801                         break;
2802                 }
2803         case WM8958:
2804                 if (wm8994->jack_cb)
2805                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2806                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2807                 break;
2808         }
2809
2810         return 0;
2811 }
2812 #else
2813 #define wm8994_suspend NULL
2814 #define wm8994_resume NULL
2815 #endif
2816
2817 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2818 {
2819         struct snd_soc_codec *codec = wm8994->codec;
2820         struct wm8994_pdata *pdata = wm8994->pdata;
2821         struct snd_kcontrol_new controls[] = {
2822                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2823                              wm8994->retune_mobile_enum,
2824                              wm8994_get_retune_mobile_enum,
2825                              wm8994_put_retune_mobile_enum),
2826                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2827                              wm8994->retune_mobile_enum,
2828                              wm8994_get_retune_mobile_enum,
2829                              wm8994_put_retune_mobile_enum),
2830                 SOC_ENUM_EXT("AIF2 EQ Mode",
2831                              wm8994->retune_mobile_enum,
2832                              wm8994_get_retune_mobile_enum,
2833                              wm8994_put_retune_mobile_enum),
2834         };
2835         int ret, i, j;
2836         const char **t;
2837
2838         /* We need an array of texts for the enum API but the number
2839          * of texts is likely to be less than the number of
2840          * configurations due to the sample rate dependency of the
2841          * configurations. */
2842         wm8994->num_retune_mobile_texts = 0;
2843         wm8994->retune_mobile_texts = NULL;
2844         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2845                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2846                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2847                                    wm8994->retune_mobile_texts[j]) == 0)
2848                                 break;
2849                 }
2850
2851                 if (j != wm8994->num_retune_mobile_texts)
2852                         continue;
2853
2854                 /* Expand the array... */
2855                 t = krealloc(wm8994->retune_mobile_texts,
2856                              sizeof(char *) *
2857                              (wm8994->num_retune_mobile_texts + 1),
2858                              GFP_KERNEL);
2859                 if (t == NULL)
2860                         continue;
2861
2862                 /* ...store the new entry... */
2863                 t[wm8994->num_retune_mobile_texts] =
2864                         pdata->retune_mobile_cfgs[i].name;
2865
2866                 /* ...and remember the new version. */
2867                 wm8994->num_retune_mobile_texts++;
2868                 wm8994->retune_mobile_texts = t;
2869         }
2870
2871         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2872                 wm8994->num_retune_mobile_texts);
2873
2874         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2875         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2876
2877         ret = snd_soc_add_codec_controls(wm8994->codec, controls,
2878                                    ARRAY_SIZE(controls));
2879         if (ret != 0)
2880                 dev_err(wm8994->codec->dev,
2881                         "Failed to add ReTune Mobile controls: %d\n", ret);
2882 }
2883
2884 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2885 {
2886         struct snd_soc_codec *codec = wm8994->codec;
2887         struct wm8994_pdata *pdata = wm8994->pdata;
2888         int ret, i;
2889
2890         if (!pdata)
2891                 return;
2892
2893         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2894                                       pdata->lineout2_diff,
2895                                       pdata->lineout1fb,
2896                                       pdata->lineout2fb,
2897                                       pdata->jd_scthr,
2898                                       pdata->jd_thr,
2899                                       pdata->micbias1_lvl,
2900                                       pdata->micbias2_lvl);
2901
2902         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2903
2904         if (pdata->num_drc_cfgs) {
2905                 struct snd_kcontrol_new controls[] = {
2906                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2907                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2908                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2909                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2910                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2911                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2912                 };
2913
2914                 /* We need an array of texts for the enum API */
2915                 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
2916                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
2917                 if (!wm8994->drc_texts) {
2918                         dev_err(wm8994->codec->dev,
2919                                 "Failed to allocate %d DRC config texts\n",
2920                                 pdata->num_drc_cfgs);
2921                         return;
2922                 }
2923
2924                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2925                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2926
2927                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2928                 wm8994->drc_enum.texts = wm8994->drc_texts;
2929
2930                 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
2931                                            ARRAY_SIZE(controls));
2932                 if (ret != 0)
2933                         dev_err(wm8994->codec->dev,
2934                                 "Failed to add DRC mode controls: %d\n", ret);
2935
2936                 for (i = 0; i < WM8994_NUM_DRC; i++)
2937                         wm8994_set_drc(codec, i);
2938         }
2939
2940         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2941                 pdata->num_retune_mobile_cfgs);
2942
2943         if (pdata->num_retune_mobile_cfgs)
2944                 wm8994_handle_retune_mobile_pdata(wm8994);
2945         else
2946                 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
2947                                      ARRAY_SIZE(wm8994_eq_controls));
2948
2949         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2950                 if (pdata->micbias[i]) {
2951                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
2952                                 pdata->micbias[i] & 0xffff);
2953                 }
2954         }
2955 }
2956
2957 /**
2958  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2959  *
2960  * @codec:   WM8994 codec
2961  * @jack:    jack to report detection events on
2962  * @micbias: microphone bias to detect on
2963  *
2964  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2965  * being used to bring out signals to the processor then only platform
2966  * data configuration is needed for WM8994 and processor GPIOs should
2967  * be configured using snd_soc_jack_add_gpios() instead.
2968  *
2969  * Configuration of detection levels is available via the micbias1_lvl
2970  * and micbias2_lvl platform data members.
2971  */
2972 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2973                       int micbias)
2974 {
2975         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2976         struct wm8994_micdet *micdet;
2977         struct wm8994 *control = wm8994->wm8994;
2978         int reg, ret;
2979
2980         if (control->type != WM8994) {
2981                 dev_warn(codec->dev, "Not a WM8994\n");
2982                 return -EINVAL;
2983         }
2984
2985         switch (micbias) {
2986         case 1:
2987                 micdet = &wm8994->micdet[0];
2988                 if (jack)
2989                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
2990                                                             "MICBIAS1");
2991                 else
2992                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
2993                                                        "MICBIAS1");
2994                 break;
2995         case 2:
2996                 micdet = &wm8994->micdet[1];
2997                 if (jack)
2998                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
2999                                                             "MICBIAS1");
3000                 else
3001                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3002                                                        "MICBIAS1");
3003                 break;
3004         default:
3005                 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3006                 return -EINVAL;
3007         }
3008
3009         if (ret != 0)
3010                 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3011                          micbias, ret);
3012
3013         dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3014                 micbias, jack);
3015
3016         /* Store the configuration */
3017         micdet->jack = jack;
3018         micdet->detecting = true;
3019
3020         /* If either of the jacks is set up then enable detection */
3021         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3022                 reg = WM8994_MICD_ENA;
3023         else
3024                 reg = 0;
3025
3026         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3027
3028         snd_soc_dapm_sync(&codec->dapm);
3029
3030         return 0;
3031 }
3032 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3033
3034 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3035 {
3036         struct wm8994_priv *priv = data;
3037         struct snd_soc_codec *codec = priv->codec;
3038         int reg;
3039         int report;
3040
3041 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3042         trace_snd_soc_jack_irq(dev_name(codec->dev));
3043 #endif
3044
3045         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3046         if (reg < 0) {
3047                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3048                         reg);
3049                 return IRQ_HANDLED;
3050         }
3051
3052         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3053
3054         report = 0;
3055         if (reg & WM8994_MIC1_DET_STS) {
3056                 if (priv->micdet[0].detecting)
3057                         report = SND_JACK_HEADSET;
3058         }
3059         if (reg & WM8994_MIC1_SHRT_STS) {
3060                 if (priv->micdet[0].detecting)
3061                         report = SND_JACK_HEADPHONE;
3062                 else
3063                         report |= SND_JACK_BTN_0;
3064         }
3065         if (report)
3066                 priv->micdet[0].detecting = false;
3067         else
3068                 priv->micdet[0].detecting = true;
3069
3070         snd_soc_jack_report(priv->micdet[0].jack, report,
3071                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3072
3073         report = 0;
3074         if (reg & WM8994_MIC2_DET_STS) {
3075                 if (priv->micdet[1].detecting)
3076                         report = SND_JACK_HEADSET;
3077         }
3078         if (reg & WM8994_MIC2_SHRT_STS) {
3079                 if (priv->micdet[1].detecting)
3080                         report = SND_JACK_HEADPHONE;
3081                 else
3082                         report |= SND_JACK_BTN_0;
3083         }
3084         if (report)
3085                 priv->micdet[1].detecting = false;
3086         else
3087                 priv->micdet[1].detecting = true;
3088
3089         snd_soc_jack_report(priv->micdet[1].jack, report,
3090                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3091
3092         return IRQ_HANDLED;
3093 }
3094
3095 /* Default microphone detection handler for WM8958 - the user can
3096  * override this if they wish.
3097  */
3098 static void wm8958_default_micdet(u16 status, void *data)
3099 {
3100         struct snd_soc_codec *codec = data;
3101         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3102         int report;
3103
3104         dev_dbg(codec->dev, "MICDET %x\n", status);
3105
3106         /* Either nothing present or just starting detection */
3107         if (!(status & WM8958_MICD_STS)) {
3108                 if (!wm8994->jackdet) {
3109                         /* If nothing present then clear our statuses */
3110                         dev_dbg(codec->dev, "Detected open circuit\n");
3111                         wm8994->jack_mic = false;
3112                         wm8994->mic_detecting = true;
3113
3114                         wm8958_micd_set_rate(codec);
3115
3116                         snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3117                                             wm8994->btn_mask |
3118                                              SND_JACK_HEADSET);
3119                 }
3120                 return;
3121         }
3122
3123         /* If the measurement is showing a high impedence we've got a
3124          * microphone.
3125          */
3126         if (wm8994->mic_detecting && (status & 0x600)) {
3127                 dev_dbg(codec->dev, "Detected microphone\n");
3128
3129                 wm8994->mic_detecting = false;
3130                 wm8994->jack_mic = true;
3131
3132                 wm8958_micd_set_rate(codec);
3133
3134                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3135                                     SND_JACK_HEADSET);
3136         }
3137
3138
3139         if (wm8994->mic_detecting && status & 0xfc) {
3140                 dev_dbg(codec->dev, "Detected headphone\n");
3141                 wm8994->mic_detecting = false;
3142
3143                 wm8958_micd_set_rate(codec);
3144
3145                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3146                                     SND_JACK_HEADSET);
3147
3148                 /* If we have jackdet that will detect removal */
3149                 if (wm8994->jackdet) {
3150                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3151                                             WM8958_MICD_ENA, 0);
3152
3153                         wm1811_jackdet_set_mode(codec,
3154                                                 WM1811_JACKDET_MODE_JACK);
3155                 }
3156         }
3157
3158         /* Report short circuit as a button */
3159         if (wm8994->jack_mic) {
3160                 report = 0;
3161                 if (status & 0x4)
3162                         report |= SND_JACK_BTN_0;
3163
3164                 if (status & 0x8)
3165                         report |= SND_JACK_BTN_1;
3166
3167                 if (status & 0x10)
3168                         report |= SND_JACK_BTN_2;
3169
3170                 if (status & 0x20)
3171                         report |= SND_JACK_BTN_3;
3172
3173                 if (status & 0x40)
3174                         report |= SND_JACK_BTN_4;
3175
3176                 if (status & 0x80)
3177                         report |= SND_JACK_BTN_5;
3178
3179                 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3180                                     wm8994->btn_mask);
3181         }
3182 }
3183
3184 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3185 {
3186         struct wm8994_priv *wm8994 = data;
3187         struct snd_soc_codec *codec = wm8994->codec;
3188         int reg;
3189
3190         mutex_lock(&wm8994->accdet_lock);
3191
3192         reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3193         if (reg < 0) {
3194                 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3195                 mutex_unlock(&wm8994->accdet_lock);
3196                 return IRQ_NONE;
3197         }
3198
3199         dev_dbg(codec->dev, "JACKDET %x\n", reg);
3200
3201         if (reg & WM1811_JACKDET_LVL) {
3202                 dev_dbg(codec->dev, "Jack detected\n");
3203
3204                 snd_soc_jack_report(wm8994->micdet[0].jack,
3205                                     SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3206
3207                 /*
3208                  * Start off measument of microphone impedence to find
3209                  * out what's actually there.
3210                  */
3211                 wm8994->mic_detecting = true;
3212                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3213                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3214                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3215         } else {
3216                 dev_dbg(codec->dev, "Jack not detected\n");
3217
3218                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3219                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3220                                     wm8994->btn_mask);
3221
3222                 wm8994->mic_detecting = false;
3223                 wm8994->jack_mic = false;
3224                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3225                                     WM8958_MICD_ENA, 0);
3226                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3227         }
3228
3229         mutex_unlock(&wm8994->accdet_lock);
3230
3231         return IRQ_HANDLED;
3232 }
3233
3234 /**
3235  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3236  *
3237  * @codec:   WM8958 codec
3238  * @jack:    jack to report detection events on
3239  *
3240  * Enable microphone detection functionality for the WM8958.  By
3241  * default simple detection which supports the detection of up to 6
3242  * buttons plus video and microphone functionality is supported.
3243  *
3244  * The WM8958 has an advanced jack detection facility which is able to
3245  * support complex accessory detection, especially when used in
3246  * conjunction with external circuitry.  In order to provide maximum
3247  * flexiblity a callback is provided which allows a completely custom
3248  * detection algorithm.
3249  */
3250 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3251                       wm8958_micdet_cb cb, void *cb_data)
3252 {
3253         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3254         struct wm8994 *control = wm8994->wm8994;
3255         u16 micd_lvl_sel;
3256
3257         switch (control->type) {
3258         case WM1811:
3259         case WM8958:
3260                 break;
3261         default:
3262                 return -EINVAL;
3263         }
3264
3265         if (jack) {
3266                 if (!cb) {
3267                         dev_dbg(codec->dev, "Using default micdet callback\n");
3268                         cb = wm8958_default_micdet;
3269                         cb_data = codec;
3270                 }
3271
3272                 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3273
3274                 wm8994->micdet[0].jack = jack;
3275                 wm8994->jack_cb = cb;
3276                 wm8994->jack_cb_data = cb_data;
3277
3278                 wm8994->mic_detecting = true;
3279                 wm8994->jack_mic = false;
3280
3281                 wm8958_micd_set_rate(codec);
3282
3283                 /* Detect microphones and short circuits by default */
3284                 if (wm8994->pdata->micd_lvl_sel)
3285                         micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3286                 else
3287                         micd_lvl_sel = 0x41;
3288
3289                 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3290                         SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3291                         SND_JACK_BTN_4 | SND_JACK_BTN_5;
3292
3293                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3294                                     WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3295
3296                 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3297
3298                 /*
3299                  * If we can use jack detection start off with that,
3300                  * otherwise jump straight to microphone detection.
3301                  */
3302                 if (wm8994->jackdet) {
3303                         snd_soc_update_bits(codec, WM8994_LDO_1,
3304                                             WM8994_LDO1_DISCH, 0);
3305                         wm1811_jackdet_set_mode(codec,
3306                                                 WM1811_JACKDET_MODE_JACK);
3307                 } else {
3308                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3309                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
3310                 }
3311
3312         } else {
3313                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3314                                     WM8958_MICD_ENA, 0);
3315                 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3316         }
3317
3318         return 0;
3319 }
3320 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3321
3322 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3323 {
3324         struct wm8994_priv *wm8994 = data;
3325         struct snd_soc_codec *codec = wm8994->codec;
3326         int reg, count;
3327
3328         mutex_lock(&wm8994->accdet_lock);
3329
3330         /*
3331          * Jack detection may have detected a removal simulataneously
3332          * with an update of the MICDET status; if so it will have
3333          * stopped detection and we can ignore this interrupt.
3334          */
3335         if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) {
3336                 mutex_unlock(&wm8994->accdet_lock);
3337                 return IRQ_HANDLED;
3338         }
3339
3340         /* We may occasionally read a detection without an impedence
3341          * range being provided - if that happens loop again.
3342          */
3343         count = 10;
3344         do {
3345                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3346                 if (reg < 0) {
3347                         mutex_unlock(&wm8994->accdet_lock);
3348                         dev_err(codec->dev,
3349                                 "Failed to read mic detect status: %d\n",
3350                                 reg);
3351                         return IRQ_NONE;
3352                 }
3353
3354                 if (!(reg & WM8958_MICD_VALID)) {
3355                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3356                         goto out;
3357                 }
3358
3359                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3360                         break;
3361
3362                 msleep(1);
3363         } while (count--);
3364
3365         if (count == 0)
3366                 dev_warn(codec->dev, "No impedence range reported for jack\n");
3367
3368 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3369         trace_snd_soc_jack_irq(dev_name(codec->dev));
3370 #endif
3371
3372         if (wm8994->jack_cb)
3373                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3374         else
3375                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3376
3377 out:
3378         mutex_unlock(&wm8994->accdet_lock);
3379
3380         return IRQ_HANDLED;
3381 }
3382
3383 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3384 {
3385         struct snd_soc_codec *codec = data;
3386
3387         dev_err(codec->dev, "FIFO error\n");
3388
3389         return IRQ_HANDLED;
3390 }
3391
3392 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3393 {
3394         struct snd_soc_codec *codec = data;
3395
3396         dev_err(codec->dev, "Thermal warning\n");
3397
3398         return IRQ_HANDLED;
3399 }
3400
3401 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3402 {
3403         struct snd_soc_codec *codec = data;
3404
3405         dev_crit(codec->dev, "Thermal shutdown\n");
3406
3407         return IRQ_HANDLED;
3408 }
3409
3410 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3411 {
3412         struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3413         struct wm8994_priv *wm8994;
3414         struct snd_soc_dapm_context *dapm = &codec->dapm;
3415         unsigned int reg;
3416         int ret, i;
3417
3418         codec->control_data = control->regmap;
3419
3420         wm8994 = devm_kzalloc(codec->dev, sizeof(struct wm8994_priv),
3421                               GFP_KERNEL);
3422         if (wm8994 == NULL)
3423                 return -ENOMEM;
3424         snd_soc_codec_set_drvdata(codec, wm8994);
3425
3426         snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3427
3428         wm8994->wm8994 = dev_get_drvdata(codec->dev->parent);
3429         wm8994->pdata = dev_get_platdata(codec->dev->parent);
3430         wm8994->codec = codec;
3431
3432         mutex_init(&wm8994->accdet_lock);
3433
3434         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3435                 init_completion(&wm8994->fll_locked[i]);
3436
3437         if (wm8994->pdata && wm8994->pdata->micdet_irq)
3438                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3439         else if (wm8994->pdata && wm8994->pdata->irq_base)
3440                 wm8994->micdet_irq = wm8994->pdata->irq_base +
3441                                      WM8994_IRQ_MIC1_DET;
3442
3443         pm_runtime_enable(codec->dev);
3444         pm_runtime_idle(codec->dev);
3445
3446         /* By default use idle_bias_off, will override for WM8994 */
3447         codec->dapm.idle_bias_off = 1;
3448
3449         /* Set revision-specific configuration */
3450         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3451         switch (control->type) {
3452         case WM8994:
3453                 /* Single ended line outputs should have VMID on. */
3454                 if (!wm8994->pdata->lineout1_diff ||
3455                     !wm8994->pdata->lineout2_diff)
3456                         codec->dapm.idle_bias_off = 0;
3457
3458                 switch (wm8994->revision) {
3459                 case 2:
3460                 case 3:
3461                         wm8994->hubs.dcs_codes_l = -5;
3462                         wm8994->hubs.dcs_codes_r = -5;
3463                         wm8994->hubs.hp_startup_mode = 1;
3464                         wm8994->hubs.dcs_readback_mode = 1;
3465                         wm8994->hubs.series_startup = 1;
3466                         break;
3467                 default:
3468                         wm8994->hubs.dcs_readback_mode = 2;
3469                         break;
3470                 }
3471                 break;
3472
3473         case WM8958:
3474                 wm8994->hubs.dcs_readback_mode = 1;
3475                 break;
3476
3477         case WM1811:
3478                 wm8994->hubs.dcs_readback_mode = 2;
3479                 wm8994->hubs.no_series_update = 1;
3480
3481                 switch (wm8994->revision) {
3482                 case 0:
3483                 case 1:
3484                 case 2:
3485                 case 3:
3486                         wm8994->hubs.dcs_codes_l = -9;
3487                         wm8994->hubs.dcs_codes_r = -5;
3488                         break;
3489                 default:
3490                         break;
3491                 }
3492
3493                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3494                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3495                 break;
3496
3497         default:
3498                 break;
3499         }
3500
3501         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3502                            wm8994_fifo_error, "FIFO error", codec);
3503         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3504                            wm8994_temp_warn, "Thermal warning", codec);
3505         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3506                            wm8994_temp_shut, "Thermal shutdown", codec);
3507
3508         ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3509                                  wm_hubs_dcs_done, "DC servo done",
3510                                  &wm8994->hubs);
3511         if (ret == 0)
3512                 wm8994->hubs.dcs_done_irq = true;
3513
3514         switch (control->type) {
3515         case WM8994:
3516                 if (wm8994->micdet_irq) {
3517                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3518                                                    wm8994_mic_irq,
3519                                                    IRQF_TRIGGER_RISING,
3520                                                    "Mic1 detect",
3521                                                    wm8994);
3522                         if (ret != 0)
3523                                 dev_warn(codec->dev,
3524                                          "Failed to request Mic1 detect IRQ: %d\n",
3525                                          ret);
3526                 }
3527
3528                 ret = wm8994_request_irq(wm8994->wm8994,
3529                                          WM8994_IRQ_MIC1_SHRT,
3530                                          wm8994_mic_irq, "Mic 1 short",
3531                                          wm8994);
3532                 if (ret != 0)
3533                         dev_warn(codec->dev,
3534                                  "Failed to request Mic1 short IRQ: %d\n",
3535                                  ret);
3536
3537                 ret = wm8994_request_irq(wm8994->wm8994,
3538                                          WM8994_IRQ_MIC2_DET,
3539                                          wm8994_mic_irq, "Mic 2 detect",
3540                                          wm8994);
3541                 if (ret != 0)
3542                         dev_warn(codec->dev,
3543                                  "Failed to request Mic2 detect IRQ: %d\n",
3544                                  ret);
3545
3546                 ret = wm8994_request_irq(wm8994->wm8994,
3547                                          WM8994_IRQ_MIC2_SHRT,
3548                                          wm8994_mic_irq, "Mic 2 short",
3549                                          wm8994);
3550                 if (ret != 0)
3551                         dev_warn(codec->dev,
3552                                  "Failed to request Mic2 short IRQ: %d\n",
3553                                  ret);
3554                 break;
3555
3556         case WM8958:
3557         case WM1811:
3558                 if (wm8994->micdet_irq) {
3559                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3560                                                    wm8958_mic_irq,
3561                                                    IRQF_TRIGGER_RISING,
3562                                                    "Mic detect",
3563                                                    wm8994);
3564                         if (ret != 0)
3565                                 dev_warn(codec->dev,
3566                                          "Failed to request Mic detect IRQ: %d\n",
3567                                          ret);
3568                 }
3569         }
3570
3571         switch (control->type) {
3572         case WM1811:
3573                 if (wm8994->revision > 1) {
3574                         ret = wm8994_request_irq(wm8994->wm8994,
3575                                                  WM8994_IRQ_GPIO(6),
3576                                                  wm1811_jackdet_irq, "JACKDET",
3577                                                  wm8994);
3578                         if (ret == 0)
3579                                 wm8994->jackdet = true;
3580                 }
3581                 break;
3582         default:
3583                 break;
3584         }
3585
3586         wm8994->fll_locked_irq = true;
3587         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3588                 ret = wm8994_request_irq(wm8994->wm8994,
3589                                          WM8994_IRQ_FLL1_LOCK + i,
3590                                          wm8994_fll_locked_irq, "FLL lock",
3591                                          &wm8994->fll_locked[i]);
3592                 if (ret != 0)
3593                         wm8994->fll_locked_irq = false;
3594         }
3595
3596         /* Make sure we can read from the GPIOs if they're inputs */
3597         pm_runtime_get_sync(codec->dev);
3598
3599         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3600          * configured on init - if a system wants to do this dynamically
3601          * at runtime we can deal with that then.
3602          */
3603         ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3604         if (ret < 0) {
3605                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3606                 goto err_irq;
3607         }
3608         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3609                 wm8994->lrclk_shared[0] = 1;
3610                 wm8994_dai[0].symmetric_rates = 1;
3611         } else {
3612                 wm8994->lrclk_shared[0] = 0;
3613         }
3614
3615         ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3616         if (ret < 0) {
3617                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3618                 goto err_irq;
3619         }
3620         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3621                 wm8994->lrclk_shared[1] = 1;
3622                 wm8994_dai[1].symmetric_rates = 1;
3623         } else {
3624                 wm8994->lrclk_shared[1] = 0;
3625         }
3626
3627         pm_runtime_put(codec->dev);
3628
3629         /* Latch volume updates (right only; we always do left then right). */
3630         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3631                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3632         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3633                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3634         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3635                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3636         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3637                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3638         snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3639                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3640         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3641                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3642         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3643                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3644         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3645                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3646         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3647                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3648         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3649                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3650         snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3651                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3652         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3653                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3654         snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3655                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3656         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3657                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3658         snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3659                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3660         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3661                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3662
3663         /* Set the low bit of the 3D stereo depth so TLV matches */
3664         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3665                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3666                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3667         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3668                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3669                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3670         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3671                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3672                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3673
3674         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3675          * use this; it only affects behaviour on idle TDM clock
3676          * cycles. */
3677         switch (control->type) {
3678         case WM8994:
3679         case WM8958:
3680                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3681                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3682                 break;
3683         default:
3684                 break;
3685         }
3686
3687         /* Put MICBIAS into bypass mode by default on newer devices */
3688         switch (control->type) {
3689         case WM8958:
3690         case WM1811:
3691                 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3692                                     WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3693                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3694                                     WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3695                 break;
3696         default:
3697                 break;
3698         }
3699
3700         wm8994_update_class_w(codec);
3701
3702         wm8994_handle_pdata(wm8994);
3703
3704         wm_hubs_add_analogue_controls(codec);
3705         snd_soc_add_codec_controls(codec, wm8994_snd_controls,
3706                              ARRAY_SIZE(wm8994_snd_controls));
3707         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3708                                   ARRAY_SIZE(wm8994_dapm_widgets));
3709
3710         switch (control->type) {
3711         case WM8994:
3712                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3713                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3714                 if (wm8994->revision < 4) {
3715                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3716                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3717                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3718                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3719                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3720                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3721                 } else {
3722                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3723                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3724                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3725                                                   ARRAY_SIZE(wm8994_adc_widgets));
3726                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3727                                                   ARRAY_SIZE(wm8994_dac_widgets));
3728                 }
3729                 break;
3730         case WM8958:
3731                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
3732                                      ARRAY_SIZE(wm8958_snd_controls));
3733                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3734                                           ARRAY_SIZE(wm8958_dapm_widgets));
3735                 if (wm8994->revision < 1) {
3736                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3737                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3738                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3739                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3740                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3741                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3742                 } else {
3743                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3744                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3745                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3746                                                   ARRAY_SIZE(wm8994_adc_widgets));
3747                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3748                                                   ARRAY_SIZE(wm8994_dac_widgets));
3749                 }
3750                 break;
3751
3752         case WM1811:
3753                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
3754                                      ARRAY_SIZE(wm8958_snd_controls));
3755                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3756                                           ARRAY_SIZE(wm8958_dapm_widgets));
3757                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3758                                           ARRAY_SIZE(wm8994_lateclk_widgets));
3759                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3760                                           ARRAY_SIZE(wm8994_adc_widgets));
3761                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3762                                           ARRAY_SIZE(wm8994_dac_widgets));
3763                 break;
3764         }
3765
3766
3767         wm_hubs_add_analogue_routes(codec, 0, 0);
3768         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3769
3770         switch (control->type) {
3771         case WM8994:
3772                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3773                                         ARRAY_SIZE(wm8994_intercon));
3774
3775                 if (wm8994->revision < 4) {
3776                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3777                                                 ARRAY_SIZE(wm8994_revd_intercon));
3778                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3779                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3780                 } else {
3781                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3782                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3783                 }
3784                 break;
3785         case WM8958:
3786                 if (wm8994->revision < 1) {
3787                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3788                                                 ARRAY_SIZE(wm8994_revd_intercon));
3789                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3790                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3791                 } else {
3792                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3793                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3794                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3795                                                 ARRAY_SIZE(wm8958_intercon));
3796                 }
3797
3798                 wm8958_dsp2_init(codec);
3799                 break;
3800         case WM1811:
3801                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3802                                         ARRAY_SIZE(wm8994_lateclk_intercon));
3803                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3804                                         ARRAY_SIZE(wm8958_intercon));
3805                 break;
3806         }
3807
3808         return 0;
3809
3810 err_irq:
3811         if (wm8994->jackdet)
3812                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3813         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3814         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3815         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
3816         if (wm8994->micdet_irq)
3817                 free_irq(wm8994->micdet_irq, wm8994);
3818         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3819                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3820                                 &wm8994->fll_locked[i]);
3821         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3822                         &wm8994->hubs);
3823         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3824         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3825         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3826
3827         return ret;
3828 }
3829
3830 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3831 {
3832         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3833         struct wm8994 *control = wm8994->wm8994;
3834         int i;
3835
3836         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3837
3838         pm_runtime_disable(codec->dev);
3839
3840         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3841                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3842                                 &wm8994->fll_locked[i]);
3843
3844         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3845                         &wm8994->hubs);
3846         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3847         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3848         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3849
3850         if (wm8994->jackdet)
3851                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3852
3853         switch (control->type) {
3854         case WM8994:
3855                 if (wm8994->micdet_irq)
3856                         free_irq(wm8994->micdet_irq, wm8994);
3857                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3858                                 wm8994);
3859                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3860                                 wm8994);
3861                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3862                                 wm8994);
3863                 break;
3864
3865         case WM1811:
3866         case WM8958:
3867                 if (wm8994->micdet_irq)
3868                         free_irq(wm8994->micdet_irq, wm8994);
3869                 break;
3870         }
3871         if (wm8994->mbc)
3872                 release_firmware(wm8994->mbc);
3873         if (wm8994->mbc_vss)
3874                 release_firmware(wm8994->mbc_vss);
3875         if (wm8994->enh_eq)
3876                 release_firmware(wm8994->enh_eq);
3877         kfree(wm8994->retune_mobile_texts);
3878
3879         return 0;
3880 }
3881
3882 static int wm8994_soc_volatile(struct snd_soc_codec *codec,
3883                                unsigned int reg)
3884 {
3885         return true;
3886 }
3887
3888 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3889         .probe =        wm8994_codec_probe,
3890         .remove =       wm8994_codec_remove,
3891         .suspend =      wm8994_suspend,
3892         .resume =       wm8994_resume,
3893         .set_bias_level = wm8994_set_bias_level,
3894         .reg_cache_size = WM8994_MAX_REGISTER,
3895         .volatile_register = wm8994_soc_volatile,
3896 };
3897
3898 static int __devinit wm8994_probe(struct platform_device *pdev)
3899 {
3900         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3901                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3902 }
3903
3904 static int __devexit wm8994_remove(struct platform_device *pdev)
3905 {
3906         snd_soc_unregister_codec(&pdev->dev);
3907         return 0;
3908 }
3909
3910 static struct platform_driver wm8994_codec_driver = {
3911         .driver = {
3912                    .name = "wm8994-codec",
3913                    .owner = THIS_MODULE,
3914                    },
3915         .probe = wm8994_probe,
3916         .remove = __devexit_p(wm8994_remove),
3917 };
3918
3919 module_platform_driver(wm8994_codec_driver);
3920
3921 MODULE_DESCRIPTION("ASoC WM8994 driver");
3922 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3923 MODULE_LICENSE("GPL");
3924 MODULE_ALIAS("platform:wm8994-codec");