Pileus Git - ~andy/linux/blob - sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009-12 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM1811_JACKDET_MODE_NONE  0x0000
  42 #define WM1811_JACKDET_MODE_JACK  0x0100
  43 #define WM1811_JACKDET_MODE_MIC   0x0080
  44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
  45
  46 #define WM8994_NUM_DRC 3
  47 #define WM8994_NUM_EQ  3
  48
  49 static struct {
  50         unsigned int reg;
  51         unsigned int mask;
  52 } wm8994_vu_bits[] = {
  53         { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  54         { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  55         { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  56         { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  57         { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
  58         { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
  59         { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  60         { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  61         { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  62         { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  63
  64         { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
  65         { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
  66         { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
  67         { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
  68         { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
  69         { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
  70         { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
  71         { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
  72         { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
  73         { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  74         { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
  75         { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  76         { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
  77         { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
  78         { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
  79         { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
  80 };
  81
  82 static int wm8994_drc_base[] = {
  83         WM8994_AIF1_DRC1_1,
  84         WM8994_AIF1_DRC2_1,
  85         WM8994_AIF2_DRC_1,
  86 };
  87
  88 static int wm8994_retune_mobile_base[] = {
  89         WM8994_AIF1_DAC1_EQ_GAINS_1,
  90         WM8994_AIF1_DAC2_EQ_GAINS_1,
  91         WM8994_AIF2_EQ_GAINS_1,
  92 };
  93
  94 static void wm8958_default_micdet(u16 status, void *data);
  95
  96 static const struct wm8958_micd_rate micdet_rates[] = {
  97         { 32768,       true,  1, 4 },
  98         { 32768,       false, 1, 1 },
  99         { 44100 * 256, true,  7, 10 },
 100         { 44100 * 256, false, 7, 10 },
 101 };
 102
 103 static const struct wm8958_micd_rate jackdet_rates[] = {
 104         { 32768,       true,  0, 1 },
 105         { 32768,       false, 0, 1 },
 106         { 44100 * 256, true,  10, 10 },
 107         { 44100 * 256, false, 7, 8 },
 108 };
 109
 110 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
 111 {
 112         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 113         int best, i, sysclk, val;
 114         bool idle;
 115         const struct wm8958_micd_rate *rates;
 116         int num_rates;
 117
 118         if (!(wm8994->pdata && wm8994->pdata->micd_rates) &&
 119             wm8994->jack_cb != wm8958_default_micdet)
 120                 return;
 121
 122         idle = !wm8994->jack_mic;
 123
 124         sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
 125         if (sysclk & WM8994_SYSCLK_SRC)
 126                 sysclk = wm8994->aifclk[1];
 127         else
 128                 sysclk = wm8994->aifclk[0];
 129
 130         if (wm8994->pdata && wm8994->pdata->micd_rates) {
 131                 rates = wm8994->pdata->micd_rates;
 132                 num_rates = wm8994->pdata->num_micd_rates;
 133         } else if (wm8994->jackdet) {
 134                 rates = jackdet_rates;
 135                 num_rates = ARRAY_SIZE(jackdet_rates);
 136         } else {
 137                 rates = micdet_rates;
 138                 num_rates = ARRAY_SIZE(micdet_rates);
 139         }
 140
 141         best = 0;
 142         for (i = 0; i < num_rates; i++) {
 143                 if (rates[i].idle != idle)
 144                         continue;
 145                 if (abs(rates[i].sysclk - sysclk) <
 146                     abs(rates[best].sysclk - sysclk))
 147                         best = i;
 148                 else if (rates[best].idle != idle)
 149                         best = i;
 150         }
 151
 152         val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
 153                 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
 154
 155         dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
 156                 rates[best].start, rates[best].rate, sysclk,
 157                 idle ? "idle" : "active");
 158
 159         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
 160                             WM8958_MICD_BIAS_STARTTIME_MASK |
 161                             WM8958_MICD_RATE_MASK, val);
 162 }
 163
 164 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 165 {
 166         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 167         int rate;
 168         int reg1 = 0;
 169         int offset;
 170
 171         if (aif)
 172                 offset = 4;
 173         else
 174                 offset = 0;
 175
 176         switch (wm8994->sysclk[aif]) {
 177         case WM8994_SYSCLK_MCLK1:
 178                 rate = wm8994->mclk[0];
 179                 break;
 180
 181         case WM8994_SYSCLK_MCLK2:
 182                 reg1 |= 0x8;
 183                 rate = wm8994->mclk[1];
 184                 break;
 185
 186         case WM8994_SYSCLK_FLL1:
 187                 reg1 |= 0x10;
 188                 rate = wm8994->fll[0].out;
 189                 break;
 190
 191         case WM8994_SYSCLK_FLL2:
 192                 reg1 |= 0x18;
 193                 rate = wm8994->fll[1].out;
 194                 break;
 195
 196         default:
 197                 return -EINVAL;
 198         }
 199
 200         if (rate >= 13500000) {
 201                 rate /= 2;
 202                 reg1 |= WM8994_AIF1CLK_DIV;
 203
 204                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 205                         aif + 1, rate);
 206         }
 207
 208         wm8994->aifclk[aif] = rate;
 209
 210         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 211                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 212                             reg1);
 213
 214         return 0;
 215 }
 216
 217 static int configure_clock(struct snd_soc_codec *codec)
 218 {
 219         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 220         int change, new;
 221
 222         /* Bring up the AIF clocks first */
 223         configure_aif_clock(codec, 0);
 224         configure_aif_clock(codec, 1);
 225
 226         /* Then switch CLK_SYS over to the higher of them; a change
 227          * can only happen as a result of a clocking change which can
 228          * only be made outside of DAPM so we can safely redo the
 229          * clocking.
 230          */
 231
 232         /* If they're equal it doesn't matter which is used */
 233         if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
 234                 wm8958_micd_set_rate(codec);
 235                 return 0;
 236         }
 237
 238         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 239                 new = WM8994_SYSCLK_SRC;
 240         else
 241                 new = 0;
 242
 243         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 244                                      WM8994_SYSCLK_SRC, new);
 245         if (change)
 246                 snd_soc_dapm_sync(&codec->dapm);
 247
 248         wm8958_micd_set_rate(codec);
 249
 250         return 0;
 251 }
 252
 253 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 254                          struct snd_soc_dapm_widget *sink)
 255 {
 256         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 257         const char *clk;
 258
 259         /* Check what we're currently using for CLK_SYS */
 260         if (reg & WM8994_SYSCLK_SRC)
 261                 clk = "AIF2CLK";
 262         else
 263                 clk = "AIF1CLK";
 264
 265         return strcmp(source->name, clk) == 0;
 266 }
 267
 268 static const char *sidetone_hpf_text[] = {
 269         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 270 };
 271
 272 static const struct soc_enum sidetone_hpf =
 273         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 274
 275 static const char *adc_hpf_text[] = {
 276         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 277 };
 278
 279 static const struct soc_enum aif1adc1_hpf =
 280         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 281
 282 static const struct soc_enum aif1adc2_hpf =
 283         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 284
 285 static const struct soc_enum aif2adc_hpf =
 286         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 287
 288 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 289 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 290 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 291 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 292 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 293 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 294 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 295
 296 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 297 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 298         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 299         .put = wm8994_put_drc_sw, \
 300         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 301
 302 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 303                              struct snd_ctl_elem_value *ucontrol)
 304 {
 305         struct soc_mixer_control *mc =
 306                 (struct soc_mixer_control *)kcontrol->private_value;
 307         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 308         int mask, ret;
 309
 310         /* Can't enable both ADC and DAC paths simultaneously */
 311         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 312                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 313                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 314         else
 315                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 316
 317         ret = snd_soc_read(codec, mc->reg);
 318         if (ret < 0)
 319                 return ret;
 320         if (ret & mask)
 321                 return -EINVAL;
 322
 323         return snd_soc_put_volsw(kcontrol, ucontrol);
 324 }
 325
 326 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 327 {
 328         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 329         struct wm8994_pdata *pdata = wm8994->pdata;
 330         int base = wm8994_drc_base[drc];
 331         int cfg = wm8994->drc_cfg[drc];
 332         int save, i;
 333
 334         /* Save any enables; the configuration should clear them. */
 335         save = snd_soc_read(codec, base);
 336         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 337                 WM8994_AIF1ADC1R_DRC_ENA;
 338
 339         for (i = 0; i < WM8994_DRC_REGS; i++)
 340                 snd_soc_update_bits(codec, base + i, 0xffff,
 341                                     pdata->drc_cfgs[cfg].regs[i]);
 342
 343         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 344                              WM8994_AIF1ADC1L_DRC_ENA |
 345                              WM8994_AIF1ADC1R_DRC_ENA, save);
 346 }
 347
 348 /* Icky as hell but saves code duplication */
 349 static int wm8994_get_drc(const char *name)
 350 {
 351         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 352                 return 0;
 353         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 354                 return 1;
 355         if (strcmp(name, "AIF2DRC Mode") == 0)
 356                 return 2;
 357         return -EINVAL;
 358 }
 359
 360 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 361                                struct snd_ctl_elem_value *ucontrol)
 362 {
 363         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 364         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 365         struct wm8994_pdata *pdata = wm8994->pdata;
 366         int drc = wm8994_get_drc(kcontrol->id.name);
 367         int value = ucontrol->value.integer.value[0];
 368
 369         if (drc < 0)
 370                 return drc;
 371
 372         if (value >= pdata->num_drc_cfgs)
 373                 return -EINVAL;
 374
 375         wm8994->drc_cfg[drc] = value;
 376
 377         wm8994_set_drc(codec, drc);
 378
 379         return 0;
 380 }
 381
 382 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 383                                struct snd_ctl_elem_value *ucontrol)
 384 {
 385         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 386         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 387         int drc = wm8994_get_drc(kcontrol->id.name);
 388
 389         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 390
 391         return 0;
 392 }
 393
 394 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 395 {
 396         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 397         struct wm8994_pdata *pdata = wm8994->pdata;
 398         int base = wm8994_retune_mobile_base[block];
 399         int iface, best, best_val, save, i, cfg;
 400
 401         if (!pdata || !wm8994->num_retune_mobile_texts)
 402                 return;
 403
 404         switch (block) {
 405         case 0:
 406         case 1:
 407                 iface = 0;
 408                 break;
 409         case 2:
 410                 iface = 1;
 411                 break;
 412         default:
 413                 return;
 414         }
 415
 416         /* Find the version of the currently selected configuration
 417          * with the nearest sample rate. */
 418         cfg = wm8994->retune_mobile_cfg[block];
 419         best = 0;
 420         best_val = INT_MAX;
 421         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 422                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 423                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 424                     abs(pdata->retune_mobile_cfgs[i].rate
 425                         - wm8994->dac_rates[iface]) < best_val) {
 426                         best = i;
 427                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 428                                        - wm8994->dac_rates[iface]);
 429                 }
 430         }
 431
 432         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 433                 block,
 434                 pdata->retune_mobile_cfgs[best].name,
 435                 pdata->retune_mobile_cfgs[best].rate,
 436                 wm8994->dac_rates[iface]);
 437
 438         /* The EQ will be disabled while reconfiguring it, remember the
 439          * current configuration.
 440          */
 441         save = snd_soc_read(codec, base);
 442         save &= WM8994_AIF1DAC1_EQ_ENA;
 443
 444         for (i = 0; i < WM8994_EQ_REGS; i++)
 445                 snd_soc_update_bits(codec, base + i, 0xffff,
 446                                 pdata->retune_mobile_cfgs[best].regs[i]);
 447
 448         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 449 }
 450
 451 /* Icky as hell but saves code duplication */
 452 static int wm8994_get_retune_mobile_block(const char *name)
 453 {
 454         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 455                 return 0;
 456         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 457                 return 1;
 458         if (strcmp(name, "AIF2 EQ Mode") == 0)
 459                 return 2;
 460         return -EINVAL;
 461 }
 462
 463 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 464                                          struct snd_ctl_elem_value *ucontrol)
 465 {
 466         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 467         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 468         struct wm8994_pdata *pdata = wm8994->pdata;
 469         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 470         int value = ucontrol->value.integer.value[0];
 471
 472         if (block < 0)
 473                 return block;
 474
 475         if (value >= pdata->num_retune_mobile_cfgs)
 476                 return -EINVAL;
 477
 478         wm8994->retune_mobile_cfg[block] = value;
 479
 480         wm8994_set_retune_mobile(codec, block);
 481
 482         return 0;
 483 }
 484
 485 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 486                                          struct snd_ctl_elem_value *ucontrol)
 487 {
 488         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 489         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 490         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 491
 492         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 493
 494         return 0;
 495 }
 496
 497 static const char *aif_chan_src_text[] = {
 498         "Left", "Right"
 499 };
 500
 501 static const struct soc_enum aif1adcl_src =
 502         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 503
 504 static const struct soc_enum aif1adcr_src =
 505         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 506
 507 static const struct soc_enum aif2adcl_src =
 508         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 509
 510 static const struct soc_enum aif2adcr_src =
 511         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 512
 513 static const struct soc_enum aif1dacl_src =
 514         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 515
 516 static const struct soc_enum aif1dacr_src =
 517         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 518
 519 static const struct soc_enum aif2dacl_src =
 520         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 521
 522 static const struct soc_enum aif2dacr_src =
 523         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 524
 525 static const char *osr_text[] = {
 526         "Low Power", "High Performance",
 527 };
 528
 529 static const struct soc_enum dac_osr =
 530         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 531
 532 static const struct soc_enum adc_osr =
 533         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 534
 535 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 536 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 537                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 538                  1, 119, 0, digital_tlv),
 539 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 540                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 541                  1, 119, 0, digital_tlv),
 542 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 543                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 544                  1, 119, 0, digital_tlv),
 545
 546 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 547 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 548 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 549 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 550
 551 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 552 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 553 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 554 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 555
 556 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 557                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 558 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 559                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 560 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 561                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 562
 563 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 564 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 565
 566 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 567 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 568 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 569
 570 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 571 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 572 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 573
 574 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 575 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 576 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 577
 578 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 579 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 580 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 581
 582 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 583                5, 12, 0, st_tlv),
 584 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 585                0, 12, 0, st_tlv),
 586 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 587                5, 12, 0, st_tlv),
 588 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 589                0, 12, 0, st_tlv),
 590 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 591 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 592
 593 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 594 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 595
 596 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 597 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 598
 599 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 600 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 601
 602 SOC_ENUM("ADC OSR", adc_osr),
 603 SOC_ENUM("DAC OSR", dac_osr),
 604
 605 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 606                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 607 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 608              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 609
 610 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 611                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 612 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 613              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 614
 615 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 616                6, 1, 1, wm_hubs_spkmix_tlv),
 617 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 618                2, 1, 1, wm_hubs_spkmix_tlv),
 619
 620 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 621                6, 1, 1, wm_hubs_spkmix_tlv),
 622 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 623                2, 1, 1, wm_hubs_spkmix_tlv),
 624
 625 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 626                10, 15, 0, wm8994_3d_tlv),
 627 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 628            8, 1, 0),
 629 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 630                10, 15, 0, wm8994_3d_tlv),
 631 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 632            8, 1, 0),
 633 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 634                10, 15, 0, wm8994_3d_tlv),
 635 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 636            8, 1, 0),
 637 };
 638
 639 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 640 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 641                eq_tlv),
 642 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 643                eq_tlv),
 644 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 645                eq_tlv),
 646 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 647                eq_tlv),
 648 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 649                eq_tlv),
 650
 651 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 652                eq_tlv),
 653 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 654                eq_tlv),
 655 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 656                eq_tlv),
 657 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 658                eq_tlv),
 659 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 660                eq_tlv),
 661
 662 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 663                eq_tlv),
 664 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 665                eq_tlv),
 666 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 667                eq_tlv),
 668 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 669                eq_tlv),
 670 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 671                eq_tlv),
 672 };
 673
 674 static const char *wm8958_ng_text[] = {
 675         "30ms", "125ms", "250ms", "500ms",
 676 };
 677
 678 static const struct soc_enum wm8958_aif1dac1_ng_hold =
 679         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
 680                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
 681
 682 static const struct soc_enum wm8958_aif1dac2_ng_hold =
 683         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
 684                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
 685
 686 static const struct soc_enum wm8958_aif2dac_ng_hold =
 687         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
 688                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
 689
 690 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 691 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 692
 693 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 694            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 695 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 696 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 697                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 698                7, 1, ng_tlv),
 699
 700 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 701            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 702 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 703 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 704                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 705                7, 1, ng_tlv),
 706
 707 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 708            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 709 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 710 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 711                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 712                7, 1, ng_tlv),
 713 };
 714
 715 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 716 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 717                mixin_boost_tlv),
 718 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 719                mixin_boost_tlv),
 720 };
 721
 722 /* We run all mode setting through a function to enforce audio mode */
 723 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
 724 {
 725         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 726
 727         if (!wm8994->jackdet || !wm8994->jack_cb)
 728                 return;
 729
 730         if (wm8994->active_refcount)
 731                 mode = WM1811_JACKDET_MODE_AUDIO;
 732
 733         if (mode == wm8994->jackdet_mode)
 734                 return;
 735
 736         wm8994->jackdet_mode = mode;
 737
 738         /* Always use audio mode to detect while the system is active */
 739         if (mode != WM1811_JACKDET_MODE_NONE)
 740                 mode = WM1811_JACKDET_MODE_AUDIO;
 741
 742         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 743                             WM1811_JACKDET_MODE_MASK, mode);
 744 }
 745
 746 static void active_reference(struct snd_soc_codec *codec)
 747 {
 748         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 749
 750         mutex_lock(&wm8994->accdet_lock);
 751
 752         wm8994->active_refcount++;
 753
 754         dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
 755                 wm8994->active_refcount);
 756
 757         /* If we're using jack detection go into audio mode */
 758         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
 759
 760         mutex_unlock(&wm8994->accdet_lock);
 761 }
 762
 763 static void active_dereference(struct snd_soc_codec *codec)
 764 {
 765         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 766         u16 mode;
 767
 768         mutex_lock(&wm8994->accdet_lock);
 769
 770         wm8994->active_refcount--;
 771
 772         dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
 773                 wm8994->active_refcount);
 774
 775         if (wm8994->active_refcount == 0) {
 776                 /* Go into appropriate detection only mode */
 777                 if (wm8994->jack_mic || wm8994->mic_detecting)
 778                         mode = WM1811_JACKDET_MODE_MIC;
 779                 else
 780                         mode = WM1811_JACKDET_MODE_JACK;
 781
 782                 wm1811_jackdet_set_mode(codec, mode);
 783         }
 784
 785         mutex_unlock(&wm8994->accdet_lock);
 786 }
 787
 788 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 789                          struct snd_kcontrol *kcontrol, int event)
 790 {
 791         struct snd_soc_codec *codec = w->codec;
 792
 793         switch (event) {
 794         case SND_SOC_DAPM_PRE_PMU:
 795                 return configure_clock(codec);
 796
 797         case SND_SOC_DAPM_POST_PMD:
 798                 configure_clock(codec);
 799                 break;
 800         }
 801
 802         return 0;
 803 }
 804
 805 static void vmid_reference(struct snd_soc_codec *codec)
 806 {
 807         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 808
 809         pm_runtime_get_sync(codec->dev);
 810
 811         wm8994->vmid_refcount++;
 812
 813         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
 814                 wm8994->vmid_refcount);
 815
 816         if (wm8994->vmid_refcount == 1) {
 817                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 818                                     WM8994_LINEOUT1_DISCH |
 819                                     WM8994_LINEOUT2_DISCH, 0);
 820
 821                 wm_hubs_vmid_ena(codec);
 822
 823                 switch (wm8994->vmid_mode) {
 824                 default:
 825                         WARN_ON(NULL == "Invalid VMID mode");
 826                 case WM8994_VMID_NORMAL:
 827                         /* Startup bias, VMID ramp & buffer */
 828                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 829                                             WM8994_BIAS_SRC |
 830                                             WM8994_VMID_DISCH |
 831                                             WM8994_STARTUP_BIAS_ENA |
 832                                             WM8994_VMID_BUF_ENA |
 833                                             WM8994_VMID_RAMP_MASK,
 834                                             WM8994_BIAS_SRC |
 835                                             WM8994_STARTUP_BIAS_ENA |
 836                                             WM8994_VMID_BUF_ENA |
 837                                             (0x3 << WM8994_VMID_RAMP_SHIFT));
 838
 839                         /* Main bias enable, VMID=2x40k */
 840                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 841                                             WM8994_BIAS_ENA |
 842                                             WM8994_VMID_SEL_MASK,
 843                                             WM8994_BIAS_ENA | 0x2);
 844
 845                         msleep(50);
 846
 847                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 848                                             WM8994_VMID_RAMP_MASK |
 849                                             WM8994_BIAS_SRC,
 850                                             0);
 851                         break;
 852
 853                 case WM8994_VMID_FORCE:
 854                         /* Startup bias, slow VMID ramp & buffer */
 855                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 856                                             WM8994_BIAS_SRC |
 857                                             WM8994_VMID_DISCH |
 858                                             WM8994_STARTUP_BIAS_ENA |
 859                                             WM8994_VMID_BUF_ENA |
 860                                             WM8994_VMID_RAMP_MASK,
 861                                             WM8994_BIAS_SRC |
 862                                             WM8994_STARTUP_BIAS_ENA |
 863                                             WM8994_VMID_BUF_ENA |
 864                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
 865
 866                         /* Main bias enable, VMID=2x40k */
 867                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 868                                             WM8994_BIAS_ENA |
 869                                             WM8994_VMID_SEL_MASK,
 870                                             WM8994_BIAS_ENA | 0x2);
 871
 872                         msleep(400);
 873
 874                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 875                                             WM8994_VMID_RAMP_MASK |
 876                                             WM8994_BIAS_SRC,
 877                                             0);
 878                         break;
 879                 }
 880         }
 881 }
 882
 883 static void vmid_dereference(struct snd_soc_codec *codec)
 884 {
 885         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 886
 887         wm8994->vmid_refcount--;
 888
 889         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
 890                 wm8994->vmid_refcount);
 891
 892         if (wm8994->vmid_refcount == 0) {
 893                 if (wm8994->hubs.lineout1_se)
 894                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 895                                             WM8994_LINEOUT1N_ENA |
 896                                             WM8994_LINEOUT1P_ENA,
 897                                             WM8994_LINEOUT1N_ENA |
 898                                             WM8994_LINEOUT1P_ENA);
 899
 900                 if (wm8994->hubs.lineout2_se)
 901                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 902                                             WM8994_LINEOUT2N_ENA |
 903                                             WM8994_LINEOUT2P_ENA,
 904                                             WM8994_LINEOUT2N_ENA |
 905                                             WM8994_LINEOUT2P_ENA);
 906
 907                 /* Start discharging VMID */
 908                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 909                                     WM8994_BIAS_SRC |
 910                                     WM8994_VMID_DISCH,
 911                                     WM8994_BIAS_SRC |
 912                                     WM8994_VMID_DISCH);
 913
 914                 switch (wm8994->vmid_mode) {
 915                 case WM8994_VMID_FORCE:
 916                         msleep(350);
 917                         break;
 918                 default:
 919                         break;
 920                 }
 921
 922                 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
 923                                     WM8994_VROI, WM8994_VROI);
 924
 925                 /* Active discharge */
 926                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 927                                     WM8994_LINEOUT1_DISCH |
 928                                     WM8994_LINEOUT2_DISCH,
 929                                     WM8994_LINEOUT1_DISCH |
 930                                     WM8994_LINEOUT2_DISCH);
 931
 932                 msleep(150);
 933
 934                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 935                                     WM8994_LINEOUT1N_ENA |
 936                                     WM8994_LINEOUT1P_ENA |
 937                                     WM8994_LINEOUT2N_ENA |
 938                                     WM8994_LINEOUT2P_ENA, 0);
 939
 940                 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
 941                                     WM8994_VROI, 0);
 942
 943                 /* Switch off startup biases */
 944                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 945                                     WM8994_BIAS_SRC |
 946                                     WM8994_STARTUP_BIAS_ENA |
 947                                     WM8994_VMID_BUF_ENA |
 948                                     WM8994_VMID_RAMP_MASK, 0);
 949
 950                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 951                                     WM8994_BIAS_ENA | WM8994_VMID_SEL_MASK, 0);
 952
 953                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 954                                     WM8994_VMID_RAMP_MASK, 0);
 955         }
 956
 957         pm_runtime_put(codec->dev);
 958 }
 959
 960 static int vmid_event(struct snd_soc_dapm_widget *w,
 961                       struct snd_kcontrol *kcontrol, int event)
 962 {
 963         struct snd_soc_codec *codec = w->codec;
 964
 965         switch (event) {
 966         case SND_SOC_DAPM_PRE_PMU:
 967                 vmid_reference(codec);
 968                 break;
 969
 970         case SND_SOC_DAPM_POST_PMD:
 971                 vmid_dereference(codec);
 972                 break;
 973         }
 974
 975         return 0;
 976 }
 977
 978 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
 979 {
 980         int source = 0;  /* GCC flow analysis can't track enable */
 981         int reg, reg_r;
 982
 983         /* We also need the same AIF source for L/R and only one path */
 984         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 985         switch (reg) {
 986         case WM8994_AIF2DACL_TO_DAC1L:
 987                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 988                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 989                 break;
 990         case WM8994_AIF1DAC2L_TO_DAC1L:
 991                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 992                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 993                 break;
 994         case WM8994_AIF1DAC1L_TO_DAC1L:
 995                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 996                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 997                 break;
 998         default:
 999                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1000                 return false;
1001         }
1002
1003         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1004         if (reg_r != reg) {
1005                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1006                 return false;
1007         }
1008
1009         /* Set the source up */
1010         snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1011                             WM8994_CP_DYN_SRC_SEL_MASK, source);
1012
1013         return true;
1014 }
1015
1016 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1017                       struct snd_kcontrol *kcontrol, int event)
1018 {
1019         struct snd_soc_codec *codec = w->codec;
1020         struct wm8994 *control = codec->control_data;
1021         int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1022         int i;
1023         int dac;
1024         int adc;
1025         int val;
1026
1027         switch (control->type) {
1028         case WM8994:
1029         case WM8958:
1030                 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1031                 break;
1032         default:
1033                 break;
1034         }
1035
1036         switch (event) {
1037         case SND_SOC_DAPM_PRE_PMU:
1038                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1039                 if ((val & WM8994_AIF1ADCL_SRC) &&
1040                     (val & WM8994_AIF1ADCR_SRC))
1041                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1042                 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1043                          !(val & WM8994_AIF1ADCR_SRC))
1044                         adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1045                 else
1046                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1047                                 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1048
1049                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1050                 if ((val & WM8994_AIF1DACL_SRC) &&
1051                     (val & WM8994_AIF1DACR_SRC))
1052                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1053                 else if (!(val & WM8994_AIF1DACL_SRC) &&
1054                          !(val & WM8994_AIF1DACR_SRC))
1055                         dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1056                 else
1057                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1058                                 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1059
1060                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1061                                     mask, adc);
1062                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1063                                     mask, dac);
1064                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1065                                     WM8994_AIF1DSPCLK_ENA |
1066                                     WM8994_SYSDSPCLK_ENA,
1067                                     WM8994_AIF1DSPCLK_ENA |
1068                                     WM8994_SYSDSPCLK_ENA);
1069                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1070                                     WM8994_AIF1ADC1R_ENA |
1071                                     WM8994_AIF1ADC1L_ENA |
1072                                     WM8994_AIF1ADC2R_ENA |
1073                                     WM8994_AIF1ADC2L_ENA);
1074                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1075                                     WM8994_AIF1DAC1R_ENA |
1076                                     WM8994_AIF1DAC1L_ENA |
1077                                     WM8994_AIF1DAC2R_ENA |
1078                                     WM8994_AIF1DAC2L_ENA);
1079                 break;
1080
1081         case SND_SOC_DAPM_POST_PMU:
1082                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1083                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1084                                       snd_soc_read(codec,
1085                                                    wm8994_vu_bits[i].reg));
1086                 break;
1087
1088         case SND_SOC_DAPM_PRE_PMD:
1089         case SND_SOC_DAPM_POST_PMD:
1090                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1091                                     mask, 0);
1092                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1093                                     mask, 0);
1094
1095                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1096                 if (val & WM8994_AIF2DSPCLK_ENA)
1097                         val = WM8994_SYSDSPCLK_ENA;
1098                 else
1099                         val = 0;
1100                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1101                                     WM8994_SYSDSPCLK_ENA |
1102                                     WM8994_AIF1DSPCLK_ENA, val);
1103                 break;
1104         }
1105
1106         return 0;
1107 }
1108
1109 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1110                       struct snd_kcontrol *kcontrol, int event)
1111 {
1112         struct snd_soc_codec *codec = w->codec;
1113         int i;
1114         int dac;
1115         int adc;
1116         int val;
1117
1118         switch (event) {
1119         case SND_SOC_DAPM_PRE_PMU:
1120                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1121                 if ((val & WM8994_AIF2ADCL_SRC) &&
1122                     (val & WM8994_AIF2ADCR_SRC))
1123                         adc = WM8994_AIF2ADCR_ENA;
1124                 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1125                          !(val & WM8994_AIF2ADCR_SRC))
1126                         adc = WM8994_AIF2ADCL_ENA;
1127                 else
1128                         adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1129
1130
1131                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1132                 if ((val & WM8994_AIF2DACL_SRC) &&
1133                     (val & WM8994_AIF2DACR_SRC))
1134                         dac = WM8994_AIF2DACR_ENA;
1135                 else if (!(val & WM8994_AIF2DACL_SRC) &&
1136                          !(val & WM8994_AIF2DACR_SRC))
1137                         dac = WM8994_AIF2DACL_ENA;
1138                 else
1139                         dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1140
1141                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1142                                     WM8994_AIF2ADCL_ENA |
1143                                     WM8994_AIF2ADCR_ENA, adc);
1144                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1145                                     WM8994_AIF2DACL_ENA |
1146                                     WM8994_AIF2DACR_ENA, dac);
1147                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1148                                     WM8994_AIF2DSPCLK_ENA |
1149                                     WM8994_SYSDSPCLK_ENA,
1150                                     WM8994_AIF2DSPCLK_ENA |
1151                                     WM8994_SYSDSPCLK_ENA);
1152                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1153                                     WM8994_AIF2ADCL_ENA |
1154                                     WM8994_AIF2ADCR_ENA,
1155                                     WM8994_AIF2ADCL_ENA |
1156                                     WM8994_AIF2ADCR_ENA);
1157                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1158                                     WM8994_AIF2DACL_ENA |
1159                                     WM8994_AIF2DACR_ENA,
1160                                     WM8994_AIF2DACL_ENA |
1161                                     WM8994_AIF2DACR_ENA);
1162                 break;
1163
1164         case SND_SOC_DAPM_POST_PMU:
1165                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1166                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1167                                       snd_soc_read(codec,
1168                                                    wm8994_vu_bits[i].reg));
1169                 break;
1170
1171         case SND_SOC_DAPM_PRE_PMD:
1172         case SND_SOC_DAPM_POST_PMD:
1173                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1174                                     WM8994_AIF2DACL_ENA |
1175                                     WM8994_AIF2DACR_ENA, 0);
1176                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1177                                     WM8994_AIF2ADCL_ENA |
1178                                     WM8994_AIF2ADCR_ENA, 0);
1179
1180                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1181                 if (val & WM8994_AIF1DSPCLK_ENA)
1182                         val = WM8994_SYSDSPCLK_ENA;
1183                 else
1184                         val = 0;
1185                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1186                                     WM8994_SYSDSPCLK_ENA |
1187                                     WM8994_AIF2DSPCLK_ENA, val);
1188                 break;
1189         }
1190
1191         return 0;
1192 }
1193
1194 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1195                            struct snd_kcontrol *kcontrol, int event)
1196 {
1197         struct snd_soc_codec *codec = w->codec;
1198         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1199
1200         switch (event) {
1201         case SND_SOC_DAPM_PRE_PMU:
1202                 wm8994->aif1clk_enable = 1;
1203                 break;
1204         case SND_SOC_DAPM_POST_PMD:
1205                 wm8994->aif1clk_disable = 1;
1206                 break;
1207         }
1208
1209         return 0;
1210 }
1211
1212 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1213                            struct snd_kcontrol *kcontrol, int event)
1214 {
1215         struct snd_soc_codec *codec = w->codec;
1216         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1217
1218         switch (event) {
1219         case SND_SOC_DAPM_PRE_PMU:
1220                 wm8994->aif2clk_enable = 1;
1221                 break;
1222         case SND_SOC_DAPM_POST_PMD:
1223                 wm8994->aif2clk_disable = 1;
1224                 break;
1225         }
1226
1227         return 0;
1228 }
1229
1230 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1231                           struct snd_kcontrol *kcontrol, int event)
1232 {
1233         struct snd_soc_codec *codec = w->codec;
1234         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1235
1236         switch (event) {
1237         case SND_SOC_DAPM_PRE_PMU:
1238                 if (wm8994->aif1clk_enable) {
1239                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1240                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1241                                             WM8994_AIF1CLK_ENA_MASK,
1242                                             WM8994_AIF1CLK_ENA);
1243                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1244                         wm8994->aif1clk_enable = 0;
1245                 }
1246                 if (wm8994->aif2clk_enable) {
1247                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1248                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1249                                             WM8994_AIF2CLK_ENA_MASK,
1250                                             WM8994_AIF2CLK_ENA);
1251                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1252                         wm8994->aif2clk_enable = 0;
1253                 }
1254                 break;
1255         }
1256
1257         /* We may also have postponed startup of DSP, handle that. */
1258         wm8958_aif_ev(w, kcontrol, event);
1259
1260         return 0;
1261 }
1262
1263 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1264                            struct snd_kcontrol *kcontrol, int event)
1265 {
1266         struct snd_soc_codec *codec = w->codec;
1267         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1268
1269         switch (event) {
1270         case SND_SOC_DAPM_POST_PMD:
1271                 if (wm8994->aif1clk_disable) {
1272                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1273                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1274                                             WM8994_AIF1CLK_ENA_MASK, 0);
1275                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1276                         wm8994->aif1clk_disable = 0;
1277                 }
1278                 if (wm8994->aif2clk_disable) {
1279                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1280                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1281                                             WM8994_AIF2CLK_ENA_MASK, 0);
1282                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1283                         wm8994->aif2clk_disable = 0;
1284                 }
1285                 break;
1286         }
1287
1288         return 0;
1289 }
1290
1291 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1292                       struct snd_kcontrol *kcontrol, int event)
1293 {
1294         late_enable_ev(w, kcontrol, event);
1295         return 0;
1296 }
1297
1298 static int micbias_ev(struct snd_soc_dapm_widget *w,
1299                       struct snd_kcontrol *kcontrol, int event)
1300 {
1301         late_enable_ev(w, kcontrol, event);
1302         return 0;
1303 }
1304
1305 static int dac_ev(struct snd_soc_dapm_widget *w,
1306                   struct snd_kcontrol *kcontrol, int event)
1307 {
1308         struct snd_soc_codec *codec = w->codec;
1309         unsigned int mask = 1 << w->shift;
1310
1311         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1312                             mask, mask);
1313         return 0;
1314 }
1315
1316 static const char *adc_mux_text[] = {
1317         "ADC",
1318         "DMIC",
1319 };
1320
1321 static const struct soc_enum adc_enum =
1322         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1323
1324 static const struct snd_kcontrol_new adcl_mux =
1325         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1326
1327 static const struct snd_kcontrol_new adcr_mux =
1328         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1329
1330 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1331 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1332 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1333 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1334 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1335 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1336 };
1337
1338 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1339 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1340 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1341 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1342 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1343 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1344 };
1345
1346 /* Debugging; dump chip status after DAPM transitions */
1347 static int post_ev(struct snd_soc_dapm_widget *w,
1348             struct snd_kcontrol *kcontrol, int event)
1349 {
1350         struct snd_soc_codec *codec = w->codec;
1351         dev_dbg(codec->dev, "SRC status: %x\n",
1352                 snd_soc_read(codec,
1353                              WM8994_RATE_STATUS));
1354         return 0;
1355 }
1356
1357 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1358 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1359                 1, 1, 0),
1360 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1361                 0, 1, 0),
1362 };
1363
1364 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1365 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1366                 1, 1, 0),
1367 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1368                 0, 1, 0),
1369 };
1370
1371 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1372 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1373                 1, 1, 0),
1374 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1375                 0, 1, 0),
1376 };
1377
1378 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1379 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1380                 1, 1, 0),
1381 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1382                 0, 1, 0),
1383 };
1384
1385 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1386 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1387                 5, 1, 0),
1388 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1389                 4, 1, 0),
1390 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1391                 2, 1, 0),
1392 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1393                 1, 1, 0),
1394 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1395                 0, 1, 0),
1396 };
1397
1398 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1399 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1400                 5, 1, 0),
1401 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1402                 4, 1, 0),
1403 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1404                 2, 1, 0),
1405 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1406                 1, 1, 0),
1407 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1408                 0, 1, 0),
1409 };
1410
1411 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1412 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1413         .info = snd_soc_info_volsw, \
1414         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1415         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1416
1417 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1418                               struct snd_ctl_elem_value *ucontrol)
1419 {
1420         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1421         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1422         struct snd_soc_codec *codec = w->codec;
1423         int ret;
1424
1425         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1426
1427         wm_hubs_update_class_w(codec);
1428
1429         return ret;
1430 }
1431
1432 static const struct snd_kcontrol_new dac1l_mix[] = {
1433 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1434                       5, 1, 0),
1435 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1436                       4, 1, 0),
1437 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1438                       2, 1, 0),
1439 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1440                       1, 1, 0),
1441 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1442                       0, 1, 0),
1443 };
1444
1445 static const struct snd_kcontrol_new dac1r_mix[] = {
1446 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1447                       5, 1, 0),
1448 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1449                       4, 1, 0),
1450 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1451                       2, 1, 0),
1452 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1453                       1, 1, 0),
1454 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1455                       0, 1, 0),
1456 };
1457
1458 static const char *sidetone_text[] = {
1459         "ADC/DMIC1", "DMIC2",
1460 };
1461
1462 static const struct soc_enum sidetone1_enum =
1463         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1464
1465 static const struct snd_kcontrol_new sidetone1_mux =
1466         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1467
1468 static const struct soc_enum sidetone2_enum =
1469         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1470
1471 static const struct snd_kcontrol_new sidetone2_mux =
1472         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1473
1474 static const char *aif1dac_text[] = {
1475         "AIF1DACDAT", "AIF3DACDAT",
1476 };
1477
1478 static const struct soc_enum aif1dac_enum =
1479         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1480
1481 static const struct snd_kcontrol_new aif1dac_mux =
1482         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1483
1484 static const char *aif2dac_text[] = {
1485         "AIF2DACDAT", "AIF3DACDAT",
1486 };
1487
1488 static const struct soc_enum aif2dac_enum =
1489         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1490
1491 static const struct snd_kcontrol_new aif2dac_mux =
1492         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1493
1494 static const char *aif2adc_text[] = {
1495         "AIF2ADCDAT", "AIF3DACDAT",
1496 };
1497
1498 static const struct soc_enum aif2adc_enum =
1499         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1500
1501 static const struct snd_kcontrol_new aif2adc_mux =
1502         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1503
1504 static const char *aif3adc_text[] = {
1505         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1506 };
1507
1508 static const struct soc_enum wm8994_aif3adc_enum =
1509         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1510
1511 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1512         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1513
1514 static const struct soc_enum wm8958_aif3adc_enum =
1515         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1516
1517 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1518         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1519
1520 static const char *mono_pcm_out_text[] = {
1521         "None", "AIF2ADCL", "AIF2ADCR",
1522 };
1523
1524 static const struct soc_enum mono_pcm_out_enum =
1525         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1526
1527 static const struct snd_kcontrol_new mono_pcm_out_mux =
1528         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1529
1530 static const char *aif2dac_src_text[] = {
1531         "AIF2", "AIF3",
1532 };
1533
1534 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1535 static const struct soc_enum aif2dacl_src_enum =
1536         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1537
1538 static const struct snd_kcontrol_new aif2dacl_src_mux =
1539         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1540
1541 static const struct soc_enum aif2dacr_src_enum =
1542         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1543
1544 static const struct snd_kcontrol_new aif2dacr_src_mux =
1545         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1546
1547 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1548 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1549         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1550 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1551         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1552
1553 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1554         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1555 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1556         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1557 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1558         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1559 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1560         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1561 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1562         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1563
1564 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1565                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1566                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1567 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1568                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1569                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1570 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1571                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1572 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1573                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1574
1575 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1576 };
1577
1578 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1579 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1580                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1581                     SND_SOC_DAPM_PRE_PMD),
1582 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1583                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1584                     SND_SOC_DAPM_PRE_PMD),
1585 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1586 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1587                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1588 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1589                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1590 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1591 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1592 };
1593
1594 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1595 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1596         dac_ev, SND_SOC_DAPM_PRE_PMU),
1597 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1598         dac_ev, SND_SOC_DAPM_PRE_PMU),
1599 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1600         dac_ev, SND_SOC_DAPM_PRE_PMU),
1601 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1602         dac_ev, SND_SOC_DAPM_PRE_PMU),
1603 };
1604
1605 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1606 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1607 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1608 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1609 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1610 };
1611
1612 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1613 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1614                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1615 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1616                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1617 };
1618
1619 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1620 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1621 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1622 };
1623
1624 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1625 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1626 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1627 SND_SOC_DAPM_INPUT("Clock"),
1628
1629 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1630                       SND_SOC_DAPM_PRE_PMU),
1631 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1632                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1633
1634 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1635                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1636
1637 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1638 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1639 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1640
1641 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1642                      0, SND_SOC_NOPM, 9, 0),
1643 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1644                      0, SND_SOC_NOPM, 8, 0),
1645 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1646                       SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1647                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1648 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1649                       SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1650                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1651
1652 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1653                      0, SND_SOC_NOPM, 11, 0),
1654 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1655                      0, SND_SOC_NOPM, 10, 0),
1656 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1657                       SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1658                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1659 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1660                       SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1661                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1662
1663 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1664                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1665 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1666                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1667
1668 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1669                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1670 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1671                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1672
1673 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1674                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1675 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1676                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1677
1678 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1679 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1680
1681 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1682                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1683 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1684                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1685
1686 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1687                      SND_SOC_NOPM, 13, 0),
1688 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1689                      SND_SOC_NOPM, 12, 0),
1690 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1691                       SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1692                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1693 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1694                       SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1695                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1696
1697 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1698 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1699 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1700 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT",  NULL, 0, SND_SOC_NOPM, 0, 0),
1701
1702 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1703 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1704 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1705
1706 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1707 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1708
1709 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1710
1711 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1712 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1713 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1714 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1715
1716 /* Power is done with the muxes since the ADC power also controls the
1717  * downsampling chain, the chip will automatically manage the analogue
1718  * specific portions.
1719  */
1720 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1721 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1722
1723 SND_SOC_DAPM_POST("Debug log", post_ev),
1724 };
1725
1726 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1727 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1728 };
1729
1730 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1731 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1732 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1733 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1734 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1735 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1736 };
1737
1738 static const struct snd_soc_dapm_route intercon[] = {
1739         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1740         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1741
1742         { "DSP1CLK", NULL, "CLK_SYS" },
1743         { "DSP2CLK", NULL, "CLK_SYS" },
1744         { "DSPINTCLK", NULL, "CLK_SYS" },
1745
1746         { "AIF1ADC1L", NULL, "AIF1CLK" },
1747         { "AIF1ADC1L", NULL, "DSP1CLK" },
1748         { "AIF1ADC1R", NULL, "AIF1CLK" },
1749         { "AIF1ADC1R", NULL, "DSP1CLK" },
1750         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1751
1752         { "AIF1DAC1L", NULL, "AIF1CLK" },
1753         { "AIF1DAC1L", NULL, "DSP1CLK" },
1754         { "AIF1DAC1R", NULL, "AIF1CLK" },
1755         { "AIF1DAC1R", NULL, "DSP1CLK" },
1756         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1757
1758         { "AIF1ADC2L", NULL, "AIF1CLK" },
1759         { "AIF1ADC2L", NULL, "DSP1CLK" },
1760         { "AIF1ADC2R", NULL, "AIF1CLK" },
1761         { "AIF1ADC2R", NULL, "DSP1CLK" },
1762         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1763
1764         { "AIF1DAC2L", NULL, "AIF1CLK" },
1765         { "AIF1DAC2L", NULL, "DSP1CLK" },
1766         { "AIF1DAC2R", NULL, "AIF1CLK" },
1767         { "AIF1DAC2R", NULL, "DSP1CLK" },
1768         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1769
1770         { "AIF2ADCL", NULL, "AIF2CLK" },
1771         { "AIF2ADCL", NULL, "DSP2CLK" },
1772         { "AIF2ADCR", NULL, "AIF2CLK" },
1773         { "AIF2ADCR", NULL, "DSP2CLK" },
1774         { "AIF2ADCR", NULL, "DSPINTCLK" },
1775
1776         { "AIF2DACL", NULL, "AIF2CLK" },
1777         { "AIF2DACL", NULL, "DSP2CLK" },
1778         { "AIF2DACR", NULL, "AIF2CLK" },
1779         { "AIF2DACR", NULL, "DSP2CLK" },
1780         { "AIF2DACR", NULL, "DSPINTCLK" },
1781
1782         { "DMIC1L", NULL, "DMIC1DAT" },
1783         { "DMIC1L", NULL, "CLK_SYS" },
1784         { "DMIC1R", NULL, "DMIC1DAT" },
1785         { "DMIC1R", NULL, "CLK_SYS" },
1786         { "DMIC2L", NULL, "DMIC2DAT" },
1787         { "DMIC2L", NULL, "CLK_SYS" },
1788         { "DMIC2R", NULL, "DMIC2DAT" },
1789         { "DMIC2R", NULL, "CLK_SYS" },
1790
1791         { "ADCL", NULL, "AIF1CLK" },
1792         { "ADCL", NULL, "DSP1CLK" },
1793         { "ADCL", NULL, "DSPINTCLK" },
1794
1795         { "ADCR", NULL, "AIF1CLK" },
1796         { "ADCR", NULL, "DSP1CLK" },
1797         { "ADCR", NULL, "DSPINTCLK" },
1798
1799         { "ADCL Mux", "ADC", "ADCL" },
1800         { "ADCL Mux", "DMIC", "DMIC1L" },
1801         { "ADCR Mux", "ADC", "ADCR" },
1802         { "ADCR Mux", "DMIC", "DMIC1R" },
1803
1804         { "DAC1L", NULL, "AIF1CLK" },
1805         { "DAC1L", NULL, "DSP1CLK" },
1806         { "DAC1L", NULL, "DSPINTCLK" },
1807
1808         { "DAC1R", NULL, "AIF1CLK" },
1809         { "DAC1R", NULL, "DSP1CLK" },
1810         { "DAC1R", NULL, "DSPINTCLK" },
1811
1812         { "DAC2L", NULL, "AIF2CLK" },
1813         { "DAC2L", NULL, "DSP2CLK" },
1814         { "DAC2L", NULL, "DSPINTCLK" },
1815
1816         { "DAC2R", NULL, "AIF2DACR" },
1817         { "DAC2R", NULL, "AIF2CLK" },
1818         { "DAC2R", NULL, "DSP2CLK" },
1819         { "DAC2R", NULL, "DSPINTCLK" },
1820
1821         { "TOCLK", NULL, "CLK_SYS" },
1822
1823         { "AIF1DACDAT", NULL, "AIF1 Playback" },
1824         { "AIF2DACDAT", NULL, "AIF2 Playback" },
1825         { "AIF3DACDAT", NULL, "AIF3 Playback" },
1826
1827         { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1828         { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1829         { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1830
1831         /* AIF1 outputs */
1832         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1833         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1834         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1835
1836         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1837         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1838         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1839
1840         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1841         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1842         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1843
1844         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1845         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1846         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1847
1848         /* Pin level routing for AIF3 */
1849         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1850         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1851         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1852         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1853
1854         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1855         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1856         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1857         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1858         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1859         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1860         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1861
1862         /* DAC1 inputs */
1863         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1864         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1865         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1866         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1867         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1868
1869         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1870         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1871         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1872         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1873         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1874
1875         /* DAC2/AIF2 outputs  */
1876         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1877         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1878         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1879         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1880         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1881         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1882
1883         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1884         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1885         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1886         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1887         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1888         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1889
1890         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1891         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1892         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1893         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1894
1895         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1896
1897         /* AIF3 output */
1898         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1899         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1900         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1901         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1902         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1903         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1904         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1905         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1906
1907         /* Sidetone */
1908         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1909         { "Left Sidetone", "DMIC2", "DMIC2L" },
1910         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1911         { "Right Sidetone", "DMIC2", "DMIC2R" },
1912
1913         /* Output stages */
1914         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1915         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1916
1917         { "SPKL", "DAC1 Switch", "DAC1L" },
1918         { "SPKL", "DAC2 Switch", "DAC2L" },
1919
1920         { "SPKR", "DAC1 Switch", "DAC1R" },
1921         { "SPKR", "DAC2 Switch", "DAC2R" },
1922
1923         { "Left Headphone Mux", "DAC", "DAC1L" },
1924         { "Right Headphone Mux", "DAC", "DAC1R" },
1925 };
1926
1927 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1928         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1929         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1930         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1931         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1932         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1933         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1934         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1935         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1936 };
1937
1938 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1939         { "DAC1L", NULL, "DAC1L Mixer" },
1940         { "DAC1R", NULL, "DAC1R Mixer" },
1941         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1942         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1943 };
1944
1945 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1946         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1947         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1948         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1949         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1950         { "MICBIAS1", NULL, "CLK_SYS" },
1951         { "MICBIAS1", NULL, "MICBIAS Supply" },
1952         { "MICBIAS2", NULL, "CLK_SYS" },
1953         { "MICBIAS2", NULL, "MICBIAS Supply" },
1954 };
1955
1956 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1957         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1958         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1959         { "MICBIAS1", NULL, "VMID" },
1960         { "MICBIAS2", NULL, "VMID" },
1961 };
1962
1963 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1964         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1965         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1966
1967         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1968         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1969         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1970         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1971
1972         { "AIF3DACDAT", NULL, "AIF3" },
1973         { "AIF3ADCDAT", NULL, "AIF3" },
1974
1975         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1976         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1977
1978         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1979 };
1980
1981 /* The size in bits of the FLL divide multiplied by 10
1982  * to allow rounding later */
1983 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1984
1985 struct fll_div {
1986         u16 outdiv;
1987         u16 n;
1988         u16 k;
1989         u16 clk_ref_div;
1990         u16 fll_fratio;
1991 };
1992
1993 static int wm8994_get_fll_config(struct fll_div *fll,
1994                                  int freq_in, int freq_out)
1995 {
1996         u64 Kpart;
1997         unsigned int K, Ndiv, Nmod;
1998
1999         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2000
2001         /* Scale the input frequency down to <= 13.5MHz */
2002         fll->clk_ref_div = 0;
2003         while (freq_in > 13500000) {
2004                 fll->clk_ref_div++;
2005                 freq_in /= 2;
2006
2007                 if (fll->clk_ref_div > 3)
2008                         return -EINVAL;
2009         }
2010         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2011
2012         /* Scale the output to give 90MHz<=Fvco<=100MHz */
2013         fll->outdiv = 3;
2014         while (freq_out * (fll->outdiv + 1) < 90000000) {
2015                 fll->outdiv++;
2016                 if (fll->outdiv > 63)
2017                         return -EINVAL;
2018         }
2019         freq_out *= fll->outdiv + 1;
2020         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2021
2022         if (freq_in > 1000000) {
2023                 fll->fll_fratio = 0;
2024         } else if (freq_in > 256000) {
2025                 fll->fll_fratio = 1;
2026                 freq_in *= 2;
2027         } else if (freq_in > 128000) {
2028                 fll->fll_fratio = 2;
2029                 freq_in *= 4;
2030         } else if (freq_in > 64000) {
2031                 fll->fll_fratio = 3;
2032                 freq_in *= 8;
2033         } else {
2034                 fll->fll_fratio = 4;
2035                 freq_in *= 16;
2036         }
2037         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2038
2039         /* Now, calculate N.K */
2040         Ndiv = freq_out / freq_in;
2041
2042         fll->n = Ndiv;
2043         Nmod = freq_out % freq_in;
2044         pr_debug("Nmod=%d\n", Nmod);
2045
2046         /* Calculate fractional part - scale up so we can round. */
2047         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2048
2049         do_div(Kpart, freq_in);
2050
2051         K = Kpart & 0xFFFFFFFF;
2052
2053         if ((K % 10) >= 5)
2054                 K += 5;
2055
2056         /* Move down to proper range now rounding is done */
2057         fll->k = K / 10;
2058
2059         pr_debug("N=%x K=%x\n", fll->n, fll->k);
2060
2061         return 0;
2062 }
2063
2064 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2065                           unsigned int freq_in, unsigned int freq_out)
2066 {
2067         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2068         struct wm8994 *control = wm8994->wm8994;
2069         int reg_offset, ret;
2070         struct fll_div fll;
2071         u16 reg, clk1, aif_reg, aif_src;
2072         unsigned long timeout;
2073         bool was_enabled;
2074
2075         switch (id) {
2076         case WM8994_FLL1:
2077                 reg_offset = 0;
2078                 id = 0;
2079                 aif_src = 0x10;
2080                 break;
2081         case WM8994_FLL2:
2082                 reg_offset = 0x20;
2083                 id = 1;
2084                 aif_src = 0x18;
2085                 break;
2086         default:
2087                 return -EINVAL;
2088         }
2089
2090         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2091         was_enabled = reg & WM8994_FLL1_ENA;
2092
2093         switch (src) {
2094         case 0:
2095                 /* Allow no source specification when stopping */
2096                 if (freq_out)
2097                         return -EINVAL;
2098                 src = wm8994->fll[id].src;
2099                 break;
2100         case WM8994_FLL_SRC_MCLK1:
2101         case WM8994_FLL_SRC_MCLK2:
2102         case WM8994_FLL_SRC_LRCLK:
2103         case WM8994_FLL_SRC_BCLK:
2104                 break;
2105         case WM8994_FLL_SRC_INTERNAL:
2106                 freq_in = 12000000;
2107                 freq_out = 12000000;
2108                 break;
2109         default:
2110                 return -EINVAL;
2111         }
2112
2113         /* Are we changing anything? */
2114         if (wm8994->fll[id].src == src &&
2115             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2116                 return 0;
2117
2118         /* If we're stopping the FLL redo the old config - no
2119          * registers will actually be written but we avoid GCC flow
2120          * analysis bugs spewing warnings.
2121          */
2122         if (freq_out)
2123                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2124         else
2125                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2126                                             wm8994->fll[id].out);
2127         if (ret < 0)
2128                 return ret;
2129
2130         /* Make sure that we're not providing SYSCLK right now */
2131         clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2132         if (clk1 & WM8994_SYSCLK_SRC)
2133                 aif_reg = WM8994_AIF2_CLOCKING_1;
2134         else
2135                 aif_reg = WM8994_AIF1_CLOCKING_1;
2136         reg = snd_soc_read(codec, aif_reg);
2137
2138         if ((reg & WM8994_AIF1CLK_ENA) &&
2139             (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2140                 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2141                         id + 1);
2142                 return -EBUSY;
2143         }
2144
2145         /* We always need to disable the FLL while reconfiguring */
2146         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2147                             WM8994_FLL1_ENA, 0);
2148
2149         if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2150             freq_in == freq_out && freq_out) {
2151                 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2152                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2153                                     WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2154                 goto out;
2155         }
2156
2157         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2158                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2159         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2160                             WM8994_FLL1_OUTDIV_MASK |
2161                             WM8994_FLL1_FRATIO_MASK, reg);
2162
2163         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2164                             WM8994_FLL1_K_MASK, fll.k);
2165
2166         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2167                             WM8994_FLL1_N_MASK,
2168                                     fll.n << WM8994_FLL1_N_SHIFT);
2169
2170         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2171                             WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2172                             WM8994_FLL1_REFCLK_DIV_MASK |
2173                             WM8994_FLL1_REFCLK_SRC_MASK,
2174                             ((src == WM8994_FLL_SRC_INTERNAL)
2175                              << WM8994_FLL1_FRC_NCO_SHIFT) |
2176                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2177                             (src - 1));
2178
2179         /* Clear any pending completion from a previous failure */
2180         try_wait_for_completion(&wm8994->fll_locked[id]);
2181
2182         /* Enable (with fractional mode if required) */
2183         if (freq_out) {
2184                 /* Enable VMID if we need it */
2185                 if (!was_enabled) {
2186                         active_reference(codec);
2187
2188                         switch (control->type) {
2189                         case WM8994:
2190                                 vmid_reference(codec);
2191                                 break;
2192                         case WM8958:
2193                                 if (wm8994->revision < 1)
2194                                         vmid_reference(codec);
2195                                 break;
2196                         default:
2197                                 break;
2198                         }
2199                 }
2200
2201                 reg = WM8994_FLL1_ENA;
2202
2203                 if (fll.k)
2204                         reg |= WM8994_FLL1_FRAC;
2205                 if (src == WM8994_FLL_SRC_INTERNAL)
2206                         reg |= WM8994_FLL1_OSC_ENA;
2207
2208                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2209                                     WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2210                                     WM8994_FLL1_FRAC, reg);
2211
2212                 if (wm8994->fll_locked_irq) {
2213                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2214                                                               msecs_to_jiffies(10));
2215                         if (timeout == 0)
2216                                 dev_warn(codec->dev,
2217                                          "Timed out waiting for FLL lock\n");
2218                 } else {
2219                         msleep(5);
2220                 }
2221         } else {
2222                 if (was_enabled) {
2223                         switch (control->type) {
2224                         case WM8994:
2225                                 vmid_dereference(codec);
2226                                 break;
2227                         case WM8958:
2228                                 if (wm8994->revision < 1)
2229                                         vmid_dereference(codec);
2230                                 break;
2231                         default:
2232                                 break;
2233                         }
2234
2235                         active_dereference(codec);
2236                 }
2237         }
2238
2239 out:
2240         wm8994->fll[id].in = freq_in;
2241         wm8994->fll[id].out = freq_out;
2242         wm8994->fll[id].src = src;
2243
2244         configure_clock(codec);
2245
2246         return 0;
2247 }
2248
2249 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2250 {
2251         struct completion *completion = data;
2252
2253         complete(completion);
2254
2255         return IRQ_HANDLED;
2256 }
2257
2258 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2259
2260 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2261                           unsigned int freq_in, unsigned int freq_out)
2262 {
2263         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2264 }
2265
2266 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2267                 int clk_id, unsigned int freq, int dir)
2268 {
2269         struct snd_soc_codec *codec = dai->codec;
2270         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2271         int i;
2272
2273         switch (dai->id) {
2274         case 1:
2275         case 2:
2276                 break;
2277
2278         default:
2279                 /* AIF3 shares clocking with AIF1/2 */
2280                 return -EINVAL;
2281         }
2282
2283         switch (clk_id) {
2284         case WM8994_SYSCLK_MCLK1:
2285                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2286                 wm8994->mclk[0] = freq;
2287                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2288                         dai->id, freq);
2289                 break;
2290
2291         case WM8994_SYSCLK_MCLK2:
2292                 /* TODO: Set GPIO AF */
2293                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2294                 wm8994->mclk[1] = freq;
2295                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2296                         dai->id, freq);
2297                 break;
2298
2299         case WM8994_SYSCLK_FLL1:
2300                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2301                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2302                 break;
2303
2304         case WM8994_SYSCLK_FLL2:
2305                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2306                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2307                 break;
2308
2309         case WM8994_SYSCLK_OPCLK:
2310                 /* Special case - a division (times 10) is given and
2311                  * no effect on main clocking.
2312                  */
2313                 if (freq) {
2314                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2315                                 if (opclk_divs[i] == freq)
2316                                         break;
2317                         if (i == ARRAY_SIZE(opclk_divs))
2318                                 return -EINVAL;
2319                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2320                                             WM8994_OPCLK_DIV_MASK, i);
2321                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2322                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2323                 } else {
2324                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2325                                             WM8994_OPCLK_ENA, 0);
2326                 }
2327
2328         default:
2329                 return -EINVAL;
2330         }
2331
2332         configure_clock(codec);
2333
2334         return 0;
2335 }
2336
2337 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2338                                  enum snd_soc_bias_level level)
2339 {
2340         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2341         struct wm8994 *control = wm8994->wm8994;
2342
2343         wm_hubs_set_bias_level(codec, level);
2344
2345         switch (level) {
2346         case SND_SOC_BIAS_ON:
2347                 break;
2348
2349         case SND_SOC_BIAS_PREPARE:
2350                 /* MICBIAS into regulating mode */
2351                 switch (control->type) {
2352                 case WM8958:
2353                 case WM1811:
2354                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2355                                             WM8958_MICB1_MODE, 0);
2356                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2357                                             WM8958_MICB2_MODE, 0);
2358                         break;
2359                 default:
2360                         break;
2361                 }
2362
2363                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2364                         active_reference(codec);
2365                 break;
2366
2367         case SND_SOC_BIAS_STANDBY:
2368                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2369                         switch (control->type) {
2370                         case WM8958:
2371                                 if (wm8994->revision == 0) {
2372                                         /* Optimise performance for rev A */
2373                                         snd_soc_update_bits(codec,
2374                                                             WM8958_CHARGE_PUMP_2,
2375                                                             WM8958_CP_DISCH,
2376                                                             WM8958_CP_DISCH);
2377                                 }
2378                                 break;
2379
2380                         default:
2381                                 break;
2382                         }
2383
2384                         /* Discharge LINEOUT1 & 2 */
2385                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2386                                             WM8994_LINEOUT1_DISCH |
2387                                             WM8994_LINEOUT2_DISCH,
2388                                             WM8994_LINEOUT1_DISCH |
2389                                             WM8994_LINEOUT2_DISCH);
2390                 }
2391
2392                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2393                         active_dereference(codec);
2394
2395                 /* MICBIAS into bypass mode on newer devices */
2396                 switch (control->type) {
2397                 case WM8958:
2398                 case WM1811:
2399                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2400                                             WM8958_MICB1_MODE,
2401                                             WM8958_MICB1_MODE);
2402                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2403                                             WM8958_MICB2_MODE,
2404                                             WM8958_MICB2_MODE);
2405                         break;
2406                 default:
2407                         break;
2408                 }
2409                 break;
2410
2411         case SND_SOC_BIAS_OFF:
2412                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2413                         wm8994->cur_fw = NULL;
2414                 break;
2415         }
2416
2417         codec->dapm.bias_level = level;
2418
2419         return 0;
2420 }
2421
2422 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2423 {
2424         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2425
2426         switch (mode) {
2427         case WM8994_VMID_NORMAL:
2428                 if (wm8994->hubs.lineout1_se) {
2429                         snd_soc_dapm_disable_pin(&codec->dapm,
2430                                                  "LINEOUT1N Driver");
2431                         snd_soc_dapm_disable_pin(&codec->dapm,
2432                                                  "LINEOUT1P Driver");
2433                 }
2434                 if (wm8994->hubs.lineout2_se) {
2435                         snd_soc_dapm_disable_pin(&codec->dapm,
2436                                                  "LINEOUT2N Driver");
2437                         snd_soc_dapm_disable_pin(&codec->dapm,
2438                                                  "LINEOUT2P Driver");
2439                 }
2440
2441                 /* Do the sync with the old mode to allow it to clean up */
2442                 snd_soc_dapm_sync(&codec->dapm);
2443                 wm8994->vmid_mode = mode;
2444                 break;
2445
2446         case WM8994_VMID_FORCE:
2447                 if (wm8994->hubs.lineout1_se) {
2448                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2449                                                       "LINEOUT1N Driver");
2450                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2451                                                       "LINEOUT1P Driver");
2452                 }
2453                 if (wm8994->hubs.lineout2_se) {
2454                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2455                                                       "LINEOUT2N Driver");
2456                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2457                                                       "LINEOUT2P Driver");
2458                 }
2459
2460                 wm8994->vmid_mode = mode;
2461                 snd_soc_dapm_sync(&codec->dapm);
2462                 break;
2463
2464         default:
2465                 return -EINVAL;
2466         }
2467
2468         return 0;
2469 }
2470
2471 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2472 {
2473         struct snd_soc_codec *codec = dai->codec;
2474         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2475         struct wm8994 *control = wm8994->wm8994;
2476         int ms_reg;
2477         int aif1_reg;
2478         int ms = 0;
2479         int aif1 = 0;
2480
2481         switch (dai->id) {
2482         case 1:
2483                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2484                 aif1_reg = WM8994_AIF1_CONTROL_1;
2485                 break;
2486         case 2:
2487                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2488                 aif1_reg = WM8994_AIF2_CONTROL_1;
2489                 break;
2490         default:
2491                 return -EINVAL;
2492         }
2493
2494         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2495         case SND_SOC_DAIFMT_CBS_CFS:
2496                 break;
2497         case SND_SOC_DAIFMT_CBM_CFM:
2498                 ms = WM8994_AIF1_MSTR;
2499                 break;
2500         default:
2501                 return -EINVAL;
2502         }
2503
2504         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2505         case SND_SOC_DAIFMT_DSP_B:
2506                 aif1 |= WM8994_AIF1_LRCLK_INV;
2507         case SND_SOC_DAIFMT_DSP_A:
2508                 aif1 |= 0x18;
2509                 break;
2510         case SND_SOC_DAIFMT_I2S:
2511                 aif1 |= 0x10;
2512                 break;
2513         case SND_SOC_DAIFMT_RIGHT_J:
2514                 break;
2515         case SND_SOC_DAIFMT_LEFT_J:
2516                 aif1 |= 0x8;
2517                 break;
2518         default:
2519                 return -EINVAL;
2520         }
2521
2522         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2523         case SND_SOC_DAIFMT_DSP_A:
2524         case SND_SOC_DAIFMT_DSP_B:
2525                 /* frame inversion not valid for DSP modes */
2526                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2527                 case SND_SOC_DAIFMT_NB_NF:
2528                         break;
2529                 case SND_SOC_DAIFMT_IB_NF:
2530                         aif1 |= WM8994_AIF1_BCLK_INV;
2531                         break;
2532                 default:
2533                         return -EINVAL;
2534                 }
2535                 break;
2536
2537         case SND_SOC_DAIFMT_I2S:
2538         case SND_SOC_DAIFMT_RIGHT_J:
2539         case SND_SOC_DAIFMT_LEFT_J:
2540                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2541                 case SND_SOC_DAIFMT_NB_NF:
2542                         break;
2543                 case SND_SOC_DAIFMT_IB_IF:
2544                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2545                         break;
2546                 case SND_SOC_DAIFMT_IB_NF:
2547                         aif1 |= WM8994_AIF1_BCLK_INV;
2548                         break;
2549                 case SND_SOC_DAIFMT_NB_IF:
2550                         aif1 |= WM8994_AIF1_LRCLK_INV;
2551                         break;
2552                 default:
2553                         return -EINVAL;
2554                 }
2555                 break;
2556         default:
2557                 return -EINVAL;
2558         }
2559
2560         /* The AIF2 format configuration needs to be mirrored to AIF3
2561          * on WM8958 if it's in use so just do it all the time. */
2562         switch (control->type) {
2563         case WM1811:
2564         case WM8958:
2565                 if (dai->id == 2)
2566                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2567                                             WM8994_AIF1_LRCLK_INV |
2568                                             WM8958_AIF3_FMT_MASK, aif1);
2569                 break;
2570
2571         default:
2572                 break;
2573         }
2574
2575         snd_soc_update_bits(codec, aif1_reg,
2576                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2577                             WM8994_AIF1_FMT_MASK,
2578                             aif1);
2579         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2580                             ms);
2581
2582         return 0;
2583 }
2584
2585 static struct {
2586         int val, rate;
2587 } srs[] = {
2588         { 0,   8000 },
2589         { 1,  11025 },
2590         { 2,  12000 },
2591         { 3,  16000 },
2592         { 4,  22050 },
2593         { 5,  24000 },
2594         { 6,  32000 },
2595         { 7,  44100 },
2596         { 8,  48000 },
2597         { 9,  88200 },
2598         { 10, 96000 },
2599 };
2600
2601 static int fs_ratios[] = {
2602         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2603 };
2604
2605 static int bclk_divs[] = {
2606         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2607         640, 880, 960, 1280, 1760, 1920
2608 };
2609
2610 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2611                             struct snd_pcm_hw_params *params,
2612                             struct snd_soc_dai *dai)
2613 {
2614         struct snd_soc_codec *codec = dai->codec;
2615         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2616         int aif1_reg;
2617         int aif2_reg;
2618         int bclk_reg;
2619         int lrclk_reg;
2620         int rate_reg;
2621         int aif1 = 0;
2622         int aif2 = 0;
2623         int bclk = 0;
2624         int lrclk = 0;
2625         int rate_val = 0;
2626         int id = dai->id - 1;
2627
2628         int i, cur_val, best_val, bclk_rate, best;
2629
2630         switch (dai->id) {
2631         case 1:
2632                 aif1_reg = WM8994_AIF1_CONTROL_1;
2633                 aif2_reg = WM8994_AIF1_CONTROL_2;
2634                 bclk_reg = WM8994_AIF1_BCLK;
2635                 rate_reg = WM8994_AIF1_RATE;
2636                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2637                     wm8994->lrclk_shared[0]) {
2638                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2639                 } else {
2640                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2641                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2642                 }
2643                 break;
2644         case 2:
2645                 aif1_reg = WM8994_AIF2_CONTROL_1;
2646                 aif2_reg = WM8994_AIF2_CONTROL_2;
2647                 bclk_reg = WM8994_AIF2_BCLK;
2648                 rate_reg = WM8994_AIF2_RATE;
2649                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2650                     wm8994->lrclk_shared[1]) {
2651                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2652                 } else {
2653                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2654                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2655                 }
2656                 break;
2657         default:
2658                 return -EINVAL;
2659         }
2660
2661         bclk_rate = params_rate(params) * 4;
2662         switch (params_format(params)) {
2663         case SNDRV_PCM_FORMAT_S16_LE:
2664                 bclk_rate *= 16;
2665                 break;
2666         case SNDRV_PCM_FORMAT_S20_3LE:
2667                 bclk_rate *= 20;
2668                 aif1 |= 0x20;
2669                 break;
2670         case SNDRV_PCM_FORMAT_S24_LE:
2671                 bclk_rate *= 24;
2672                 aif1 |= 0x40;
2673                 break;
2674         case SNDRV_PCM_FORMAT_S32_LE:
2675                 bclk_rate *= 32;
2676                 aif1 |= 0x60;
2677                 break;
2678         default:
2679                 return -EINVAL;
2680         }
2681
2682         /* Try to find an appropriate sample rate; look for an exact match. */
2683         for (i = 0; i < ARRAY_SIZE(srs); i++)
2684                 if (srs[i].rate == params_rate(params))
2685                         break;
2686         if (i == ARRAY_SIZE(srs))
2687                 return -EINVAL;
2688         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2689
2690         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2691         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2692                 dai->id, wm8994->aifclk[id], bclk_rate);
2693
2694         if (params_channels(params) == 1 &&
2695             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2696                 aif2 |= WM8994_AIF1_MONO;
2697
2698         if (wm8994->aifclk[id] == 0) {
2699                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2700                 return -EINVAL;
2701         }
2702
2703         /* AIFCLK/fs ratio; look for a close match in either direction */
2704         best = 0;
2705         best_val = abs((fs_ratios[0] * params_rate(params))
2706                        - wm8994->aifclk[id]);
2707         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2708                 cur_val = abs((fs_ratios[i] * params_rate(params))
2709                               - wm8994->aifclk[id]);
2710                 if (cur_val >= best_val)
2711                         continue;
2712                 best = i;
2713                 best_val = cur_val;
2714         }
2715         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2716                 dai->id, fs_ratios[best]);
2717         rate_val |= best;
2718
2719         /* We may not get quite the right frequency if using
2720          * approximate clocks so look for the closest match that is
2721          * higher than the target (we need to ensure that there enough
2722          * BCLKs to clock out the samples).
2723          */
2724         best = 0;
2725         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2726                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2727                 if (cur_val < 0) /* BCLK table is sorted */
2728                         break;
2729                 best = i;
2730         }
2731         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2732         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2733                 bclk_divs[best], bclk_rate);
2734         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2735
2736         lrclk = bclk_rate / params_rate(params);
2737         if (!lrclk) {
2738                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2739                         bclk_rate);
2740                 return -EINVAL;
2741         }
2742         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2743                 lrclk, bclk_rate / lrclk);
2744
2745         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2746         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2747         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2748         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2749                             lrclk);
2750         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2751                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2752
2753         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2754                 switch (dai->id) {
2755                 case 1:
2756                         wm8994->dac_rates[0] = params_rate(params);
2757                         wm8994_set_retune_mobile(codec, 0);
2758                         wm8994_set_retune_mobile(codec, 1);
2759                         break;
2760                 case 2:
2761                         wm8994->dac_rates[1] = params_rate(params);
2762                         wm8994_set_retune_mobile(codec, 2);
2763                         break;
2764                 }
2765         }
2766
2767         return 0;
2768 }
2769
2770 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2771                                  struct snd_pcm_hw_params *params,
2772                                  struct snd_soc_dai *dai)
2773 {
2774         struct snd_soc_codec *codec = dai->codec;
2775         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2776         struct wm8994 *control = wm8994->wm8994;
2777         int aif1_reg;
2778         int aif1 = 0;
2779
2780         switch (dai->id) {
2781         case 3:
2782                 switch (control->type) {
2783                 case WM1811:
2784                 case WM8958:
2785                         aif1_reg = WM8958_AIF3_CONTROL_1;
2786                         break;
2787                 default:
2788                         return 0;
2789                 }
2790         default:
2791                 return 0;
2792         }
2793
2794         switch (params_format(params)) {
2795         case SNDRV_PCM_FORMAT_S16_LE:
2796                 break;
2797         case SNDRV_PCM_FORMAT_S20_3LE:
2798                 aif1 |= 0x20;
2799                 break;
2800         case SNDRV_PCM_FORMAT_S24_LE:
2801                 aif1 |= 0x40;
2802                 break;
2803         case SNDRV_PCM_FORMAT_S32_LE:
2804                 aif1 |= 0x60;
2805                 break;
2806         default:
2807                 return -EINVAL;
2808         }
2809
2810         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2811 }
2812
2813 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2814 {
2815         struct snd_soc_codec *codec = codec_dai->codec;
2816         int mute_reg;
2817         int reg;
2818
2819         switch (codec_dai->id) {
2820         case 1:
2821                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2822                 break;
2823         case 2:
2824                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2825                 break;
2826         default:
2827                 return -EINVAL;
2828         }
2829
2830         if (mute)
2831                 reg = WM8994_AIF1DAC1_MUTE;
2832         else
2833                 reg = 0;
2834
2835         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2836
2837         return 0;
2838 }
2839
2840 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2841 {
2842         struct snd_soc_codec *codec = codec_dai->codec;
2843         int reg, val, mask;
2844
2845         switch (codec_dai->id) {
2846         case 1:
2847                 reg = WM8994_AIF1_MASTER_SLAVE;
2848                 mask = WM8994_AIF1_TRI;
2849                 break;
2850         case 2:
2851                 reg = WM8994_AIF2_MASTER_SLAVE;
2852                 mask = WM8994_AIF2_TRI;
2853                 break;
2854         default:
2855                 return -EINVAL;
2856         }
2857
2858         if (tristate)
2859                 val = mask;
2860         else
2861                 val = 0;
2862
2863         return snd_soc_update_bits(codec, reg, mask, val);
2864 }
2865
2866 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2867 {
2868         struct snd_soc_codec *codec = dai->codec;
2869
2870         /* Disable the pulls on the AIF if we're using it to save power. */
2871         snd_soc_update_bits(codec, WM8994_GPIO_3,
2872                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2873         snd_soc_update_bits(codec, WM8994_GPIO_4,
2874                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2875         snd_soc_update_bits(codec, WM8994_GPIO_5,
2876                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2877
2878         return 0;
2879 }
2880
2881 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2882
2883 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2884                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2885
2886 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2887         .set_sysclk     = wm8994_set_dai_sysclk,
2888         .set_fmt        = wm8994_set_dai_fmt,
2889         .hw_params      = wm8994_hw_params,
2890         .digital_mute   = wm8994_aif_mute,
2891         .set_pll        = wm8994_set_fll,
2892         .set_tristate   = wm8994_set_tristate,
2893 };
2894
2895 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2896         .set_sysclk     = wm8994_set_dai_sysclk,
2897         .set_fmt        = wm8994_set_dai_fmt,
2898         .hw_params      = wm8994_hw_params,
2899         .digital_mute   = wm8994_aif_mute,
2900         .set_pll        = wm8994_set_fll,
2901         .set_tristate   = wm8994_set_tristate,
2902 };
2903
2904 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2905         .hw_params      = wm8994_aif3_hw_params,
2906 };
2907
2908 static struct snd_soc_dai_driver wm8994_dai[] = {
2909         {
2910                 .name = "wm8994-aif1",
2911                 .id = 1,
2912                 .playback = {
2913                         .stream_name = "AIF1 Playback",
2914                         .channels_min = 1,
2915                         .channels_max = 2,
2916                         .rates = WM8994_RATES,
2917                         .formats = WM8994_FORMATS,
2918                         .sig_bits = 24,
2919                 },
2920                 .capture = {
2921                         .stream_name = "AIF1 Capture",
2922                         .channels_min = 1,
2923                         .channels_max = 2,
2924                         .rates = WM8994_RATES,
2925                         .formats = WM8994_FORMATS,
2926                         .sig_bits = 24,
2927                  },
2928                 .ops = &wm8994_aif1_dai_ops,
2929         },
2930         {
2931                 .name = "wm8994-aif2",
2932                 .id = 2,
2933                 .playback = {
2934                         .stream_name = "AIF2 Playback",
2935                         .channels_min = 1,
2936                         .channels_max = 2,
2937                         .rates = WM8994_RATES,
2938                         .formats = WM8994_FORMATS,
2939                         .sig_bits = 24,
2940                 },
2941                 .capture = {
2942                         .stream_name = "AIF2 Capture",
2943                         .channels_min = 1,
2944                         .channels_max = 2,
2945                         .rates = WM8994_RATES,
2946                         .formats = WM8994_FORMATS,
2947                         .sig_bits = 24,
2948                 },
2949                 .probe = wm8994_aif2_probe,
2950                 .ops = &wm8994_aif2_dai_ops,
2951         },
2952         {
2953                 .name = "wm8994-aif3",
2954                 .id = 3,
2955                 .playback = {
2956                         .stream_name = "AIF3 Playback",
2957                         .channels_min = 1,
2958                         .channels_max = 2,
2959                         .rates = WM8994_RATES,
2960                         .formats = WM8994_FORMATS,
2961                         .sig_bits = 24,
2962                 },
2963                 .capture = {
2964                         .stream_name = "AIF3 Capture",
2965                         .channels_min = 1,
2966                         .channels_max = 2,
2967                         .rates = WM8994_RATES,
2968                         .formats = WM8994_FORMATS,
2969                         .sig_bits = 24,
2970                  },
2971                 .ops = &wm8994_aif3_dai_ops,
2972         }
2973 };
2974
2975 #ifdef CONFIG_PM
2976 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
2977 {
2978         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2979         int i, ret;
2980
2981         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2982                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2983                        sizeof(struct wm8994_fll_config));
2984                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2985                 if (ret < 0)
2986                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2987                                  i + 1, ret);
2988         }
2989
2990         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2991
2992         return 0;
2993 }
2994
2995 static int wm8994_codec_resume(struct snd_soc_codec *codec)
2996 {
2997         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2998         struct wm8994 *control = wm8994->wm8994;
2999         int i, ret;
3000         unsigned int val, mask;
3001
3002         if (wm8994->revision < 4) {
3003                 /* force a HW read */
3004                 ret = regmap_read(control->regmap,
3005                                   WM8994_POWER_MANAGEMENT_5, &val);
3006
3007                 /* modify the cache only */
3008                 codec->cache_only = 1;
3009                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3010                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3011                 val &= mask;
3012                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3013                                     mask, val);
3014                 codec->cache_only = 0;
3015         }
3016
3017         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3018                 if (!wm8994->fll_suspend[i].out)
3019                         continue;
3020
3021                 ret = _wm8994_set_fll(codec, i + 1,
3022                                      wm8994->fll_suspend[i].src,
3023                                      wm8994->fll_suspend[i].in,
3024                                      wm8994->fll_suspend[i].out);
3025                 if (ret < 0)
3026                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3027                                  i + 1, ret);
3028         }
3029
3030         return 0;
3031 }
3032 #else
3033 #define wm8994_codec_suspend NULL
3034 #define wm8994_codec_resume NULL
3035 #endif
3036
3037 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3038 {
3039         struct snd_soc_codec *codec = wm8994->hubs.codec;
3040         struct wm8994_pdata *pdata = wm8994->pdata;
3041         struct snd_kcontrol_new controls[] = {
3042                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3043                              wm8994->retune_mobile_enum,
3044                              wm8994_get_retune_mobile_enum,
3045                              wm8994_put_retune_mobile_enum),
3046                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3047                              wm8994->retune_mobile_enum,
3048                              wm8994_get_retune_mobile_enum,
3049                              wm8994_put_retune_mobile_enum),
3050                 SOC_ENUM_EXT("AIF2 EQ Mode",
3051                              wm8994->retune_mobile_enum,
3052                              wm8994_get_retune_mobile_enum,
3053                              wm8994_put_retune_mobile_enum),
3054         };
3055         int ret, i, j;
3056         const char **t;
3057
3058         /* We need an array of texts for the enum API but the number
3059          * of texts is likely to be less than the number of
3060          * configurations due to the sample rate dependency of the
3061          * configurations. */
3062         wm8994->num_retune_mobile_texts = 0;
3063         wm8994->retune_mobile_texts = NULL;
3064         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3065                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3066                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
3067                                    wm8994->retune_mobile_texts[j]) == 0)
3068                                 break;
3069                 }
3070
3071                 if (j != wm8994->num_retune_mobile_texts)
3072                         continue;
3073
3074                 /* Expand the array... */
3075                 t = krealloc(wm8994->retune_mobile_texts,
3076                              sizeof(char *) *
3077                              (wm8994->num_retune_mobile_texts + 1),
3078                              GFP_KERNEL);
3079                 if (t == NULL)
3080                         continue;
3081
3082                 /* ...store the new entry... */
3083                 t[wm8994->num_retune_mobile_texts] =
3084                         pdata->retune_mobile_cfgs[i].name;
3085
3086                 /* ...and remember the new version. */
3087                 wm8994->num_retune_mobile_texts++;
3088                 wm8994->retune_mobile_texts = t;
3089         }
3090
3091         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3092                 wm8994->num_retune_mobile_texts);
3093
3094         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3095         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3096
3097         ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3098                                    ARRAY_SIZE(controls));
3099         if (ret != 0)
3100                 dev_err(wm8994->hubs.codec->dev,
3101                         "Failed to add ReTune Mobile controls: %d\n", ret);
3102 }
3103
3104 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3105 {
3106         struct snd_soc_codec *codec = wm8994->hubs.codec;
3107         struct wm8994_pdata *pdata = wm8994->pdata;
3108         int ret, i;
3109
3110         if (!pdata)
3111                 return;
3112
3113         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3114                                       pdata->lineout2_diff,
3115                                       pdata->lineout1fb,
3116                                       pdata->lineout2fb,
3117                                       pdata->jd_scthr,
3118                                       pdata->jd_thr,
3119                                       pdata->micbias1_lvl,
3120                                       pdata->micbias2_lvl);
3121
3122         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3123
3124         if (pdata->num_drc_cfgs) {
3125                 struct snd_kcontrol_new controls[] = {
3126                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3127                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3128                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3129                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3130                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3131                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3132                 };
3133
3134                 /* We need an array of texts for the enum API */
3135                 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3136                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3137                 if (!wm8994->drc_texts) {
3138                         dev_err(wm8994->hubs.codec->dev,
3139                                 "Failed to allocate %d DRC config texts\n",
3140                                 pdata->num_drc_cfgs);
3141                         return;
3142                 }
3143
3144                 for (i = 0; i < pdata->num_drc_cfgs; i++)
3145                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3146
3147                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3148                 wm8994->drc_enum.texts = wm8994->drc_texts;
3149
3150                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3151                                            ARRAY_SIZE(controls));
3152                 if (ret != 0)
3153                         dev_err(wm8994->hubs.codec->dev,
3154                                 "Failed to add DRC mode controls: %d\n", ret);
3155
3156                 for (i = 0; i < WM8994_NUM_DRC; i++)
3157                         wm8994_set_drc(codec, i);
3158         }
3159
3160         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3161                 pdata->num_retune_mobile_cfgs);
3162
3163         if (pdata->num_retune_mobile_cfgs)
3164                 wm8994_handle_retune_mobile_pdata(wm8994);
3165         else
3166                 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3167                                      ARRAY_SIZE(wm8994_eq_controls));
3168
3169         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3170                 if (pdata->micbias[i]) {
3171                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
3172                                 pdata->micbias[i] & 0xffff);
3173                 }
3174         }
3175 }
3176
3177 /**
3178  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3179  *
3180  * @codec:   WM8994 codec
3181  * @jack:    jack to report detection events on
3182  * @micbias: microphone bias to detect on
3183  *
3184  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
3185  * being used to bring out signals to the processor then only platform
3186  * data configuration is needed for WM8994 and processor GPIOs should
3187  * be configured using snd_soc_jack_add_gpios() instead.
3188  *
3189  * Configuration of detection levels is available via the micbias1_lvl
3190  * and micbias2_lvl platform data members.
3191  */
3192 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3193                       int micbias)
3194 {
3195         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3196         struct wm8994_micdet *micdet;
3197         struct wm8994 *control = wm8994->wm8994;
3198         int reg, ret;
3199
3200         if (control->type != WM8994) {
3201                 dev_warn(codec->dev, "Not a WM8994\n");
3202                 return -EINVAL;
3203         }
3204
3205         switch (micbias) {
3206         case 1:
3207                 micdet = &wm8994->micdet[0];
3208                 if (jack)
3209                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3210                                                             "MICBIAS1");
3211                 else
3212                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3213                                                        "MICBIAS1");
3214                 break;
3215         case 2:
3216                 micdet = &wm8994->micdet[1];
3217                 if (jack)
3218                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3219                                                             "MICBIAS1");
3220                 else
3221                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3222                                                        "MICBIAS1");
3223                 break;
3224         default:
3225                 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3226                 return -EINVAL;
3227         }
3228
3229         if (ret != 0)
3230                 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3231                          micbias, ret);
3232
3233         dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3234                 micbias, jack);
3235
3236         /* Store the configuration */
3237         micdet->jack = jack;
3238         micdet->detecting = true;
3239
3240         /* If either of the jacks is set up then enable detection */
3241         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3242                 reg = WM8994_MICD_ENA;
3243         else
3244                 reg = 0;
3245
3246         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3247
3248         snd_soc_dapm_sync(&codec->dapm);
3249
3250         return 0;
3251 }
3252 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3253
3254 static void wm8994_mic_work(struct work_struct *work)
3255 {
3256         struct wm8994_priv *priv = container_of(work,
3257                                                 struct wm8994_priv,
3258                                                 mic_work.work);
3259         struct regmap *regmap = priv->wm8994->regmap;
3260         struct device *dev = priv->wm8994->dev;
3261         unsigned int reg;
3262         int ret;
3263         int report;
3264
3265         pm_runtime_get_sync(dev);
3266
3267         ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3268         if (ret < 0) {
3269                 dev_err(dev, "Failed to read microphone status: %d\n",
3270                         ret);
3271                 pm_runtime_put(dev);
3272                 return;
3273         }
3274
3275         dev_dbg(dev, "Microphone status: %x\n", reg);
3276
3277         report = 0;
3278         if (reg & WM8994_MIC1_DET_STS) {
3279                 if (priv->micdet[0].detecting)
3280                         report = SND_JACK_HEADSET;
3281         }
3282         if (reg & WM8994_MIC1_SHRT_STS) {
3283                 if (priv->micdet[0].detecting)
3284                         report = SND_JACK_HEADPHONE;
3285                 else
3286                         report |= SND_JACK_BTN_0;
3287         }
3288         if (report)
3289                 priv->micdet[0].detecting = false;
3290         else
3291                 priv->micdet[0].detecting = true;
3292
3293         snd_soc_jack_report(priv->micdet[0].jack, report,
3294                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3295
3296         report = 0;
3297         if (reg & WM8994_MIC2_DET_STS) {
3298                 if (priv->micdet[1].detecting)
3299                         report = SND_JACK_HEADSET;
3300         }
3301         if (reg & WM8994_MIC2_SHRT_STS) {
3302                 if (priv->micdet[1].detecting)
3303                         report = SND_JACK_HEADPHONE;
3304                 else
3305                         report |= SND_JACK_BTN_0;
3306         }
3307         if (report)
3308                 priv->micdet[1].detecting = false;
3309         else
3310                 priv->micdet[1].detecting = true;
3311
3312         snd_soc_jack_report(priv->micdet[1].jack, report,
3313                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3314
3315         pm_runtime_put(dev);
3316 }
3317
3318 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3319 {
3320         struct wm8994_priv *priv = data;
3321         struct snd_soc_codec *codec = priv->hubs.codec;
3322
3323 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3324         trace_snd_soc_jack_irq(dev_name(codec->dev));
3325 #endif
3326
3327         pm_wakeup_event(codec->dev, 300);
3328
3329         schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
3330
3331         return IRQ_HANDLED;
3332 }
3333
3334 /* Default microphone detection handler for WM8958 - the user can
3335  * override this if they wish.
3336  */
3337 static void wm8958_default_micdet(u16 status, void *data)
3338 {
3339         struct snd_soc_codec *codec = data;
3340         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3341         int report;
3342
3343         dev_dbg(codec->dev, "MICDET %x\n", status);
3344
3345         /* Either nothing present or just starting detection */
3346         if (!(status & WM8958_MICD_STS)) {
3347                 if (!wm8994->jackdet) {
3348                         /* If nothing present then clear our statuses */
3349                         dev_dbg(codec->dev, "Detected open circuit\n");
3350                         wm8994->jack_mic = false;
3351                         wm8994->mic_detecting = true;
3352
3353                         wm8958_micd_set_rate(codec);
3354
3355                         snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3356                                             wm8994->btn_mask |
3357                                              SND_JACK_HEADSET);
3358                 }
3359                 return;
3360         }
3361
3362         /* If the measurement is showing a high impedence we've got a
3363          * microphone.
3364          */
3365         if (wm8994->mic_detecting && (status & 0x600)) {
3366                 dev_dbg(codec->dev, "Detected microphone\n");
3367
3368                 wm8994->mic_detecting = false;
3369                 wm8994->jack_mic = true;
3370
3371                 wm8958_micd_set_rate(codec);
3372
3373                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3374                                     SND_JACK_HEADSET);
3375         }
3376
3377
3378         if (wm8994->mic_detecting && status & 0xfc) {
3379                 dev_dbg(codec->dev, "Detected headphone\n");
3380                 wm8994->mic_detecting = false;
3381
3382                 wm8958_micd_set_rate(codec);
3383
3384                 /* If we have jackdet that will detect removal */
3385                 if (wm8994->jackdet) {
3386                         mutex_lock(&wm8994->accdet_lock);
3387
3388                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3389                                             WM8958_MICD_ENA, 0);
3390
3391                         wm1811_jackdet_set_mode(codec,
3392                                                 WM1811_JACKDET_MODE_JACK);
3393
3394                         mutex_unlock(&wm8994->accdet_lock);
3395
3396                         if (wm8994->pdata->jd_ext_cap)
3397                                 snd_soc_dapm_disable_pin(&codec->dapm,
3398                                                          "MICBIAS2");
3399                 }
3400
3401                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3402                                     SND_JACK_HEADSET);
3403         }
3404
3405         /* Report short circuit as a button */
3406         if (wm8994->jack_mic) {
3407                 report = 0;
3408                 if (status & 0x4)
3409                         report |= SND_JACK_BTN_0;
3410
3411                 if (status & 0x8)
3412                         report |= SND_JACK_BTN_1;
3413
3414                 if (status & 0x10)
3415                         report |= SND_JACK_BTN_2;
3416
3417                 if (status & 0x20)
3418                         report |= SND_JACK_BTN_3;
3419
3420                 if (status & 0x40)
3421                         report |= SND_JACK_BTN_4;
3422
3423                 if (status & 0x80)
3424                         report |= SND_JACK_BTN_5;
3425
3426                 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3427                                     wm8994->btn_mask);
3428         }
3429 }
3430
3431 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3432 {
3433         struct wm8994_priv *wm8994 = data;
3434         struct snd_soc_codec *codec = wm8994->hubs.codec;
3435         int reg;
3436         bool present;
3437
3438         pm_runtime_get_sync(codec->dev);
3439
3440         mutex_lock(&wm8994->accdet_lock);
3441
3442         reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3443         if (reg < 0) {
3444                 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3445                 mutex_unlock(&wm8994->accdet_lock);
3446                 pm_runtime_put(codec->dev);
3447                 return IRQ_NONE;
3448         }
3449
3450         dev_dbg(codec->dev, "JACKDET %x\n", reg);
3451
3452         present = reg & WM1811_JACKDET_LVL;
3453
3454         if (present) {
3455                 dev_dbg(codec->dev, "Jack detected\n");
3456
3457                 wm8958_micd_set_rate(codec);
3458
3459                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3460                                     WM8958_MICB2_DISCH, 0);
3461
3462                 /* Disable debounce while inserted */
3463                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3464                                     WM1811_JACKDET_DB, 0);
3465
3466                 /*
3467                  * Start off measument of microphone impedence to find
3468                  * out what's actually there.
3469                  */
3470                 wm8994->mic_detecting = true;
3471                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3472
3473                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3474                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3475         } else {
3476                 dev_dbg(codec->dev, "Jack not detected\n");
3477
3478                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3479                                     WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3480
3481                 /* Enable debounce while removed */
3482                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3483                                     WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3484
3485                 wm8994->mic_detecting = false;
3486                 wm8994->jack_mic = false;
3487                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3488                                     WM8958_MICD_ENA, 0);
3489                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3490         }
3491
3492         mutex_unlock(&wm8994->accdet_lock);
3493
3494         /* If required for an external cap force MICBIAS on */
3495         if (wm8994->pdata->jd_ext_cap) {
3496                 if (present)
3497                         snd_soc_dapm_force_enable_pin(&codec->dapm,
3498                                                       "MICBIAS2");
3499                 else
3500                         snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3501         }
3502
3503         if (present)
3504                 snd_soc_jack_report(wm8994->micdet[0].jack,
3505                                     SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3506         else
3507                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3508                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3509                                     wm8994->btn_mask);
3510
3511         pm_runtime_put(codec->dev);
3512         return IRQ_HANDLED;
3513 }
3514
3515 /**
3516  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3517  *
3518  * @codec:   WM8958 codec
3519  * @jack:    jack to report detection events on
3520  *
3521  * Enable microphone detection functionality for the WM8958.  By
3522  * default simple detection which supports the detection of up to 6
3523  * buttons plus video and microphone functionality is supported.
3524  *
3525  * The WM8958 has an advanced jack detection facility which is able to
3526  * support complex accessory detection, especially when used in
3527  * conjunction with external circuitry.  In order to provide maximum
3528  * flexiblity a callback is provided which allows a completely custom
3529  * detection algorithm.
3530  */
3531 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3532                       wm8958_micdet_cb cb, void *cb_data)
3533 {
3534         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3535         struct wm8994 *control = wm8994->wm8994;
3536         u16 micd_lvl_sel;
3537
3538         switch (control->type) {
3539         case WM1811:
3540         case WM8958:
3541                 break;
3542         default:
3543                 return -EINVAL;
3544         }
3545
3546         if (jack) {
3547                 if (!cb) {
3548                         dev_dbg(codec->dev, "Using default micdet callback\n");
3549                         cb = wm8958_default_micdet;
3550                         cb_data = codec;
3551                 }
3552
3553                 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3554                 snd_soc_dapm_sync(&codec->dapm);
3555
3556                 wm8994->micdet[0].jack = jack;
3557                 wm8994->jack_cb = cb;
3558                 wm8994->jack_cb_data = cb_data;
3559
3560                 wm8994->mic_detecting = true;
3561                 wm8994->jack_mic = false;
3562
3563                 wm8958_micd_set_rate(codec);
3564
3565                 /* Detect microphones and short circuits by default */
3566                 if (wm8994->pdata->micd_lvl_sel)
3567                         micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3568                 else
3569                         micd_lvl_sel = 0x41;
3570
3571                 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3572                         SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3573                         SND_JACK_BTN_4 | SND_JACK_BTN_5;
3574
3575                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3576                                     WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3577
3578                 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3579
3580                 /*
3581                  * If we can use jack detection start off with that,
3582                  * otherwise jump straight to microphone detection.
3583                  */
3584                 if (wm8994->jackdet) {
3585                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
3586                                             WM8958_MICB2_DISCH,
3587                                             WM8958_MICB2_DISCH);
3588                         snd_soc_update_bits(codec, WM8994_LDO_1,
3589                                             WM8994_LDO1_DISCH, 0);
3590                         wm1811_jackdet_set_mode(codec,
3591                                                 WM1811_JACKDET_MODE_JACK);
3592                 } else {
3593                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3594                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
3595                 }
3596
3597         } else {
3598                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3599                                     WM8958_MICD_ENA, 0);
3600                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3601                 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3602                 snd_soc_dapm_sync(&codec->dapm);
3603         }
3604
3605         return 0;
3606 }
3607 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3608
3609 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3610 {
3611         struct wm8994_priv *wm8994 = data;
3612         struct snd_soc_codec *codec = wm8994->hubs.codec;
3613         int reg, count;
3614
3615         /*
3616          * Jack detection may have detected a removal simulataneously
3617          * with an update of the MICDET status; if so it will have
3618          * stopped detection and we can ignore this interrupt.
3619          */
3620         if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3621                 return IRQ_HANDLED;
3622
3623         pm_runtime_get_sync(codec->dev);
3624
3625         /* We may occasionally read a detection without an impedence
3626          * range being provided - if that happens loop again.
3627          */
3628         count = 10;
3629         do {
3630                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3631                 if (reg < 0) {
3632                         dev_err(codec->dev,
3633                                 "Failed to read mic detect status: %d\n",
3634                                 reg);
3635                         pm_runtime_put(codec->dev);
3636                         return IRQ_NONE;
3637                 }
3638
3639                 if (!(reg & WM8958_MICD_VALID)) {
3640                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3641                         goto out;
3642                 }
3643
3644                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3645                         break;
3646
3647                 msleep(1);
3648         } while (count--);
3649
3650         if (count == 0)
3651                 dev_warn(codec->dev, "No impedence range reported for jack\n");
3652
3653 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3654         trace_snd_soc_jack_irq(dev_name(codec->dev));
3655 #endif
3656
3657         if (wm8994->jack_cb)
3658                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3659         else
3660                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3661
3662 out:
3663         pm_runtime_put(codec->dev);
3664         return IRQ_HANDLED;
3665 }
3666
3667 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3668 {
3669         struct snd_soc_codec *codec = data;
3670
3671         dev_err(codec->dev, "FIFO error\n");
3672
3673         return IRQ_HANDLED;
3674 }
3675
3676 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3677 {
3678         struct snd_soc_codec *codec = data;
3679
3680         dev_err(codec->dev, "Thermal warning\n");
3681
3682         return IRQ_HANDLED;
3683 }
3684
3685 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3686 {
3687         struct snd_soc_codec *codec = data;
3688
3689         dev_crit(codec->dev, "Thermal shutdown\n");
3690
3691         return IRQ_HANDLED;
3692 }
3693
3694 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3695 {
3696         struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3697         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3698         struct snd_soc_dapm_context *dapm = &codec->dapm;
3699         unsigned int reg;
3700         int ret, i;
3701
3702         wm8994->hubs.codec = codec;
3703         codec->control_data = control->regmap;
3704
3705         snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3706
3707         mutex_init(&wm8994->accdet_lock);
3708         INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3709
3710         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3711                 init_completion(&wm8994->fll_locked[i]);
3712
3713         if (wm8994->pdata && wm8994->pdata->micdet_irq)
3714                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3715
3716         pm_runtime_enable(codec->dev);
3717         pm_runtime_idle(codec->dev);
3718
3719         /* By default use idle_bias_off, will override for WM8994 */
3720         codec->dapm.idle_bias_off = 1;
3721
3722         /* Set revision-specific configuration */
3723         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3724         switch (control->type) {
3725         case WM8994:
3726                 /* Single ended line outputs should have VMID on. */
3727                 if (!wm8994->pdata->lineout1_diff ||
3728                     !wm8994->pdata->lineout2_diff)
3729                         codec->dapm.idle_bias_off = 0;
3730
3731                 switch (wm8994->revision) {
3732                 case 2:
3733                 case 3:
3734                         wm8994->hubs.dcs_codes_l = -5;
3735                         wm8994->hubs.dcs_codes_r = -5;
3736                         wm8994->hubs.hp_startup_mode = 1;
3737                         wm8994->hubs.dcs_readback_mode = 1;
3738                         wm8994->hubs.series_startup = 1;
3739                         break;
3740                 default:
3741                         wm8994->hubs.dcs_readback_mode = 2;
3742                         break;
3743                 }
3744                 break;
3745
3746         case WM8958:
3747                 wm8994->hubs.dcs_readback_mode = 1;
3748                 wm8994->hubs.hp_startup_mode = 1;
3749
3750                 switch (wm8994->revision) {
3751                 case 0:
3752                         break;
3753                 default:
3754                         wm8994->fll_byp = true;
3755                         break;
3756                 }
3757                 break;
3758
3759         case WM1811:
3760                 wm8994->hubs.dcs_readback_mode = 2;
3761                 wm8994->hubs.no_series_update = 1;
3762                 wm8994->hubs.hp_startup_mode = 1;
3763                 wm8994->hubs.no_cache_dac_hp_direct = true;
3764                 wm8994->fll_byp = true;
3765
3766                 switch (wm8994->revision) {
3767                 case 0:
3768                 case 1:
3769                 case 2:
3770                 case 3:
3771                         wm8994->hubs.dcs_codes_l = -9;
3772                         wm8994->hubs.dcs_codes_r = -7;
3773                         break;
3774                 default:
3775                         break;
3776                 }
3777
3778                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3779                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3780                 break;
3781
3782         default:
3783                 break;
3784         }
3785
3786         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3787                            wm8994_fifo_error, "FIFO error", codec);
3788         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3789                            wm8994_temp_warn, "Thermal warning", codec);
3790         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3791                            wm8994_temp_shut, "Thermal shutdown", codec);
3792
3793         ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3794                                  wm_hubs_dcs_done, "DC servo done",
3795                                  &wm8994->hubs);
3796         if (ret == 0)
3797                 wm8994->hubs.dcs_done_irq = true;
3798
3799         switch (control->type) {
3800         case WM8994:
3801                 if (wm8994->micdet_irq) {
3802                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3803                                                    wm8994_mic_irq,
3804                                                    IRQF_TRIGGER_RISING,
3805                                                    "Mic1 detect",
3806                                                    wm8994);
3807                         if (ret != 0)
3808                                 dev_warn(codec->dev,
3809                                          "Failed to request Mic1 detect IRQ: %d\n",
3810                                          ret);
3811                 }
3812
3813                 ret = wm8994_request_irq(wm8994->wm8994,
3814                                          WM8994_IRQ_MIC1_SHRT,
3815                                          wm8994_mic_irq, "Mic 1 short",
3816                                          wm8994);
3817                 if (ret != 0)
3818                         dev_warn(codec->dev,
3819                                  "Failed to request Mic1 short IRQ: %d\n",
3820                                  ret);
3821
3822                 ret = wm8994_request_irq(wm8994->wm8994,
3823                                          WM8994_IRQ_MIC2_DET,
3824                                          wm8994_mic_irq, "Mic 2 detect",
3825                                          wm8994);
3826                 if (ret != 0)
3827                         dev_warn(codec->dev,
3828                                  "Failed to request Mic2 detect IRQ: %d\n",
3829                                  ret);
3830
3831                 ret = wm8994_request_irq(wm8994->wm8994,
3832                                          WM8994_IRQ_MIC2_SHRT,
3833                                          wm8994_mic_irq, "Mic 2 short",
3834                                          wm8994);
3835                 if (ret != 0)
3836                         dev_warn(codec->dev,
3837                                  "Failed to request Mic2 short IRQ: %d\n",
3838                                  ret);
3839                 break;
3840
3841         case WM8958:
3842         case WM1811:
3843                 if (wm8994->micdet_irq) {
3844                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3845                                                    wm8958_mic_irq,
3846                                                    IRQF_TRIGGER_RISING,
3847                                                    "Mic detect",
3848                                                    wm8994);
3849                         if (ret != 0)
3850                                 dev_warn(codec->dev,
3851                                          "Failed to request Mic detect IRQ: %d\n",
3852                                          ret);
3853                 } else {
3854                         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3855                                            wm8958_mic_irq, "Mic detect",
3856                                            wm8994);
3857                 }
3858         }
3859
3860         switch (control->type) {
3861         case WM1811:
3862                 if (wm8994->revision > 1) {
3863                         ret = wm8994_request_irq(wm8994->wm8994,
3864                                                  WM8994_IRQ_GPIO(6),
3865                                                  wm1811_jackdet_irq, "JACKDET",
3866                                                  wm8994);
3867                         if (ret == 0)
3868                                 wm8994->jackdet = true;
3869                 }
3870                 break;
3871         default:
3872                 break;
3873         }
3874
3875         wm8994->fll_locked_irq = true;
3876         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3877                 ret = wm8994_request_irq(wm8994->wm8994,
3878                                          WM8994_IRQ_FLL1_LOCK + i,
3879                                          wm8994_fll_locked_irq, "FLL lock",
3880                                          &wm8994->fll_locked[i]);
3881                 if (ret != 0)
3882                         wm8994->fll_locked_irq = false;
3883         }
3884
3885         /* Make sure we can read from the GPIOs if they're inputs */
3886         pm_runtime_get_sync(codec->dev);
3887
3888         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3889          * configured on init - if a system wants to do this dynamically
3890          * at runtime we can deal with that then.
3891          */
3892         ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3893         if (ret < 0) {
3894                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3895                 goto err_irq;
3896         }
3897         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3898                 wm8994->lrclk_shared[0] = 1;
3899                 wm8994_dai[0].symmetric_rates = 1;
3900         } else {
3901                 wm8994->lrclk_shared[0] = 0;
3902         }
3903
3904         ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3905         if (ret < 0) {
3906                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3907                 goto err_irq;
3908         }
3909         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3910                 wm8994->lrclk_shared[1] = 1;
3911                 wm8994_dai[1].symmetric_rates = 1;
3912         } else {
3913                 wm8994->lrclk_shared[1] = 0;
3914         }
3915
3916         pm_runtime_put(codec->dev);
3917
3918         /* Latch volume update bits */
3919         for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
3920                 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
3921                                     wm8994_vu_bits[i].mask,
3922                                     wm8994_vu_bits[i].mask);
3923
3924         /* Set the low bit of the 3D stereo depth so TLV matches */
3925         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3926                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3927                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3928         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3929                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3930                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3931         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3932                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3933                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3934
3935         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3936          * use this; it only affects behaviour on idle TDM clock
3937          * cycles. */
3938         switch (control->type) {
3939         case WM8994:
3940         case WM8958:
3941                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3942                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3943                 break;
3944         default:
3945                 break;
3946         }
3947
3948         /* Put MICBIAS into bypass mode by default on newer devices */
3949         switch (control->type) {
3950         case WM8958:
3951         case WM1811:
3952                 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3953                                     WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3954                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3955                                     WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3956                 break;
3957         default:
3958                 break;
3959         }
3960
3961         wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
3962         wm_hubs_update_class_w(codec);
3963
3964         wm8994_handle_pdata(wm8994);
3965
3966         wm_hubs_add_analogue_controls(codec);
3967         snd_soc_add_codec_controls(codec, wm8994_snd_controls,
3968                              ARRAY_SIZE(wm8994_snd_controls));
3969         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3970                                   ARRAY_SIZE(wm8994_dapm_widgets));
3971
3972         switch (control->type) {
3973         case WM8994:
3974                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3975                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3976                 if (wm8994->revision < 4) {
3977                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3978                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3979                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3980                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3981                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3982                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3983                 } else {
3984                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3985                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3986                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3987                                                   ARRAY_SIZE(wm8994_adc_widgets));
3988                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3989                                                   ARRAY_SIZE(wm8994_dac_widgets));
3990                 }
3991                 break;
3992         case WM8958:
3993                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
3994                                      ARRAY_SIZE(wm8958_snd_controls));
3995                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3996                                           ARRAY_SIZE(wm8958_dapm_widgets));
3997                 if (wm8994->revision < 1) {
3998                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3999                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4000                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4001                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4002                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4003                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4004                 } else {
4005                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4006                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4007                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4008                                                   ARRAY_SIZE(wm8994_adc_widgets));
4009                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4010                                                   ARRAY_SIZE(wm8994_dac_widgets));
4011                 }
4012                 break;
4013
4014         case WM1811:
4015                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4016                                      ARRAY_SIZE(wm8958_snd_controls));
4017                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4018                                           ARRAY_SIZE(wm8958_dapm_widgets));
4019                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4020                                           ARRAY_SIZE(wm8994_lateclk_widgets));
4021                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4022                                           ARRAY_SIZE(wm8994_adc_widgets));
4023                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4024                                           ARRAY_SIZE(wm8994_dac_widgets));
4025                 break;
4026         }
4027
4028         wm_hubs_add_analogue_routes(codec, 0, 0);
4029         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4030
4031         switch (control->type) {
4032         case WM8994:
4033                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4034                                         ARRAY_SIZE(wm8994_intercon));
4035
4036                 if (wm8994->revision < 4) {
4037                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4038                                                 ARRAY_SIZE(wm8994_revd_intercon));
4039                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4040                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4041                 } else {
4042                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4043                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4044                 }
4045                 break;
4046         case WM8958:
4047                 if (wm8994->revision < 1) {
4048                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4049                                                 ARRAY_SIZE(wm8994_revd_intercon));
4050                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4051                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4052                 } else {
4053                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4054                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4055                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4056                                                 ARRAY_SIZE(wm8958_intercon));
4057                 }
4058
4059                 wm8958_dsp2_init(codec);
4060                 break;
4061         case WM1811:
4062                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4063                                         ARRAY_SIZE(wm8994_lateclk_intercon));
4064                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4065                                         ARRAY_SIZE(wm8958_intercon));
4066                 break;
4067         }
4068
4069         return 0;
4070
4071 err_irq:
4072         if (wm8994->jackdet)
4073                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4074         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4075         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4076         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4077         if (wm8994->micdet_irq)
4078                 free_irq(wm8994->micdet_irq, wm8994);
4079         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4080                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4081                                 &wm8994->fll_locked[i]);
4082         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4083                         &wm8994->hubs);
4084         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4085         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4086         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4087
4088         return ret;
4089 }
4090
4091 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4092 {
4093         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4094         struct wm8994 *control = wm8994->wm8994;
4095         int i;
4096
4097         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4098
4099         pm_runtime_disable(codec->dev);
4100
4101         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4102                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4103                                 &wm8994->fll_locked[i]);
4104
4105         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4106                         &wm8994->hubs);
4107         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4108         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4109         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4110
4111         if (wm8994->jackdet)
4112                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4113
4114         switch (control->type) {
4115         case WM8994:
4116                 if (wm8994->micdet_irq)
4117                         free_irq(wm8994->micdet_irq, wm8994);
4118                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4119                                 wm8994);
4120                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4121                                 wm8994);
4122                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4123                                 wm8994);
4124                 break;
4125
4126         case WM1811:
4127         case WM8958:
4128                 if (wm8994->micdet_irq)
4129                         free_irq(wm8994->micdet_irq, wm8994);
4130                 break;
4131         }
4132         release_firmware(wm8994->mbc);
4133         release_firmware(wm8994->mbc_vss);
4134         release_firmware(wm8994->enh_eq);
4135         kfree(wm8994->retune_mobile_texts);
4136         return 0;
4137 }
4138
4139 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4140         .probe =        wm8994_codec_probe,
4141         .remove =       wm8994_codec_remove,
4142         .suspend =      wm8994_codec_suspend,
4143         .resume =       wm8994_codec_resume,
4144         .set_bias_level = wm8994_set_bias_level,
4145 };
4146
4147 static int __devinit wm8994_probe(struct platform_device *pdev)
4148 {
4149         struct wm8994_priv *wm8994;
4150
4151         wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4152                               GFP_KERNEL);
4153         if (wm8994 == NULL)
4154                 return -ENOMEM;
4155         platform_set_drvdata(pdev, wm8994);
4156
4157         wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4158         wm8994->pdata = dev_get_platdata(pdev->dev.parent);
4159
4160         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4161                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
4162 }
4163
4164 static int __devexit wm8994_remove(struct platform_device *pdev)
4165 {
4166         snd_soc_unregister_codec(&pdev->dev);
4167         return 0;
4168 }
4169
4170 #ifdef CONFIG_PM_SLEEP
4171 static int wm8994_suspend(struct device *dev)
4172 {
4173         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4174
4175         /* Drop down to power saving mode when system is suspended */
4176         if (wm8994->jackdet && !wm8994->active_refcount)
4177                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4178                                    WM1811_JACKDET_MODE_MASK,
4179                                    wm8994->jackdet_mode);
4180
4181         return 0;
4182 }
4183
4184 static int wm8994_resume(struct device *dev)
4185 {
4186         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4187
4188         if (wm8994->jackdet && wm8994->jack_cb)
4189                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4190                                    WM1811_JACKDET_MODE_MASK,
4191                                    WM1811_JACKDET_MODE_AUDIO);
4192
4193         return 0;
4194 }
4195 #endif
4196
4197 static const struct dev_pm_ops wm8994_pm_ops = {
4198         SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4199 };
4200
4201 static struct platform_driver wm8994_codec_driver = {
4202         .driver = {
4203                 .name = "wm8994-codec",
4204                 .owner = THIS_MODULE,
4205                 .pm = &wm8994_pm_ops,
4206         },
4207         .probe = wm8994_probe,
4208         .remove = __devexit_p(wm8994_remove),
4209 };
4210
4211 module_platform_driver(wm8994_codec_driver);
4212
4213 MODULE_DESCRIPTION("ASoC WM8994 driver");
4214 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4215 MODULE_LICENSE("GPL");
4216 MODULE_ALIAS("platform:wm8994-codec");