Pileus Git - ~andy/linux/blob - sound/soc/codecs/wm8985.c

   1 /*
   2  * wm8985.c  --  WM8985 ALSA SoC Audio driver
   3  *
   4  * Copyright 2010 Wolfson Microelectronics plc
   5  *
   6  * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * TODO:
  13  *  o Add OUT3/OUT4 mixer controls.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/init.h>
  19 #include <linux/delay.h>
  20 #include <linux/pm.h>
  21 #include <linux/i2c.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/spi/spi.h>
  24 #include <linux/slab.h>
  25 #include <sound/core.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31
  32 #include "wm8985.h"
  33
  34 #define WM8985_NUM_SUPPLIES 4
  35 static const char *wm8985_supply_names[WM8985_NUM_SUPPLIES] = {
  36         "DCVDD",
  37         "DBVDD",
  38         "AVDD1",
  39         "AVDD2"
  40 };
  41
  42 static const u16 wm8985_reg_defs[] = {
  43         0x0000,     /* R0  - Software Reset */
  44         0x0000,     /* R1  - Power management 1 */
  45         0x0000,     /* R2  - Power management 2 */
  46         0x0000,     /* R3  - Power management 3 */
  47         0x0050,     /* R4  - Audio Interface */
  48         0x0000,     /* R5  - Companding control */
  49         0x0140,     /* R6  - Clock Gen control */
  50         0x0000,     /* R7  - Additional control */
  51         0x0000,     /* R8  - GPIO Control */
  52         0x0000,     /* R9  - Jack Detect Control 1 */
  53         0x0000,     /* R10 - DAC Control */
  54         0x00FF,     /* R11 - Left DAC digital Vol */
  55         0x00FF,     /* R12 - Right DAC digital vol */
  56         0x0000,     /* R13 - Jack Detect Control 2 */
  57         0x0100,     /* R14 - ADC Control */
  58         0x00FF,     /* R15 - Left ADC Digital Vol */
  59         0x00FF,     /* R16 - Right ADC Digital Vol */
  60         0x0000,     /* R17 */
  61         0x012C,     /* R18 - EQ1 - low shelf */
  62         0x002C,     /* R19 - EQ2 - peak 1 */
  63         0x002C,     /* R20 - EQ3 - peak 2 */
  64         0x002C,     /* R21 - EQ4 - peak 3 */
  65         0x002C,     /* R22 - EQ5 - high shelf */
  66         0x0000,     /* R23 */
  67         0x0032,     /* R24 - DAC Limiter 1 */
  68         0x0000,     /* R25 - DAC Limiter 2 */
  69         0x0000,     /* R26 */
  70         0x0000,     /* R27 - Notch Filter 1 */
  71         0x0000,     /* R28 - Notch Filter 2 */
  72         0x0000,     /* R29 - Notch Filter 3 */
  73         0x0000,     /* R30 - Notch Filter 4 */
  74         0x0000,     /* R31 */
  75         0x0038,     /* R32 - ALC control 1 */
  76         0x000B,     /* R33 - ALC control 2 */
  77         0x0032,     /* R34 - ALC control 3 */
  78         0x0000,     /* R35 - Noise Gate */
  79         0x0008,     /* R36 - PLL N */
  80         0x000C,     /* R37 - PLL K 1 */
  81         0x0093,     /* R38 - PLL K 2 */
  82         0x00E9,     /* R39 - PLL K 3 */
  83         0x0000,     /* R40 */
  84         0x0000,     /* R41 - 3D control */
  85         0x0000,     /* R42 - OUT4 to ADC */
  86         0x0000,     /* R43 - Beep control */
  87         0x0033,     /* R44 - Input ctrl */
  88         0x0010,     /* R45 - Left INP PGA gain ctrl */
  89         0x0010,     /* R46 - Right INP PGA gain ctrl */
  90         0x0100,     /* R47 - Left ADC BOOST ctrl */
  91         0x0100,     /* R48 - Right ADC BOOST ctrl */
  92         0x0002,     /* R49 - Output ctrl */
  93         0x0001,     /* R50 - Left mixer ctrl */
  94         0x0001,     /* R51 - Right mixer ctrl */
  95         0x0039,     /* R52 - LOUT1 (HP) volume ctrl */
  96         0x0039,     /* R53 - ROUT1 (HP) volume ctrl */
  97         0x0039,     /* R54 - LOUT2 (SPK) volume ctrl */
  98         0x0039,     /* R55 - ROUT2 (SPK) volume ctrl */
  99         0x0001,     /* R56 - OUT3 mixer ctrl */
 100         0x0001,     /* R57 - OUT4 (MONO) mix ctrl */
 101         0x0001,     /* R58 */
 102         0x0000,     /* R59 */
 103         0x0004,     /* R60 - OUTPUT ctrl */
 104         0x0000,     /* R61 - BIAS CTRL */
 105         0x0180,     /* R62 */
 106         0x0000      /* R63 */
 107 };
 108
 109 /*
 110  * latch bit 8 of these registers to ensure instant
 111  * volume updates
 112  */
 113 static const int volume_update_regs[] = {
 114         WM8985_LEFT_DAC_DIGITAL_VOL,
 115         WM8985_RIGHT_DAC_DIGITAL_VOL,
 116         WM8985_LEFT_ADC_DIGITAL_VOL,
 117         WM8985_RIGHT_ADC_DIGITAL_VOL,
 118         WM8985_LOUT2_SPK_VOLUME_CTRL,
 119         WM8985_ROUT2_SPK_VOLUME_CTRL,
 120         WM8985_LOUT1_HP_VOLUME_CTRL,
 121         WM8985_ROUT1_HP_VOLUME_CTRL,
 122         WM8985_LEFT_INP_PGA_GAIN_CTRL,
 123         WM8985_RIGHT_INP_PGA_GAIN_CTRL
 124 };
 125
 126 struct wm8985_priv {
 127         enum snd_soc_control_type control_type;
 128         struct regulator_bulk_data supplies[WM8985_NUM_SUPPLIES];
 129         unsigned int sysclk;
 130         unsigned int bclk;
 131 };
 132
 133 static const struct {
 134         int div;
 135         int ratio;
 136 } fs_ratios[] = {
 137         { 10, 128 },
 138         { 15, 192 },
 139         { 20, 256 },
 140         { 30, 384 },
 141         { 40, 512 },
 142         { 60, 768 },
 143         { 80, 1024 },
 144         { 120, 1536 }
 145 };
 146
 147 static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
 148
 149 static const int bclk_divs[] = {
 150         1, 2, 4, 8, 16, 32
 151 };
 152
 153 static int eqmode_get(struct snd_kcontrol *kcontrol,
 154                       struct snd_ctl_elem_value *ucontrol);
 155 static int eqmode_put(struct snd_kcontrol *kcontrol,
 156                       struct snd_ctl_elem_value *ucontrol);
 157
 158 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
 159 static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
 160 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
 161 static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
 162 static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
 163 static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
 164 static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
 165 static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
 166 static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
 167 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
 168 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 169 static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
 170 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
 171 static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
 172
 173 static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
 174 static const SOC_ENUM_SINGLE_DECL(alc_sel, WM8985_ALC_CONTROL_1, 7,
 175                                   alc_sel_text);
 176
 177 static const char *alc_mode_text[] = { "ALC", "Limiter" };
 178 static const SOC_ENUM_SINGLE_DECL(alc_mode, WM8985_ALC_CONTROL_3, 8,
 179                                   alc_mode_text);
 180
 181 static const char *filter_mode_text[] = { "Audio", "Application" };
 182 static const SOC_ENUM_SINGLE_DECL(filter_mode, WM8985_ADC_CONTROL, 7,
 183                                   filter_mode_text);
 184
 185 static const char *eq_bw_text[] = { "Narrow", "Wide" };
 186 static const char *eqmode_text[] = { "Capture", "Playback" };
 187 static const SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
 188
 189 static const char *eq1_cutoff_text[] = {
 190         "80Hz", "105Hz", "135Hz", "175Hz"
 191 };
 192 static const SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8985_EQ1_LOW_SHELF, 5,
 193                                   eq1_cutoff_text);
 194 static const char *eq2_cutoff_text[] = {
 195         "230Hz", "300Hz", "385Hz", "500Hz"
 196 };
 197 static const SOC_ENUM_SINGLE_DECL(eq2_bw, WM8985_EQ2_PEAK_1, 8, eq_bw_text);
 198 static const SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8985_EQ2_PEAK_1, 5,
 199                                   eq2_cutoff_text);
 200 static const char *eq3_cutoff_text[] = {
 201         "650Hz", "850Hz", "1.1kHz", "1.4kHz"
 202 };
 203 static const SOC_ENUM_SINGLE_DECL(eq3_bw, WM8985_EQ3_PEAK_2, 8, eq_bw_text);
 204 static const SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8985_EQ3_PEAK_2, 5,
 205                                   eq3_cutoff_text);
 206 static const char *eq4_cutoff_text[] = {
 207         "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
 208 };
 209 static const SOC_ENUM_SINGLE_DECL(eq4_bw, WM8985_EQ4_PEAK_3, 8, eq_bw_text);
 210 static const SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8985_EQ4_PEAK_3, 5,
 211                                   eq4_cutoff_text);
 212 static const char *eq5_cutoff_text[] = {
 213         "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
 214 };
 215 static const SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8985_EQ5_HIGH_SHELF, 5,
 216                                   eq5_cutoff_text);
 217
 218 static const char *speaker_mode_text[] = { "Class A/B", "Class D" };
 219 static const SOC_ENUM_SINGLE_DECL(speaker_mode, 0x17, 8, speaker_mode_text);
 220
 221 static const char *depth_3d_text[] = {
 222         "Off",
 223         "6.67%",
 224         "13.3%",
 225         "20%",
 226         "26.7%",
 227         "33.3%",
 228         "40%",
 229         "46.6%",
 230         "53.3%",
 231         "60%",
 232         "66.7%",
 233         "73.3%",
 234         "80%",
 235         "86.7%",
 236         "93.3%",
 237         "100%"
 238 };
 239 static const SOC_ENUM_SINGLE_DECL(depth_3d, WM8985_3D_CONTROL, 0,
 240                                   depth_3d_text);
 241
 242 static const struct snd_kcontrol_new wm8985_snd_controls[] = {
 243         SOC_SINGLE("Digital Loopback Switch", WM8985_COMPANDING_CONTROL,
 244                 0, 1, 0),
 245
 246         SOC_ENUM("ALC Capture Function", alc_sel),
 247         SOC_SINGLE_TLV("ALC Capture Max Volume", WM8985_ALC_CONTROL_1,
 248                 3, 7, 0, alc_max_tlv),
 249         SOC_SINGLE_TLV("ALC Capture Min Volume", WM8985_ALC_CONTROL_1,
 250                 0, 7, 0, alc_min_tlv),
 251         SOC_SINGLE_TLV("ALC Capture Target Volume", WM8985_ALC_CONTROL_2,
 252                 0, 15, 0, alc_tar_tlv),
 253         SOC_SINGLE("ALC Capture Attack", WM8985_ALC_CONTROL_3, 0, 10, 0),
 254         SOC_SINGLE("ALC Capture Hold", WM8985_ALC_CONTROL_2, 4, 10, 0),
 255         SOC_SINGLE("ALC Capture Decay", WM8985_ALC_CONTROL_3, 4, 10, 0),
 256         SOC_ENUM("ALC Mode", alc_mode),
 257         SOC_SINGLE("ALC Capture NG Switch", WM8985_NOISE_GATE,
 258                 3, 1, 0),
 259         SOC_SINGLE("ALC Capture NG Threshold", WM8985_NOISE_GATE,
 260                 0, 7, 1),
 261
 262         SOC_DOUBLE_R_TLV("Capture Volume", WM8985_LEFT_ADC_DIGITAL_VOL,
 263                 WM8985_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
 264         SOC_DOUBLE_R("Capture PGA ZC Switch", WM8985_LEFT_INP_PGA_GAIN_CTRL,
 265                 WM8985_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
 266         SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8985_LEFT_INP_PGA_GAIN_CTRL,
 267                 WM8985_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
 268
 269         SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
 270                 WM8985_LEFT_ADC_BOOST_CTRL, WM8985_RIGHT_ADC_BOOST_CTRL,
 271                 8, 1, 0, pga_boost_tlv),
 272
 273         SOC_DOUBLE("ADC Inversion Switch", WM8985_ADC_CONTROL, 0, 1, 1, 0),
 274         SOC_SINGLE("ADC 128x Oversampling Switch", WM8985_ADC_CONTROL, 8, 1, 0),
 275
 276         SOC_DOUBLE_R_TLV("Playback Volume", WM8985_LEFT_DAC_DIGITAL_VOL,
 277                 WM8985_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
 278
 279         SOC_SINGLE("DAC Playback Limiter Switch", WM8985_DAC_LIMITER_1, 8, 1, 0),
 280         SOC_SINGLE("DAC Playback Limiter Decay", WM8985_DAC_LIMITER_1, 4, 10, 0),
 281         SOC_SINGLE("DAC Playback Limiter Attack", WM8985_DAC_LIMITER_1, 0, 11, 0),
 282         SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8985_DAC_LIMITER_2,
 283                 4, 7, 1, lim_thresh_tlv),
 284         SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8985_DAC_LIMITER_2,
 285                 0, 12, 0, lim_boost_tlv),
 286         SOC_DOUBLE("DAC Inversion Switch", WM8985_DAC_CONTROL, 0, 1, 1, 0),
 287         SOC_SINGLE("DAC Auto Mute Switch", WM8985_DAC_CONTROL, 2, 1, 0),
 288         SOC_SINGLE("DAC 128x Oversampling Switch", WM8985_DAC_CONTROL, 3, 1, 0),
 289
 290         SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8985_LOUT1_HP_VOLUME_CTRL,
 291                 WM8985_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
 292         SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
 293                 WM8985_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
 294         SOC_DOUBLE_R("Headphone Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
 295                 WM8985_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
 296
 297         SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8985_LOUT2_SPK_VOLUME_CTRL,
 298                 WM8985_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
 299         SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
 300                 WM8985_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
 301         SOC_DOUBLE_R("Speaker Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
 302                 WM8985_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
 303
 304         SOC_SINGLE("High Pass Filter Switch", WM8985_ADC_CONTROL, 8, 1, 0),
 305         SOC_ENUM("High Pass Filter Mode", filter_mode),
 306         SOC_SINGLE("High Pass Filter Cutoff", WM8985_ADC_CONTROL, 4, 7, 0),
 307
 308         SOC_DOUBLE_R_TLV("Aux Bypass Volume",
 309                 WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 6, 7, 0,
 310                 aux_tlv),
 311
 312         SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
 313                 WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 2, 7, 0,
 314                 bypass_tlv),
 315
 316         SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
 317         SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
 318         SOC_SINGLE_TLV("EQ1 Volume", WM8985_EQ1_LOW_SHELF,  0, 24, 1, eq_tlv),
 319         SOC_ENUM("EQ2 Bandwith", eq2_bw),
 320         SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
 321         SOC_SINGLE_TLV("EQ2 Volume", WM8985_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
 322         SOC_ENUM("EQ3 Bandwith", eq3_bw),
 323         SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
 324         SOC_SINGLE_TLV("EQ3 Volume", WM8985_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
 325         SOC_ENUM("EQ4 Bandwith", eq4_bw),
 326         SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
 327         SOC_SINGLE_TLV("EQ4 Volume", WM8985_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
 328         SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
 329         SOC_SINGLE_TLV("EQ5 Volume", WM8985_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
 330
 331         SOC_ENUM("3D Depth", depth_3d),
 332
 333         SOC_ENUM("Speaker Mode", speaker_mode)
 334 };
 335
 336 static const struct snd_kcontrol_new left_out_mixer[] = {
 337         SOC_DAPM_SINGLE("Line Switch", WM8985_LEFT_MIXER_CTRL, 1, 1, 0),
 338         SOC_DAPM_SINGLE("Aux Switch", WM8985_LEFT_MIXER_CTRL, 5, 1, 0),
 339         SOC_DAPM_SINGLE("PCM Switch", WM8985_LEFT_MIXER_CTRL, 0, 1, 0),
 340 };
 341
 342 static const struct snd_kcontrol_new right_out_mixer[] = {
 343         SOC_DAPM_SINGLE("Line Switch", WM8985_RIGHT_MIXER_CTRL, 1, 1, 0),
 344         SOC_DAPM_SINGLE("Aux Switch", WM8985_RIGHT_MIXER_CTRL, 5, 1, 0),
 345         SOC_DAPM_SINGLE("PCM Switch", WM8985_RIGHT_MIXER_CTRL, 0, 1, 0),
 346 };
 347
 348 static const struct snd_kcontrol_new left_input_mixer[] = {
 349         SOC_DAPM_SINGLE("L2 Switch", WM8985_INPUT_CTRL, 2, 1, 0),
 350         SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 1, 1, 0),
 351         SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 0, 1, 0),
 352 };
 353
 354 static const struct snd_kcontrol_new right_input_mixer[] = {
 355         SOC_DAPM_SINGLE("R2 Switch", WM8985_INPUT_CTRL, 6, 1, 0),
 356         SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 5, 1, 0),
 357         SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 4, 1, 0),
 358 };
 359
 360 static const struct snd_kcontrol_new left_boost_mixer[] = {
 361         SOC_DAPM_SINGLE_TLV("L2 Volume", WM8985_LEFT_ADC_BOOST_CTRL,
 362                 4, 7, 0, boost_tlv),
 363         SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8985_LEFT_ADC_BOOST_CTRL,
 364                 0, 7, 0, boost_tlv)
 365 };
 366
 367 static const struct snd_kcontrol_new right_boost_mixer[] = {
 368         SOC_DAPM_SINGLE_TLV("R2 Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
 369                 4, 7, 0, boost_tlv),
 370         SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
 371                 0, 7, 0, boost_tlv)
 372 };
 373
 374 static const struct snd_soc_dapm_widget wm8985_dapm_widgets[] = {
 375         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8985_POWER_MANAGEMENT_3,
 376                 0, 0),
 377         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8985_POWER_MANAGEMENT_3,
 378                 1, 0),
 379         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8985_POWER_MANAGEMENT_2,
 380                 0, 0),
 381         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8985_POWER_MANAGEMENT_2,
 382                 1, 0),
 383
 384         SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
 385                 2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
 386         SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
 387                 3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
 388
 389         SND_SOC_DAPM_MIXER("Left Input Mixer", WM8985_POWER_MANAGEMENT_2,
 390                 2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
 391         SND_SOC_DAPM_MIXER("Right Input Mixer", WM8985_POWER_MANAGEMENT_2,
 392                 3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
 393
 394         SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
 395                 4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
 396         SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
 397                 5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
 398
 399         SND_SOC_DAPM_PGA("Left Capture PGA", WM8985_LEFT_INP_PGA_GAIN_CTRL,
 400                 6, 1, NULL, 0),
 401         SND_SOC_DAPM_PGA("Right Capture PGA", WM8985_RIGHT_INP_PGA_GAIN_CTRL,
 402                 6, 1, NULL, 0),
 403
 404         SND_SOC_DAPM_PGA("Left Headphone Out", WM8985_POWER_MANAGEMENT_2,
 405                 7, 0, NULL, 0),
 406         SND_SOC_DAPM_PGA("Right Headphone Out", WM8985_POWER_MANAGEMENT_2,
 407                 8, 0, NULL, 0),
 408
 409         SND_SOC_DAPM_PGA("Left Speaker Out", WM8985_POWER_MANAGEMENT_3,
 410                 5, 0, NULL, 0),
 411         SND_SOC_DAPM_PGA("Right Speaker Out", WM8985_POWER_MANAGEMENT_3,
 412                 6, 0, NULL, 0),
 413
 414         SND_SOC_DAPM_SUPPLY("Mic Bias", WM8985_POWER_MANAGEMENT_1, 4, 0,
 415                             NULL, 0),
 416
 417         SND_SOC_DAPM_INPUT("LIN"),
 418         SND_SOC_DAPM_INPUT("LIP"),
 419         SND_SOC_DAPM_INPUT("RIN"),
 420         SND_SOC_DAPM_INPUT("RIP"),
 421         SND_SOC_DAPM_INPUT("AUXL"),
 422         SND_SOC_DAPM_INPUT("AUXR"),
 423         SND_SOC_DAPM_INPUT("L2"),
 424         SND_SOC_DAPM_INPUT("R2"),
 425         SND_SOC_DAPM_OUTPUT("HPL"),
 426         SND_SOC_DAPM_OUTPUT("HPR"),
 427         SND_SOC_DAPM_OUTPUT("SPKL"),
 428         SND_SOC_DAPM_OUTPUT("SPKR")
 429 };
 430
 431 static const struct snd_soc_dapm_route audio_map[] = {
 432         { "Right Output Mixer", "PCM Switch", "Right DAC" },
 433         { "Right Output Mixer", "Aux Switch", "AUXR" },
 434         { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
 435
 436         { "Left Output Mixer", "PCM Switch", "Left DAC" },
 437         { "Left Output Mixer", "Aux Switch", "AUXL" },
 438         { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
 439
 440         { "Right Headphone Out", NULL, "Right Output Mixer" },
 441         { "HPR", NULL, "Right Headphone Out" },
 442
 443         { "Left Headphone Out", NULL, "Left Output Mixer" },
 444         { "HPL", NULL, "Left Headphone Out" },
 445
 446         { "Right Speaker Out", NULL, "Right Output Mixer" },
 447         { "SPKR", NULL, "Right Speaker Out" },
 448
 449         { "Left Speaker Out", NULL, "Left Output Mixer" },
 450         { "SPKL", NULL, "Left Speaker Out" },
 451
 452         { "Right ADC", NULL, "Right Boost Mixer" },
 453
 454         { "Right Boost Mixer", "AUXR Volume", "AUXR" },
 455         { "Right Boost Mixer", NULL, "Right Capture PGA" },
 456         { "Right Boost Mixer", "R2 Volume", "R2" },
 457
 458         { "Left ADC", NULL, "Left Boost Mixer" },
 459
 460         { "Left Boost Mixer", "AUXL Volume", "AUXL" },
 461         { "Left Boost Mixer", NULL, "Left Capture PGA" },
 462         { "Left Boost Mixer", "L2 Volume", "L2" },
 463
 464         { "Right Capture PGA", NULL, "Right Input Mixer" },
 465         { "Left Capture PGA", NULL, "Left Input Mixer" },
 466
 467         { "Right Input Mixer", "R2 Switch", "R2" },
 468         { "Right Input Mixer", "MicN Switch", "RIN" },
 469         { "Right Input Mixer", "MicP Switch", "RIP" },
 470
 471         { "Left Input Mixer", "L2 Switch", "L2" },
 472         { "Left Input Mixer", "MicN Switch", "LIN" },
 473         { "Left Input Mixer", "MicP Switch", "LIP" },
 474 };
 475
 476 static int eqmode_get(struct snd_kcontrol *kcontrol,
 477                       struct snd_ctl_elem_value *ucontrol)
 478 {
 479         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 480         unsigned int reg;
 481
 482         reg = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
 483         if (reg & WM8985_EQ3DMODE)
 484                 ucontrol->value.integer.value[0] = 1;
 485         else
 486                 ucontrol->value.integer.value[0] = 0;
 487
 488         return 0;
 489 }
 490
 491 static int eqmode_put(struct snd_kcontrol *kcontrol,
 492                       struct snd_ctl_elem_value *ucontrol)
 493 {
 494         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 495         unsigned int regpwr2, regpwr3;
 496         unsigned int reg_eq;
 497
 498         if (ucontrol->value.integer.value[0] != 0
 499                         && ucontrol->value.integer.value[0] != 1)
 500                 return -EINVAL;
 501
 502         reg_eq = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
 503         switch ((reg_eq & WM8985_EQ3DMODE) >> WM8985_EQ3DMODE_SHIFT) {
 504         case 0:
 505                 if (!ucontrol->value.integer.value[0])
 506                         return 0;
 507                 break;
 508         case 1:
 509                 if (ucontrol->value.integer.value[0])
 510                         return 0;
 511                 break;
 512         }
 513
 514         regpwr2 = snd_soc_read(codec, WM8985_POWER_MANAGEMENT_2);
 515         regpwr3 = snd_soc_read(codec, WM8985_POWER_MANAGEMENT_3);
 516         /* disable the DACs and ADCs */
 517         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_2,
 518                             WM8985_ADCENR_MASK | WM8985_ADCENL_MASK, 0);
 519         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_3,
 520                             WM8985_DACENR_MASK | WM8985_DACENL_MASK, 0);
 521         snd_soc_update_bits(codec, WM8985_ADDITIONAL_CONTROL,
 522                             WM8985_M128ENB_MASK, WM8985_M128ENB);
 523         /* set the desired eqmode */
 524         snd_soc_update_bits(codec, WM8985_EQ1_LOW_SHELF,
 525                             WM8985_EQ3DMODE_MASK,
 526                             ucontrol->value.integer.value[0]
 527                             << WM8985_EQ3DMODE_SHIFT);
 528         /* restore DAC/ADC configuration */
 529         snd_soc_write(codec, WM8985_POWER_MANAGEMENT_2, regpwr2);
 530         snd_soc_write(codec, WM8985_POWER_MANAGEMENT_3, regpwr3);
 531         return 0;
 532 }
 533
 534 static int wm8985_add_widgets(struct snd_soc_codec *codec)
 535 {
 536         struct snd_soc_dapm_context *dapm = &codec->dapm;
 537
 538         snd_soc_dapm_new_controls(dapm, wm8985_dapm_widgets,
 539                                   ARRAY_SIZE(wm8985_dapm_widgets));
 540         snd_soc_dapm_add_routes(dapm, audio_map,
 541                                 ARRAY_SIZE(audio_map));
 542         return 0;
 543 }
 544
 545 static int wm8985_reset(struct snd_soc_codec *codec)
 546 {
 547         return snd_soc_write(codec, WM8985_SOFTWARE_RESET, 0x0);
 548 }
 549
 550 static int wm8985_dac_mute(struct snd_soc_dai *dai, int mute)
 551 {
 552         struct snd_soc_codec *codec = dai->codec;
 553
 554         return snd_soc_update_bits(codec, WM8985_DAC_CONTROL,
 555                                    WM8985_SOFTMUTE_MASK,
 556                                    !!mute << WM8985_SOFTMUTE_SHIFT);
 557 }
 558
 559 static int wm8985_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 560 {
 561         struct snd_soc_codec *codec;
 562         u16 format, master, bcp, lrp;
 563
 564         codec = dai->codec;
 565
 566         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 567         case SND_SOC_DAIFMT_I2S:
 568                 format = 0x2;
 569                 break;
 570         case SND_SOC_DAIFMT_RIGHT_J:
 571                 format = 0x0;
 572                 break;
 573         case SND_SOC_DAIFMT_LEFT_J:
 574                 format = 0x1;
 575                 break;
 576         case SND_SOC_DAIFMT_DSP_A:
 577         case SND_SOC_DAIFMT_DSP_B:
 578                 format = 0x3;
 579                 break;
 580         default:
 581                 dev_err(dai->dev, "Unknown dai format\n");
 582                 return -EINVAL;
 583         }
 584
 585         snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
 586                             WM8985_FMT_MASK, format << WM8985_FMT_SHIFT);
 587
 588         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 589         case SND_SOC_DAIFMT_CBM_CFM:
 590                 master = 1;
 591                 break;
 592         case SND_SOC_DAIFMT_CBS_CFS:
 593                 master = 0;
 594                 break;
 595         default:
 596                 dev_err(dai->dev, "Unknown master/slave configuration\n");
 597                 return -EINVAL;
 598         }
 599
 600         snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 601                             WM8985_MS_MASK, master << WM8985_MS_SHIFT);
 602
 603         /* frame inversion is not valid for dsp modes */
 604         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 605         case SND_SOC_DAIFMT_DSP_A:
 606         case SND_SOC_DAIFMT_DSP_B:
 607                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 608                 case SND_SOC_DAIFMT_IB_IF:
 609                 case SND_SOC_DAIFMT_NB_IF:
 610                         return -EINVAL;
 611                 default:
 612                         break;
 613                 }
 614                 break;
 615         default:
 616                 break;
 617         }
 618
 619         bcp = lrp = 0;
 620         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 621         case SND_SOC_DAIFMT_NB_NF:
 622                 break;
 623         case SND_SOC_DAIFMT_IB_IF:
 624                 bcp = lrp = 1;
 625                 break;
 626         case SND_SOC_DAIFMT_IB_NF:
 627                 bcp = 1;
 628                 break;
 629         case SND_SOC_DAIFMT_NB_IF:
 630                 lrp = 1;
 631                 break;
 632         default:
 633                 dev_err(dai->dev, "Unknown polarity configuration\n");
 634                 return -EINVAL;
 635         }
 636
 637         snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
 638                             WM8985_LRP_MASK, lrp << WM8985_LRP_SHIFT);
 639         snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
 640                             WM8985_BCP_MASK, bcp << WM8985_BCP_SHIFT);
 641         return 0;
 642 }
 643
 644 static int wm8985_hw_params(struct snd_pcm_substream *substream,
 645                             struct snd_pcm_hw_params *params,
 646                             struct snd_soc_dai *dai)
 647 {
 648         int i;
 649         struct snd_soc_codec *codec;
 650         struct wm8985_priv *wm8985;
 651         u16 blen, srate_idx;
 652         unsigned int tmp;
 653         int srate_best;
 654
 655         codec = dai->codec;
 656         wm8985 = snd_soc_codec_get_drvdata(codec);
 657
 658         wm8985->bclk = snd_soc_params_to_bclk(params);
 659         if ((int)wm8985->bclk < 0)
 660                 return wm8985->bclk;
 661
 662         switch (params_format(params)) {
 663         case SNDRV_PCM_FORMAT_S16_LE:
 664                 blen = 0x0;
 665                 break;
 666         case SNDRV_PCM_FORMAT_S20_3LE:
 667                 blen = 0x1;
 668                 break;
 669         case SNDRV_PCM_FORMAT_S24_LE:
 670                 blen = 0x2;
 671                 break;
 672         case SNDRV_PCM_FORMAT_S32_LE:
 673                 blen = 0x3;
 674                 break;
 675         default:
 676                 dev_err(dai->dev, "Unsupported word length %u\n",
 677                         params_format(params));
 678                 return -EINVAL;
 679         }
 680
 681         snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
 682                             WM8985_WL_MASK, blen << WM8985_WL_SHIFT);
 683
 684         /*
 685          * match to the nearest possible sample rate and rely
 686          * on the array index to configure the SR register
 687          */
 688         srate_idx = 0;
 689         srate_best = abs(srates[0] - params_rate(params));
 690         for (i = 1; i < ARRAY_SIZE(srates); ++i) {
 691                 if (abs(srates[i] - params_rate(params)) >= srate_best)
 692                         continue;
 693                 srate_idx = i;
 694                 srate_best = abs(srates[i] - params_rate(params));
 695         }
 696
 697         dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
 698         snd_soc_update_bits(codec, WM8985_ADDITIONAL_CONTROL,
 699                             WM8985_SR_MASK, srate_idx << WM8985_SR_SHIFT);
 700
 701         dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8985->bclk);
 702         dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8985->sysclk);
 703
 704         for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
 705                 if (wm8985->sysclk / params_rate(params)
 706                                 == fs_ratios[i].ratio)
 707                         break;
 708         }
 709
 710         if (i == ARRAY_SIZE(fs_ratios)) {
 711                 dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
 712                         wm8985->sysclk, params_rate(params));
 713                 return -EINVAL;
 714         }
 715
 716         dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
 717         snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 718                             WM8985_MCLKDIV_MASK, i << WM8985_MCLKDIV_SHIFT);
 719
 720         /* select the appropriate bclk divider */
 721         tmp = (wm8985->sysclk / fs_ratios[i].div) * 10;
 722         for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
 723                 if (wm8985->bclk == tmp / bclk_divs[i])
 724                         break;
 725         }
 726
 727         if (i == ARRAY_SIZE(bclk_divs)) {
 728                 dev_err(dai->dev, "No matching BCLK divider found\n");
 729                 return -EINVAL;
 730         }
 731
 732         dev_dbg(dai->dev, "BCLK div = %d\n", i);
 733         snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 734                             WM8985_BCLKDIV_MASK, i << WM8985_BCLKDIV_SHIFT);
 735         return 0;
 736 }
 737
 738 struct pll_div {
 739         u32 div2:1;
 740         u32 n:4;
 741         u32 k:24;
 742 };
 743
 744 #define FIXED_PLL_SIZE ((1ULL << 24) * 10)
 745 static int pll_factors(struct pll_div *pll_div, unsigned int target,
 746                        unsigned int source)
 747 {
 748         u64 Kpart;
 749         unsigned long int K, Ndiv, Nmod;
 750
 751         pll_div->div2 = 0;
 752         Ndiv = target / source;
 753         if (Ndiv < 6) {
 754                 source >>= 1;
 755                 pll_div->div2 = 1;
 756                 Ndiv = target / source;
 757         }
 758
 759         if (Ndiv < 6 || Ndiv > 12) {
 760                 printk(KERN_ERR "%s: WM8985 N value is not within"
 761                        " the recommended range: %lu\n", __func__, Ndiv);
 762                 return -EINVAL;
 763         }
 764         pll_div->n = Ndiv;
 765
 766         Nmod = target % source;
 767         Kpart = FIXED_PLL_SIZE * (u64)Nmod;
 768
 769         do_div(Kpart, source);
 770
 771         K = Kpart & 0xffffffff;
 772         if ((K % 10) >= 5)
 773                 K += 5;
 774         K /= 10;
 775         pll_div->k = K;
 776
 777         return 0;
 778 }
 779
 780 static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id,
 781                           int source, unsigned int freq_in,
 782                           unsigned int freq_out)
 783 {
 784         int ret;
 785         struct snd_soc_codec *codec;
 786         struct pll_div pll_div;
 787
 788         codec = dai->codec;
 789         if (freq_in && freq_out) {
 790                 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
 791                 if (ret)
 792                         return ret;
 793         }
 794
 795         /* disable the PLL before reprogramming it */
 796         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 797                             WM8985_PLLEN_MASK, 0);
 798
 799         if (!freq_in || !freq_out)
 800                 return 0;
 801
 802         /* set PLLN and PRESCALE */
 803         snd_soc_write(codec, WM8985_PLL_N,
 804                       (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT)
 805                       | pll_div.n);
 806         /* set PLLK */
 807         snd_soc_write(codec, WM8985_PLL_K_3, pll_div.k & 0x1ff);
 808         snd_soc_write(codec, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
 809         snd_soc_write(codec, WM8985_PLL_K_1, (pll_div.k >> 18));
 810         /* set the source of the clock to be the PLL */
 811         snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 812                             WM8985_CLKSEL_MASK, WM8985_CLKSEL);
 813         /* enable the PLL */
 814         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 815                             WM8985_PLLEN_MASK, WM8985_PLLEN);
 816         return 0;
 817 }
 818
 819 static int wm8985_set_sysclk(struct snd_soc_dai *dai,
 820                              int clk_id, unsigned int freq, int dir)
 821 {
 822         struct snd_soc_codec *codec;
 823         struct wm8985_priv *wm8985;
 824
 825         codec = dai->codec;
 826         wm8985 = snd_soc_codec_get_drvdata(codec);
 827
 828         switch (clk_id) {
 829         case WM8985_CLKSRC_MCLK:
 830                 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 831                                     WM8985_CLKSEL_MASK, 0);
 832                 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 833                                     WM8985_PLLEN_MASK, 0);
 834                 break;
 835         case WM8985_CLKSRC_PLL:
 836                 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 837                                     WM8985_CLKSEL_MASK, WM8985_CLKSEL);
 838                 break;
 839         default:
 840                 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
 841                 return -EINVAL;
 842         }
 843
 844         wm8985->sysclk = freq;
 845         return 0;
 846 }
 847
 848 static void wm8985_sync_cache(struct snd_soc_codec *codec)
 849 {
 850         short i;
 851         u16 *cache;
 852
 853         if (!codec->cache_sync)
 854                 return;
 855         codec->cache_only = 0;
 856         /* restore cache */
 857         cache = codec->reg_cache;
 858         for (i = 0; i < codec->driver->reg_cache_size; i++) {
 859                 if (i == WM8985_SOFTWARE_RESET
 860                                 || cache[i] == wm8985_reg_defs[i])
 861                         continue;
 862                 snd_soc_write(codec, i, cache[i]);
 863         }
 864         codec->cache_sync = 0;
 865 }
 866
 867 static int wm8985_set_bias_level(struct snd_soc_codec *codec,
 868                                  enum snd_soc_bias_level level)
 869 {
 870         int ret;
 871         struct wm8985_priv *wm8985;
 872
 873         wm8985 = snd_soc_codec_get_drvdata(codec);
 874         switch (level) {
 875         case SND_SOC_BIAS_ON:
 876         case SND_SOC_BIAS_PREPARE:
 877                 /* VMID at 75k */
 878                 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 879                                     WM8985_VMIDSEL_MASK,
 880                                     1 << WM8985_VMIDSEL_SHIFT);
 881                 break;
 882         case SND_SOC_BIAS_STANDBY:
 883                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
 884                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
 885                                                     wm8985->supplies);
 886                         if (ret) {
 887                                 dev_err(codec->dev,
 888                                         "Failed to enable supplies: %d\n",
 889                                         ret);
 890                                 return ret;
 891                         }
 892
 893                         wm8985_sync_cache(codec);
 894
 895                         /* enable anti-pop features */
 896                         snd_soc_update_bits(codec, WM8985_OUT4_TO_ADC,
 897                                             WM8985_POBCTRL_MASK,
 898                                             WM8985_POBCTRL);
 899                         /* enable thermal shutdown */
 900                         snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
 901                                             WM8985_TSDEN_MASK, WM8985_TSDEN);
 902                         snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
 903                                             WM8985_TSOPCTRL_MASK,
 904                                             WM8985_TSOPCTRL);
 905                         /* enable BIASEN */
 906                         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 907                                             WM8985_BIASEN_MASK, WM8985_BIASEN);
 908                         /* VMID at 75k */
 909                         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 910                                             WM8985_VMIDSEL_MASK,
 911                                             1 << WM8985_VMIDSEL_SHIFT);
 912                         msleep(500);
 913                         /* disable anti-pop features */
 914                         snd_soc_update_bits(codec, WM8985_OUT4_TO_ADC,
 915                                             WM8985_POBCTRL_MASK, 0);
 916                 }
 917                 /* VMID at 300k */
 918                 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 919                                     WM8985_VMIDSEL_MASK,
 920                                     2 << WM8985_VMIDSEL_SHIFT);
 921                 break;
 922         case SND_SOC_BIAS_OFF:
 923                 /* disable thermal shutdown */
 924                 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
 925                                     WM8985_TSOPCTRL_MASK, 0);
 926                 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
 927                                     WM8985_TSDEN_MASK, 0);
 928                 /* disable VMIDSEL and BIASEN */
 929                 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 930                                     WM8985_VMIDSEL_MASK | WM8985_BIASEN_MASK,
 931                                     0);
 932                 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_1, 0);
 933                 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_2, 0);
 934                 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_3, 0);
 935
 936                 codec->cache_sync = 1;
 937
 938                 regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies),
 939                                        wm8985->supplies);
 940                 break;
 941         }
 942
 943         codec->dapm.bias_level = level;
 944         return 0;
 945 }
 946
 947 #ifdef CONFIG_PM
 948 static int wm8985_suspend(struct snd_soc_codec *codec)
 949 {
 950         wm8985_set_bias_level(codec, SND_SOC_BIAS_OFF);
 951         return 0;
 952 }
 953
 954 static int wm8985_resume(struct snd_soc_codec *codec)
 955 {
 956         wm8985_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 957         return 0;
 958 }
 959 #else
 960 #define wm8985_suspend NULL
 961 #define wm8985_resume NULL
 962 #endif
 963
 964 static int wm8985_remove(struct snd_soc_codec *codec)
 965 {
 966         struct wm8985_priv *wm8985;
 967
 968         wm8985 = snd_soc_codec_get_drvdata(codec);
 969         wm8985_set_bias_level(codec, SND_SOC_BIAS_OFF);
 970         regulator_bulk_free(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
 971         return 0;
 972 }
 973
 974 static int wm8985_probe(struct snd_soc_codec *codec)
 975 {
 976         size_t i;
 977         struct wm8985_priv *wm8985;
 978         int ret;
 979         u16 *cache;
 980
 981         wm8985 = snd_soc_codec_get_drvdata(codec);
 982
 983         ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8985->control_type);
 984         if (ret < 0) {
 985                 dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
 986                 return ret;
 987         }
 988
 989         for (i = 0; i < ARRAY_SIZE(wm8985->supplies); i++)
 990                 wm8985->supplies[i].supply = wm8985_supply_names[i];
 991
 992         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8985->supplies),
 993                                  wm8985->supplies);
 994         if (ret) {
 995                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
 996                 return ret;
 997         }
 998
 999         ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
1000                                     wm8985->supplies);
1001         if (ret) {
1002                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1003                 goto err_reg_get;
1004         }
1005
1006         ret = wm8985_reset(codec);
1007         if (ret < 0) {
1008                 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
1009                 goto err_reg_enable;
1010         }
1011
1012         cache = codec->reg_cache;
1013         /* latch volume update bits */
1014         for (i = 0; i < ARRAY_SIZE(volume_update_regs); ++i)
1015                 cache[volume_update_regs[i]] |= 0x100;
1016         /* enable BIASCUT */
1017         cache[WM8985_BIAS_CTRL] |= WM8985_BIASCUT;
1018         codec->cache_sync = 1;
1019
1020         snd_soc_add_controls(codec, wm8985_snd_controls,
1021                              ARRAY_SIZE(wm8985_snd_controls));
1022         wm8985_add_widgets(codec);
1023
1024         wm8985_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1025         return 0;
1026
1027 err_reg_enable:
1028         regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
1029 err_reg_get:
1030         regulator_bulk_free(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
1031         return ret;
1032 }
1033
1034 static const struct snd_soc_dai_ops wm8985_dai_ops = {
1035         .digital_mute = wm8985_dac_mute,
1036         .hw_params = wm8985_hw_params,
1037         .set_fmt = wm8985_set_fmt,
1038         .set_sysclk = wm8985_set_sysclk,
1039         .set_pll = wm8985_set_pll
1040 };
1041
1042 #define WM8985_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1043                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1044
1045 static struct snd_soc_dai_driver wm8985_dai = {
1046         .name = "wm8985-hifi",
1047         .playback = {
1048                 .stream_name = "Playback",
1049                 .channels_min = 2,
1050                 .channels_max = 2,
1051                 .rates = SNDRV_PCM_RATE_8000_48000,
1052                 .formats = WM8985_FORMATS,
1053         },
1054         .capture = {
1055                 .stream_name = "Capture",
1056                 .channels_min = 2,
1057                 .channels_max = 2,
1058                 .rates = SNDRV_PCM_RATE_8000_48000,
1059                 .formats = WM8985_FORMATS,
1060         },
1061         .ops = &wm8985_dai_ops,
1062         .symmetric_rates = 1
1063 };
1064
1065 static struct snd_soc_codec_driver soc_codec_dev_wm8985 = {
1066         .probe = wm8985_probe,
1067         .remove = wm8985_remove,
1068         .suspend = wm8985_suspend,
1069         .resume = wm8985_resume,
1070         .set_bias_level = wm8985_set_bias_level,
1071         .reg_cache_size = ARRAY_SIZE(wm8985_reg_defs),
1072         .reg_word_size = sizeof(u16),
1073         .reg_cache_default = wm8985_reg_defs
1074 };
1075
1076 #if defined(CONFIG_SPI_MASTER)
1077 static int __devinit wm8985_spi_probe(struct spi_device *spi)
1078 {
1079         struct wm8985_priv *wm8985;
1080         int ret;
1081
1082         wm8985 = kzalloc(sizeof *wm8985, GFP_KERNEL);
1083         if (!wm8985)
1084                 return -ENOMEM;
1085
1086         wm8985->control_type = SND_SOC_SPI;
1087         spi_set_drvdata(spi, wm8985);
1088
1089         ret = snd_soc_register_codec(&spi->dev,
1090                                      &soc_codec_dev_wm8985, &wm8985_dai, 1);
1091         if (ret < 0)
1092                 kfree(wm8985);
1093         return ret;
1094 }
1095
1096 static int __devexit wm8985_spi_remove(struct spi_device *spi)
1097 {
1098         snd_soc_unregister_codec(&spi->dev);
1099         kfree(spi_get_drvdata(spi));
1100         return 0;
1101 }
1102
1103 static struct spi_driver wm8985_spi_driver = {
1104         .driver = {
1105                 .name = "wm8985",
1106                 .owner = THIS_MODULE,
1107         },
1108         .probe = wm8985_spi_probe,
1109         .remove = __devexit_p(wm8985_spi_remove)
1110 };
1111 #endif
1112
1113 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1114 static __devinit int wm8985_i2c_probe(struct i2c_client *i2c,
1115                                       const struct i2c_device_id *id)
1116 {
1117         struct wm8985_priv *wm8985;
1118         int ret;
1119
1120         wm8985 = kzalloc(sizeof *wm8985, GFP_KERNEL);
1121         if (!wm8985)
1122                 return -ENOMEM;
1123
1124         wm8985->control_type = SND_SOC_I2C;
1125         i2c_set_clientdata(i2c, wm8985);
1126
1127         ret = snd_soc_register_codec(&i2c->dev,
1128                                      &soc_codec_dev_wm8985, &wm8985_dai, 1);
1129         if (ret < 0)
1130                 kfree(wm8985);
1131         return ret;
1132 }
1133
1134 static __devexit int wm8985_i2c_remove(struct i2c_client *client)
1135 {
1136         snd_soc_unregister_codec(&client->dev);
1137         kfree(i2c_get_clientdata(client));
1138         return 0;
1139 }
1140
1141 static const struct i2c_device_id wm8985_i2c_id[] = {
1142         { "wm8985", 0 },
1143         { }
1144 };
1145 MODULE_DEVICE_TABLE(i2c, wm8985_i2c_id);
1146
1147 static struct i2c_driver wm8985_i2c_driver = {
1148         .driver = {
1149                 .name = "wm8985",
1150                 .owner = THIS_MODULE,
1151         },
1152         .probe = wm8985_i2c_probe,
1153         .remove = __devexit_p(wm8985_i2c_remove),
1154         .id_table = wm8985_i2c_id
1155 };
1156 #endif
1157
1158 static int __init wm8985_modinit(void)
1159 {
1160         int ret = 0;
1161
1162 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1163         ret = i2c_add_driver(&wm8985_i2c_driver);
1164         if (ret) {
1165                 printk(KERN_ERR "Failed to register wm8985 I2C driver: %d\n",
1166                        ret);
1167         }
1168 #endif
1169 #if defined(CONFIG_SPI_MASTER)
1170         ret = spi_register_driver(&wm8985_spi_driver);
1171         if (ret != 0) {
1172                 printk(KERN_ERR "Failed to register wm8985 SPI driver: %d\n",
1173                        ret);
1174         }
1175 #endif
1176         return ret;
1177 }
1178 module_init(wm8985_modinit);
1179
1180 static void __exit wm8985_exit(void)
1181 {
1182 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1183         i2c_del_driver(&wm8985_i2c_driver);
1184 #endif
1185 #if defined(CONFIG_SPI_MASTER)
1186         spi_unregister_driver(&wm8985_spi_driver);
1187 #endif
1188 }
1189 module_exit(wm8985_exit);
1190
1191 MODULE_DESCRIPTION("ASoC WM8985 driver");
1192 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1193 MODULE_LICENSE("GPL");