2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33, aic3007.
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/platform_device.h>
44 #include <linux/slab.h>
45 #include <sound/core.h>
46 #include <sound/pcm.h>
47 #include <sound/pcm_params.h>
48 #include <sound/soc.h>
49 #include <sound/soc-dapm.h>
50 #include <sound/initval.h>
51 #include <sound/tlv.h>
52 #include <sound/tlv320aic3x.h>
54 #include "tlv320aic3x.h"
56 #define AIC3X_NUM_SUPPLIES 4
57 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
64 /* codec private data */
66 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
67 enum snd_soc_control_type control_type;
68 struct aic3x_setup_data *setup;
73 #define AIC3X_MODEL_3X 0
74 #define AIC3X_MODEL_33 1
75 #define AIC3X_MODEL_3007 2
80 * AIC3X register cache
81 * We can't read the AIC3X register space when we are
82 * using 2 wire for device control, so we cache them instead.
83 * There is no point in caching the reset register
85 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
86 0x00, 0x00, 0x00, 0x10, /* 0 */
87 0x04, 0x00, 0x00, 0x00, /* 4 */
88 0x00, 0x00, 0x00, 0x01, /* 8 */
89 0x00, 0x00, 0x00, 0x80, /* 12 */
90 0x80, 0xff, 0xff, 0x78, /* 16 */
91 0x78, 0x78, 0x78, 0x78, /* 20 */
92 0x78, 0x00, 0x00, 0xfe, /* 24 */
93 0x00, 0x00, 0xfe, 0x00, /* 28 */
94 0x18, 0x18, 0x00, 0x00, /* 32 */
95 0x00, 0x00, 0x00, 0x00, /* 36 */
96 0x00, 0x00, 0x00, 0x80, /* 40 */
97 0x80, 0x00, 0x00, 0x00, /* 44 */
98 0x00, 0x00, 0x00, 0x04, /* 48 */
99 0x00, 0x00, 0x00, 0x00, /* 52 */
100 0x00, 0x00, 0x04, 0x00, /* 56 */
101 0x00, 0x00, 0x00, 0x00, /* 60 */
102 0x00, 0x04, 0x00, 0x00, /* 64 */
103 0x00, 0x00, 0x00, 0x00, /* 68 */
104 0x04, 0x00, 0x00, 0x00, /* 72 */
105 0x00, 0x00, 0x00, 0x00, /* 76 */
106 0x00, 0x00, 0x00, 0x00, /* 80 */
107 0x00, 0x00, 0x00, 0x00, /* 84 */
108 0x00, 0x00, 0x00, 0x00, /* 88 */
109 0x00, 0x00, 0x00, 0x00, /* 92 */
110 0x00, 0x00, 0x00, 0x00, /* 96 */
111 0x00, 0x00, 0x02, /* 100 */
115 * read aic3x register cache
117 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
120 u8 *cache = codec->reg_cache;
121 if (reg >= AIC3X_CACHEREGNUM)
127 * write aic3x register cache
129 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
132 u8 *cache = codec->reg_cache;
133 if (reg >= AIC3X_CACHEREGNUM)
139 * write to the aic3x register space
141 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
147 * D15..D8 aic3x register offset
148 * D7...D0 register data
150 data[0] = reg & 0xff;
151 data[1] = value & 0xff;
153 aic3x_write_reg_cache(codec, data[0], data[1]);
154 if (codec->hw_write(codec->control_data, data, 2) == 2)
161 * read from the aic3x register space
163 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
168 value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]);
170 aic3x_write_reg_cache(codec, reg, *value);
174 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
175 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
176 .info = snd_soc_info_volsw, \
177 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
178 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
181 * All input lines are connected when !0xf and disconnected with 0xf bit field,
182 * so we have to use specific dapm_put call for input mixer
184 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
185 struct snd_ctl_elem_value *ucontrol)
187 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
188 struct soc_mixer_control *mc =
189 (struct soc_mixer_control *)kcontrol->private_value;
190 unsigned int reg = mc->reg;
191 unsigned int shift = mc->shift;
193 unsigned int mask = (1 << fls(max)) - 1;
194 unsigned int invert = mc->invert;
195 unsigned short val, val_mask;
197 struct snd_soc_dapm_path *path;
200 val = (ucontrol->value.integer.value[0] & mask);
208 val_mask = mask << shift;
211 mutex_lock(&widget->codec->mutex);
213 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
214 /* find dapm widget path assoc with kcontrol */
215 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
216 if (path->kcontrol != kcontrol)
219 /* found, now check type */
223 path->connect = invert ? 0 : 1;
225 /* old connection must be powered down */
226 path->connect = invert ? 1 : 0;
231 snd_soc_dapm_sync(widget->codec);
234 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
236 mutex_unlock(&widget->codec->mutex);
240 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
241 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
242 static const char *aic3x_left_hpcom_mux[] =
243 { "differential of HPLOUT", "constant VCM", "single-ended" };
244 static const char *aic3x_right_hpcom_mux[] =
245 { "differential of HPROUT", "constant VCM", "single-ended",
246 "differential of HPLCOM", "external feedback" };
247 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
248 static const char *aic3x_adc_hpf[] =
249 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
253 #define LHPCOM_ENUM 2
254 #define RHPCOM_ENUM 3
255 #define LINE1L_ENUM 4
256 #define LINE1R_ENUM 5
257 #define LINE2L_ENUM 6
258 #define LINE2R_ENUM 7
259 #define ADC_HPF_ENUM 8
261 static const struct soc_enum aic3x_enum[] = {
262 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
263 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
264 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
265 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
266 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
267 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
268 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
269 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
270 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
274 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
276 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
277 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
278 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
280 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
281 * Step size is approximately 0.5 dB over most of the scale but increasing
282 * near the very low levels.
283 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
284 * but having increasing dB difference below that (and where it doesn't count
285 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
286 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
288 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
290 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
292 SOC_DOUBLE_R_TLV("PCM Playback Volume",
293 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
295 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
296 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
297 0, 118, 1, output_stage_tlv),
298 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0),
299 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0),
300 SOC_DOUBLE_R_TLV("LineL DAC Playback Volume",
301 DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL,
302 0, 118, 1, output_stage_tlv),
303 SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume",
304 PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
305 SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume",
306 PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
307 SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume",
308 LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL,
309 0, 118, 1, output_stage_tlv),
310 SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume",
311 LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL,
312 0, 118, 1, output_stage_tlv),
314 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
315 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
316 0, 118, 1, output_stage_tlv),
317 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
318 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
319 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
320 0, 118, 1, output_stage_tlv),
321 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
322 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
323 0, 118, 1, output_stage_tlv),
325 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
326 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
327 0, 118, 1, output_stage_tlv),
328 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
330 SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume",
331 PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
332 0, 118, 1, output_stage_tlv),
333 SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume",
334 PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
335 SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume",
336 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
337 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
338 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
339 0, 118, 1, output_stage_tlv),
341 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
342 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
343 0, 118, 1, output_stage_tlv),
344 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
346 SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume",
347 PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
348 SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume",
349 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
350 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
351 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
352 0, 118, 1, output_stage_tlv),
355 * Note: enable Automatic input Gain Controller with care. It can
356 * adjust PGA to max value when ADC is on and will never go back.
358 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
361 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
363 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
365 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
369 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
371 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
373 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
374 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
377 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
378 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
381 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
382 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
385 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
386 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
388 /* Right HPCOM Mux */
389 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
390 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
392 /* Left DAC_L1 Mixer */
393 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
394 SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
395 SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
396 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
397 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
398 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
401 /* Right DAC_R1 Mixer */
402 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
403 SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
404 SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
405 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
406 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
407 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
411 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
412 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
413 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
414 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
415 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
416 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
419 /* Right PGA Mixer */
420 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
421 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
422 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
423 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
424 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
425 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
429 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
430 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
432 /* Right Line1 Mux */
433 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
434 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
437 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
438 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
440 /* Right Line2 Mux */
441 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
442 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
444 /* Left PGA Bypass Mixer */
445 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
446 SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
448 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
449 SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
450 SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
451 SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
452 SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
455 /* Right PGA Bypass Mixer */
456 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
457 SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
459 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
460 SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
461 SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
462 SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
463 SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
466 /* Left Line2 Bypass Mixer */
467 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
468 SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
469 SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
470 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
471 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
472 SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
475 /* Right Line2 Bypass Mixer */
476 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
477 SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
478 SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
479 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
480 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
481 SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
484 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
485 /* Left DAC to Left Outputs */
486 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
487 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
488 &aic3x_left_dac_mux_controls),
489 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
490 &aic3x_left_dac_mixer_controls[0],
491 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
492 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
493 &aic3x_left_hpcom_mux_controls),
494 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
495 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
496 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
498 /* Right DAC to Right Outputs */
499 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
500 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
501 &aic3x_right_dac_mux_controls),
502 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
503 &aic3x_right_dac_mixer_controls[0],
504 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
505 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
506 &aic3x_right_hpcom_mux_controls),
507 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
508 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
509 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
512 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
514 /* Inputs to Left ADC */
515 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
516 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
517 &aic3x_left_pga_mixer_controls[0],
518 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
519 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
520 &aic3x_left_line1_mux_controls),
521 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
522 &aic3x_left_line1_mux_controls),
523 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
524 &aic3x_left_line2_mux_controls),
526 /* Inputs to Right ADC */
527 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
528 LINE1R_2_RADC_CTRL, 2, 0),
529 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
530 &aic3x_right_pga_mixer_controls[0],
531 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
532 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
533 &aic3x_right_line1_mux_controls),
534 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
535 &aic3x_right_line1_mux_controls),
536 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
537 &aic3x_right_line2_mux_controls),
540 * Not a real mic bias widget but similar function. This is for dynamic
541 * control of GPIO1 digital mic modulator clock output function when
544 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
545 AIC3X_GPIO1_REG, 4, 0xf,
546 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
547 AIC3X_GPIO1_FUNC_DISABLED),
550 * Also similar function like mic bias. Selects digital mic with
551 * configurable oversampling rate instead of ADC converter.
553 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
554 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
555 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
556 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
557 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
558 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
561 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
562 MICBIAS_CTRL, 6, 3, 1, 0),
563 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
564 MICBIAS_CTRL, 6, 3, 2, 0),
565 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
566 MICBIAS_CTRL, 6, 3, 3, 0),
568 /* Left PGA to Left Output bypass */
569 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
570 &aic3x_left_pga_bp_mixer_controls[0],
571 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
573 /* Right PGA to Right Output bypass */
574 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
575 &aic3x_right_pga_bp_mixer_controls[0],
576 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
578 /* Left Line2 to Left Output bypass */
579 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
580 &aic3x_left_line2_bp_mixer_controls[0],
581 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
583 /* Right Line2 to Right Output bypass */
584 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
585 &aic3x_right_line2_bp_mixer_controls[0],
586 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
588 SND_SOC_DAPM_OUTPUT("LLOUT"),
589 SND_SOC_DAPM_OUTPUT("RLOUT"),
590 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
591 SND_SOC_DAPM_OUTPUT("HPLOUT"),
592 SND_SOC_DAPM_OUTPUT("HPROUT"),
593 SND_SOC_DAPM_OUTPUT("HPLCOM"),
594 SND_SOC_DAPM_OUTPUT("HPRCOM"),
596 SND_SOC_DAPM_INPUT("MIC3L"),
597 SND_SOC_DAPM_INPUT("MIC3R"),
598 SND_SOC_DAPM_INPUT("LINE1L"),
599 SND_SOC_DAPM_INPUT("LINE1R"),
600 SND_SOC_DAPM_INPUT("LINE2L"),
601 SND_SOC_DAPM_INPUT("LINE2R"),
604 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
605 /* Class-D outputs */
606 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
607 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
609 SND_SOC_DAPM_OUTPUT("SPOP"),
610 SND_SOC_DAPM_OUTPUT("SPOM"),
613 static const struct snd_soc_dapm_route intercon[] = {
615 {"Left DAC Mux", "DAC_L1", "Left DAC"},
616 {"Left DAC Mux", "DAC_L2", "Left DAC"},
617 {"Left DAC Mux", "DAC_L3", "Left DAC"},
619 {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
620 {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
621 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
622 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
623 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
624 {"Left Line Out", NULL, "Left DAC Mux"},
625 {"Left HP Out", NULL, "Left DAC Mux"},
627 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
628 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
629 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
631 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
632 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
633 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
634 {"Left HP Com", NULL, "Left HPCOM Mux"},
636 {"LLOUT", NULL, "Left Line Out"},
637 {"LLOUT", NULL, "Left Line Out"},
638 {"HPLOUT", NULL, "Left HP Out"},
639 {"HPLCOM", NULL, "Left HP Com"},
642 {"Right DAC Mux", "DAC_R1", "Right DAC"},
643 {"Right DAC Mux", "DAC_R2", "Right DAC"},
644 {"Right DAC Mux", "DAC_R3", "Right DAC"},
646 {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
647 {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
648 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
649 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
650 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
651 {"Right Line Out", NULL, "Right DAC Mux"},
652 {"Right HP Out", NULL, "Right DAC Mux"},
654 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
655 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
656 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
657 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
658 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
660 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
661 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
662 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
663 {"Right HP Com", NULL, "Right HPCOM Mux"},
665 {"RLOUT", NULL, "Right Line Out"},
666 {"RLOUT", NULL, "Right Line Out"},
667 {"HPROUT", NULL, "Right HP Out"},
668 {"HPRCOM", NULL, "Right HP Com"},
671 {"MONO_LOUT", NULL, "Mono Out"},
672 {"MONO_LOUT", NULL, "Mono Out"},
675 {"Left Line1L Mux", "single-ended", "LINE1L"},
676 {"Left Line1L Mux", "differential", "LINE1L"},
678 {"Left Line2L Mux", "single-ended", "LINE2L"},
679 {"Left Line2L Mux", "differential", "LINE2L"},
681 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
682 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
683 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
684 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
685 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
687 {"Left ADC", NULL, "Left PGA Mixer"},
688 {"Left ADC", NULL, "GPIO1 dmic modclk"},
691 {"Right Line1R Mux", "single-ended", "LINE1R"},
692 {"Right Line1R Mux", "differential", "LINE1R"},
694 {"Right Line2R Mux", "single-ended", "LINE2R"},
695 {"Right Line2R Mux", "differential", "LINE2R"},
697 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
698 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
699 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
700 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
701 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
703 {"Right ADC", NULL, "Right PGA Mixer"},
704 {"Right ADC", NULL, "GPIO1 dmic modclk"},
706 /* Left PGA Bypass */
707 {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
708 {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
709 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
710 {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
711 {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
712 {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
713 {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
715 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
716 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
717 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
719 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
720 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
721 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
723 /* Right PGA Bypass */
724 {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
725 {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
726 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
727 {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
728 {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
729 {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
730 {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
732 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
733 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
734 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
735 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
736 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
738 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
739 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
740 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
742 /* Left Line2 Bypass */
743 {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
744 {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
745 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
746 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
747 {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
749 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
750 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
751 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
753 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
754 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
755 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
757 /* Right Line2 Bypass */
758 {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
759 {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
760 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
761 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
762 {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
764 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
765 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
766 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
767 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
768 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
770 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
771 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
772 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
775 * Logical path between digital mic enable and GPIO1 modulator clock
778 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
779 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
780 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
783 static const struct snd_soc_dapm_route intercon_3007[] = {
784 /* Class-D outputs */
785 {"Left Class-D Out", NULL, "Left Line Out"},
786 {"Right Class-D Out", NULL, "Left Line Out"},
787 {"SPOP", NULL, "Left Class-D Out"},
788 {"SPOM", NULL, "Right Class-D Out"},
791 static int aic3x_add_widgets(struct snd_soc_codec *codec)
793 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
795 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
796 ARRAY_SIZE(aic3x_dapm_widgets));
798 /* set up audio path interconnects */
799 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
801 if (aic3x->model == AIC3X_MODEL_3007) {
802 snd_soc_dapm_new_controls(codec, aic3007_dapm_widgets,
803 ARRAY_SIZE(aic3007_dapm_widgets));
804 snd_soc_dapm_add_routes(codec, intercon_3007, ARRAY_SIZE(intercon_3007));
810 static int aic3x_hw_params(struct snd_pcm_substream *substream,
811 struct snd_pcm_hw_params *params,
812 struct snd_soc_dai *dai)
814 struct snd_soc_pcm_runtime *rtd = substream->private_data;
815 struct snd_soc_codec *codec =rtd->codec;
816 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
817 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
818 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
823 /* select data word length */
825 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
826 switch (params_format(params)) {
827 case SNDRV_PCM_FORMAT_S16_LE:
829 case SNDRV_PCM_FORMAT_S20_3LE:
832 case SNDRV_PCM_FORMAT_S24_LE:
835 case SNDRV_PCM_FORMAT_S32_LE:
839 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
841 /* Fsref can be 44100 or 48000 */
842 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
844 /* Try to find a value for Q which allows us to bypass the PLL and
845 * generate CODEC_CLK directly. */
846 for (pll_q = 2; pll_q < 18; pll_q++)
847 if (aic3x->sysclk / (128 * pll_q) == fsref) {
854 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
855 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
856 /* disable PLL if it is bypassed */
857 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
858 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
861 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
862 /* enable PLL when it is used */
863 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
864 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
867 /* Route Left DAC to left channel input and
868 * right DAC to right channel input */
869 data = (LDAC2LCH | RDAC2RCH);
870 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
871 if (params_rate(params) >= 64000)
872 data |= DUAL_RATE_MODE;
873 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
875 /* codec sample rate select */
876 data = (fsref * 20) / params_rate(params);
877 if (params_rate(params) < 64000)
882 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
887 /* Use PLL, compute apropriate setup for j, d, r and p, the closest
888 * one wins the game. Try with d==0 first, next with d!=0.
889 * Constraints for j are according to the datasheet.
890 * The sysclk is divided by 1000 to prevent integer overflows.
893 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
895 for (r = 1; r <= 16; r++)
896 for (p = 1; p <= 8; p++) {
897 for (j = 4; j <= 55; j++) {
898 /* This is actually 1000*((j+(d/10000))*r)/p
899 * The term had to be converted to get
900 * rid of the division by 10000; d = 0 here
902 int tmp_clk = (1000 * j * r) / p;
904 /* Check whether this values get closer than
905 * the best ones we had before
907 if (abs(codec_clk - tmp_clk) <
908 abs(codec_clk - last_clk)) {
909 pll_j = j; pll_d = 0;
910 pll_r = r; pll_p = p;
914 /* Early exit for exact matches */
915 if (tmp_clk == codec_clk)
920 /* try with d != 0 */
921 for (p = 1; p <= 8; p++) {
922 j = codec_clk * p / 1000;
927 /* do not use codec_clk here since we'd loose precision */
928 d = ((2048 * p * fsref) - j * aic3x->sysclk)
929 * 100 / (aic3x->sysclk/100);
931 clk = (10000 * j + d) / (10 * p);
933 /* check whether this values get closer than the best
934 * ones we had before */
935 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
936 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
940 /* Early exit for exact matches */
941 if (clk == codec_clk)
946 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
951 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
952 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
953 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
954 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
955 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
956 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
957 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
962 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
964 struct snd_soc_codec *codec = dai->codec;
965 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
966 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
969 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
970 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
972 aic3x_write(codec, LDAC_VOL, ldac_reg);
973 aic3x_write(codec, RDAC_VOL, rdac_reg);
979 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
980 int clk_id, unsigned int freq, int dir)
982 struct snd_soc_codec *codec = codec_dai->codec;
983 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
985 aic3x->sysclk = freq;
989 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
992 struct snd_soc_codec *codec = codec_dai->codec;
993 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
994 u8 iface_areg, iface_breg;
997 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
998 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1000 /* set master/slave audio interface */
1001 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1002 case SND_SOC_DAIFMT_CBM_CFM:
1004 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1006 case SND_SOC_DAIFMT_CBS_CFS:
1014 * match both interface format and signal polarities since they
1017 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1018 SND_SOC_DAIFMT_INV_MASK)) {
1019 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1021 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1023 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1024 iface_breg |= (0x01 << 6);
1026 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1027 iface_breg |= (0x02 << 6);
1029 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1030 iface_breg |= (0x03 << 6);
1037 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1038 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1039 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1044 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1045 enum snd_soc_bias_level level)
1047 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1051 case SND_SOC_BIAS_ON:
1053 case SND_SOC_BIAS_PREPARE:
1054 if (aic3x->master) {
1056 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1057 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1061 case SND_SOC_BIAS_STANDBY:
1062 /* fall through and disable pll */
1063 case SND_SOC_BIAS_OFF:
1064 if (aic3x->master) {
1066 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1067 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1072 codec->bias_level = level;
1077 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1079 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1080 u8 bit = gpio ? 3: 0;
1081 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1082 aic3x_write(codec, reg, val | (!!state << bit));
1084 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1086 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1088 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1089 u8 val, bit = gpio ? 2: 1;
1091 aic3x_read(codec, reg, &val);
1092 return (val >> bit) & 1;
1094 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1096 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1097 int headset_debounce, int button_debounce)
1101 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1102 << AIC3X_HEADSET_DETECT_SHIFT) |
1103 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1104 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1105 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1106 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1108 if (detect & AIC3X_HEADSET_DETECT_MASK)
1109 val |= AIC3X_HEADSET_DETECT_ENABLED;
1111 aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1113 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1115 int aic3x_headset_detected(struct snd_soc_codec *codec)
1118 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1119 return (val >> 4) & 1;
1121 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1123 int aic3x_button_pressed(struct snd_soc_codec *codec)
1126 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1127 return (val >> 5) & 1;
1129 EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1131 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1132 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1133 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1135 static struct snd_soc_dai_ops aic3x_dai_ops = {
1136 .hw_params = aic3x_hw_params,
1137 .digital_mute = aic3x_mute,
1138 .set_sysclk = aic3x_set_dai_sysclk,
1139 .set_fmt = aic3x_set_dai_fmt,
1142 static struct snd_soc_dai_driver aic3x_dai = {
1143 .name = "tlv320aic3x-hifi",
1145 .stream_name = "Playback",
1148 .rates = AIC3X_RATES,
1149 .formats = AIC3X_FORMATS,},
1151 .stream_name = "Capture",
1154 .rates = AIC3X_RATES,
1155 .formats = AIC3X_FORMATS,},
1156 .ops = &aic3x_dai_ops,
1157 .symmetric_rates = 1,
1160 static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
1162 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1167 static int aic3x_resume(struct snd_soc_codec *codec)
1171 u8 *cache = codec->reg_cache;
1173 /* Sync reg_cache with the hardware */
1174 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1177 codec->hw_write(codec->control_data, data, 2);
1180 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1186 * initialise the AIC3X driver
1187 * register the mixer and dsp interfaces with the kernel
1189 static int aic3x_init(struct snd_soc_codec *codec)
1191 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1194 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1195 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1197 /* DAC default volume and mute */
1198 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1199 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1201 /* DAC to HP default volume and route to Output mixer */
1202 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1203 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1204 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1205 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1206 /* DAC to Line Out default volume and route to Output mixer */
1207 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1208 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1209 /* DAC to Mono Line Out default volume and route to Output mixer */
1210 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1211 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1213 /* unmute all outputs */
1214 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1215 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1216 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1217 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1218 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1219 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1220 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1221 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1222 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1223 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1224 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1225 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1226 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1227 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1229 /* ADC default volume and unmute */
1230 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1231 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1232 /* By default route Line1 to ADC PGA mixer */
1233 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1234 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1236 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1237 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1238 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1239 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1240 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1241 /* PGA to Line Out default volume, disconnect from Output Mixer */
1242 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1243 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1244 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1245 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1246 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1248 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1249 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1250 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1251 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1252 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1253 /* Line2 Line Out default volume, disconnect from Output Mixer */
1254 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1255 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1256 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1257 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1258 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1260 if (aic3x->model == AIC3X_MODEL_3007) {
1261 /* Class-D speaker driver init; datasheet p. 46 */
1262 aic3x_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1263 aic3x_write(codec, 0xD, 0x0D);
1264 aic3x_write(codec, 0x8, 0x5C);
1265 aic3x_write(codec, 0x8, 0x5D);
1266 aic3x_write(codec, 0x8, 0x5C);
1267 aic3x_write(codec, AIC3X_PAGE_SELECT, 0x00);
1268 aic3x_write(codec, CLASSD_CTRL, 0);
1271 /* off, with power on */
1272 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1277 static int aic3x_probe(struct snd_soc_codec *codec)
1279 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1281 codec->hw_write = (hw_write_t) i2c_master_send;
1282 codec->control_data = aic3x->control_data;
1287 /* setup GPIO functions */
1288 aic3x_write(codec, AIC3X_GPIO1_REG,
1289 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1290 aic3x_write(codec, AIC3X_GPIO2_REG,
1291 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1294 snd_soc_add_controls(codec, aic3x_snd_controls,
1295 ARRAY_SIZE(aic3x_snd_controls));
1296 if (aic3x->model == AIC3X_MODEL_3007)
1297 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
1299 aic3x_add_widgets(codec);
1304 static int aic3x_remove(struct snd_soc_codec *codec)
1306 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1310 static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1311 .read = aic3x_read_reg_cache,
1312 .write = aic3x_write,
1313 .set_bias_level = aic3x_set_bias_level,
1314 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1315 .reg_word_size = sizeof(u8),
1316 .reg_cache_default = aic3x_reg,
1317 .probe = aic3x_probe,
1318 .remove = aic3x_remove,
1319 .suspend = aic3x_suspend,
1320 .resume = aic3x_resume,
1323 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1325 * AIC3X 2 wire address can be up to 4 devices with device addresses
1326 * 0x18, 0x19, 0x1A, 0x1B
1329 static const struct i2c_device_id aic3x_i2c_id[] = {
1330 [AIC3X_MODEL_3X] = { "tlv320aic3x", 0 },
1331 [AIC3X_MODEL_33] = { "tlv320aic33", 0 },
1332 [AIC3X_MODEL_3007] = { "tlv320aic3007", 0 },
1335 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1338 * If the i2c layer weren't so broken, we could pass this kind of data
1341 static int aic3x_i2c_probe(struct i2c_client *i2c,
1342 const struct i2c_device_id *id)
1344 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1345 struct aic3x_setup_data *setup = pdata->setup;
1346 struct aic3x_priv *aic3x;
1348 const struct i2c_device_id *tbl;
1350 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1351 if (aic3x == NULL) {
1352 dev_err(&i2c->dev, "failed to create private data\n");
1356 aic3x->control_data = i2c;
1357 aic3x->setup = setup;
1358 i2c_set_clientdata(i2c, aic3x);
1360 aic3x->gpio_reset = -1;
1361 if (pdata && pdata->gpio_reset >= 0) {
1362 ret = gpio_request(pdata->gpio_reset, "tlv320aic3x reset");
1365 aic3x->gpio_reset = pdata->gpio_reset;
1366 gpio_direction_output(aic3x->gpio_reset, 0);
1369 for (tbl = aic3x_i2c_id; tbl->name[0]; tbl++) {
1370 if (!strcmp(tbl->name, id->name))
1373 aic3x->model = tbl - aic3x_i2c_id;
1375 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1376 aic3x->supplies[i].supply = aic3x_supply_names[i];
1378 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1381 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1385 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1388 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
1392 if (aic3x->gpio_reset >= 0) {
1394 gpio_set_value(aic3x->gpio_reset, 1);
1397 ret = snd_soc_register_codec(&i2c->dev,
1398 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1404 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1406 if (aic3x->gpio_reset >= 0)
1407 gpio_free(aic3x->gpio_reset);
1413 static int aic3x_i2c_remove(struct i2c_client *client)
1415 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1417 if (aic3x->gpio_reset >= 0) {
1418 gpio_set_value(aic3x->gpio_reset, 0);
1419 gpio_free(aic3x->gpio_reset);
1421 regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1422 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1424 snd_soc_unregister_codec(&client->dev);
1425 kfree(i2c_get_clientdata(client));
1429 /* machine i2c codec control layer */
1430 static struct i2c_driver aic3x_i2c_driver = {
1432 .name = "tlv320aic3x-codec",
1433 .owner = THIS_MODULE,
1435 .probe = aic3x_i2c_probe,
1436 .remove = aic3x_i2c_remove,
1437 .id_table = aic3x_i2c_id,
1440 static inline void aic3x_i2c_init(void)
1444 ret = i2c_add_driver(&aic3x_i2c_driver);
1446 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
1450 static inline void aic3x_i2c_exit(void)
1452 i2c_del_driver(&aic3x_i2c_driver);
1456 static int __init aic3x_modinit(void)
1459 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1460 ret = i2c_add_driver(&aic3x_i2c_driver);
1462 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1468 module_init(aic3x_modinit);
1470 static void __exit aic3x_exit(void)
1472 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1473 i2c_del_driver(&aic3x_i2c_driver);
1476 module_exit(aic3x_exit);
1478 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1479 MODULE_AUTHOR("Vladimir Barinov");
1480 MODULE_LICENSE("GPL");