2 * DA9055 ALSA Soc codec driver
4 * Copyright (c) 2012 Dialog Semiconductor
6 * Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C
7 * Written by David Chen <david.chen@diasemi.com> and
8 * Ashish Chavan <ashish.chavan@kpitcummins.com>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc.h>
24 #include <sound/initval.h>
25 #include <sound/tlv.h>
26 #include <sound/da9055.h>
28 /* DA9055 register space */
30 /* Status Registers */
31 #define DA9055_STATUS1 0x02
32 #define DA9055_PLL_STATUS 0x03
33 #define DA9055_AUX_L_GAIN_STATUS 0x04
34 #define DA9055_AUX_R_GAIN_STATUS 0x05
35 #define DA9055_MIC_L_GAIN_STATUS 0x06
36 #define DA9055_MIC_R_GAIN_STATUS 0x07
37 #define DA9055_MIXIN_L_GAIN_STATUS 0x08
38 #define DA9055_MIXIN_R_GAIN_STATUS 0x09
39 #define DA9055_ADC_L_GAIN_STATUS 0x0A
40 #define DA9055_ADC_R_GAIN_STATUS 0x0B
41 #define DA9055_DAC_L_GAIN_STATUS 0x0C
42 #define DA9055_DAC_R_GAIN_STATUS 0x0D
43 #define DA9055_HP_L_GAIN_STATUS 0x0E
44 #define DA9055_HP_R_GAIN_STATUS 0x0F
45 #define DA9055_LINE_GAIN_STATUS 0x10
47 /* System Initialisation Registers */
48 #define DA9055_CIF_CTRL 0x20
49 #define DA9055_DIG_ROUTING_AIF 0X21
50 #define DA9055_SR 0x22
51 #define DA9055_REFERENCES 0x23
52 #define DA9055_PLL_FRAC_TOP 0x24
53 #define DA9055_PLL_FRAC_BOT 0x25
54 #define DA9055_PLL_INTEGER 0x26
55 #define DA9055_PLL_CTRL 0x27
56 #define DA9055_AIF_CLK_MODE 0x28
57 #define DA9055_AIF_CTRL 0x29
58 #define DA9055_DIG_ROUTING_DAC 0x2A
59 #define DA9055_ALC_CTRL1 0x2B
61 /* Input - Gain, Select and Filter Registers */
62 #define DA9055_AUX_L_GAIN 0x30
63 #define DA9055_AUX_R_GAIN 0x31
64 #define DA9055_MIXIN_L_SELECT 0x32
65 #define DA9055_MIXIN_R_SELECT 0x33
66 #define DA9055_MIXIN_L_GAIN 0x34
67 #define DA9055_MIXIN_R_GAIN 0x35
68 #define DA9055_ADC_L_GAIN 0x36
69 #define DA9055_ADC_R_GAIN 0x37
70 #define DA9055_ADC_FILTERS1 0x38
71 #define DA9055_MIC_L_GAIN 0x39
72 #define DA9055_MIC_R_GAIN 0x3A
74 /* Output - Gain, Select and Filter Registers */
75 #define DA9055_DAC_FILTERS5 0x40
76 #define DA9055_DAC_FILTERS2 0x41
77 #define DA9055_DAC_FILTERS3 0x42
78 #define DA9055_DAC_FILTERS4 0x43
79 #define DA9055_DAC_FILTERS1 0x44
80 #define DA9055_DAC_L_GAIN 0x45
81 #define DA9055_DAC_R_GAIN 0x46
82 #define DA9055_CP_CTRL 0x47
83 #define DA9055_HP_L_GAIN 0x48
84 #define DA9055_HP_R_GAIN 0x49
85 #define DA9055_LINE_GAIN 0x4A
86 #define DA9055_MIXOUT_L_SELECT 0x4B
87 #define DA9055_MIXOUT_R_SELECT 0x4C
89 /* System Controller Registers */
90 #define DA9055_SYSTEM_MODES_INPUT 0x50
91 #define DA9055_SYSTEM_MODES_OUTPUT 0x51
93 /* Control Registers */
94 #define DA9055_AUX_L_CTRL 0x60
95 #define DA9055_AUX_R_CTRL 0x61
96 #define DA9055_MIC_BIAS_CTRL 0x62
97 #define DA9055_MIC_L_CTRL 0x63
98 #define DA9055_MIC_R_CTRL 0x64
99 #define DA9055_MIXIN_L_CTRL 0x65
100 #define DA9055_MIXIN_R_CTRL 0x66
101 #define DA9055_ADC_L_CTRL 0x67
102 #define DA9055_ADC_R_CTRL 0x68
103 #define DA9055_DAC_L_CTRL 0x69
104 #define DA9055_DAC_R_CTRL 0x6A
105 #define DA9055_HP_L_CTRL 0x6B
106 #define DA9055_HP_R_CTRL 0x6C
107 #define DA9055_LINE_CTRL 0x6D
108 #define DA9055_MIXOUT_L_CTRL 0x6E
109 #define DA9055_MIXOUT_R_CTRL 0x6F
111 /* Configuration Registers */
112 #define DA9055_LDO_CTRL 0x90
113 #define DA9055_IO_CTRL 0x91
114 #define DA9055_GAIN_RAMP_CTRL 0x92
115 #define DA9055_MIC_CONFIG 0x93
116 #define DA9055_PC_COUNT 0x94
117 #define DA9055_CP_VOL_THRESHOLD1 0x95
118 #define DA9055_CP_DELAY 0x96
119 #define DA9055_CP_DETECTOR 0x97
120 #define DA9055_AIF_OFFSET 0x98
121 #define DA9055_DIG_CTRL 0x99
122 #define DA9055_ALC_CTRL2 0x9A
123 #define DA9055_ALC_CTRL3 0x9B
124 #define DA9055_ALC_NOISE 0x9C
125 #define DA9055_ALC_TARGET_MIN 0x9D
126 #define DA9055_ALC_TARGET_MAX 0x9E
127 #define DA9055_ALC_GAIN_LIMITS 0x9F
128 #define DA9055_ALC_ANA_GAIN_LIMITS 0xA0
129 #define DA9055_ALC_ANTICLIP_CTRL 0xA1
130 #define DA9055_ALC_ANTICLIP_LEVEL 0xA2
131 #define DA9055_ALC_OFFSET_OP2M_L 0xA6
132 #define DA9055_ALC_OFFSET_OP2U_L 0xA7
133 #define DA9055_ALC_OFFSET_OP2M_R 0xAB
134 #define DA9055_ALC_OFFSET_OP2U_R 0xAC
135 #define DA9055_ALC_CIC_OP_LVL_CTRL 0xAD
136 #define DA9055_ALC_CIC_OP_LVL_DATA 0xAE
137 #define DA9055_DAC_NG_SETUP_TIME 0xAF
138 #define DA9055_DAC_NG_OFF_THRESHOLD 0xB0
139 #define DA9055_DAC_NG_ON_THRESHOLD 0xB1
140 #define DA9055_DAC_NG_CTRL 0xB2
143 #define DA9055_SR_8000 (0x1 << 0)
144 #define DA9055_SR_11025 (0x2 << 0)
145 #define DA9055_SR_12000 (0x3 << 0)
146 #define DA9055_SR_16000 (0x5 << 0)
147 #define DA9055_SR_22050 (0x6 << 0)
148 #define DA9055_SR_24000 (0x7 << 0)
149 #define DA9055_SR_32000 (0x9 << 0)
150 #define DA9055_SR_44100 (0xA << 0)
151 #define DA9055_SR_48000 (0xB << 0)
152 #define DA9055_SR_88200 (0xE << 0)
153 #define DA9055_SR_96000 (0xF << 0)
155 /* REFERENCES bit fields */
156 #define DA9055_BIAS_EN (1 << 3)
157 #define DA9055_VMID_EN (1 << 7)
159 /* PLL_CTRL bit fields */
160 #define DA9055_PLL_INDIV_10_20_MHZ (1 << 2)
161 #define DA9055_PLL_SRM_EN (1 << 6)
162 #define DA9055_PLL_EN (1 << 7)
164 /* AIF_CLK_MODE bit fields */
165 #define DA9055_AIF_BCLKS_PER_WCLK_32 (0 << 0)
166 #define DA9055_AIF_BCLKS_PER_WCLK_64 (1 << 0)
167 #define DA9055_AIF_BCLKS_PER_WCLK_128 (2 << 0)
168 #define DA9055_AIF_BCLKS_PER_WCLK_256 (3 << 0)
169 #define DA9055_AIF_CLK_EN_SLAVE_MODE (0 << 7)
170 #define DA9055_AIF_CLK_EN_MASTER_MODE (1 << 7)
172 /* AIF_CTRL bit fields */
173 #define DA9055_AIF_FORMAT_I2S_MODE (0 << 0)
174 #define DA9055_AIF_FORMAT_LEFT_J (1 << 0)
175 #define DA9055_AIF_FORMAT_RIGHT_J (2 << 0)
176 #define DA9055_AIF_WORD_S16_LE (0 << 2)
177 #define DA9055_AIF_WORD_S20_3LE (1 << 2)
178 #define DA9055_AIF_WORD_S24_LE (2 << 2)
179 #define DA9055_AIF_WORD_S32_LE (3 << 2)
181 /* MIC_L_CTRL bit fields */
182 #define DA9055_MIC_L_MUTE_EN (1 << 6)
184 /* MIC_R_CTRL bit fields */
185 #define DA9055_MIC_R_MUTE_EN (1 << 6)
187 /* MIXIN_L_CTRL bit fields */
188 #define DA9055_MIXIN_L_MIX_EN (1 << 3)
190 /* MIXIN_R_CTRL bit fields */
191 #define DA9055_MIXIN_R_MIX_EN (1 << 3)
193 /* ADC_L_CTRL bit fields */
194 #define DA9055_ADC_L_EN (1 << 7)
196 /* ADC_R_CTRL bit fields */
197 #define DA9055_ADC_R_EN (1 << 7)
199 /* DAC_L_CTRL bit fields */
200 #define DA9055_DAC_L_MUTE_EN (1 << 6)
202 /* DAC_R_CTRL bit fields */
203 #define DA9055_DAC_R_MUTE_EN (1 << 6)
205 /* HP_L_CTRL bit fields */
206 #define DA9055_HP_L_AMP_OE (1 << 3)
208 /* HP_R_CTRL bit fields */
209 #define DA9055_HP_R_AMP_OE (1 << 3)
211 /* LINE_CTRL bit fields */
212 #define DA9055_LINE_AMP_OE (1 << 3)
214 /* MIXOUT_L_CTRL bit fields */
215 #define DA9055_MIXOUT_L_MIX_EN (1 << 3)
217 /* MIXOUT_R_CTRL bit fields */
218 #define DA9055_MIXOUT_R_MIX_EN (1 << 3)
220 /* MIC bias select bit fields */
221 #define DA9055_MICBIAS2_EN (1 << 6)
223 /* ALC_CIC_OP_LEVEL_CTRL bit fields */
224 #define DA9055_ALC_DATA_MIDDLE (2 << 0)
225 #define DA9055_ALC_DATA_TOP (3 << 0)
226 #define DA9055_ALC_CIC_OP_CHANNEL_LEFT (0 << 7)
227 #define DA9055_ALC_CIC_OP_CHANNEL_RIGHT (1 << 7)
229 #define DA9055_AIF_BCLK_MASK (3 << 0)
230 #define DA9055_AIF_CLK_MODE_MASK (1 << 7)
231 #define DA9055_AIF_FORMAT_MASK (3 << 0)
232 #define DA9055_AIF_WORD_LENGTH_MASK (3 << 2)
233 #define DA9055_GAIN_RAMPING_EN (1 << 5)
234 #define DA9055_MICBIAS_LEVEL_MASK (3 << 4)
236 #define DA9055_ALC_OFFSET_15_8 0x00FF00
237 #define DA9055_ALC_OFFSET_17_16 0x030000
238 #define DA9055_ALC_AVG_ITERATIONS 5
246 u8 mode; /* 0 = slave, 1 = master */
249 /* PLL divisor table */
250 static const struct pll_div da9055_pll_div[] = {
251 /* for MASTER mode, fs = 44.1Khz and its harmonics */
252 {11289600, 2822400, 0x00, 0x00, 0x20, 1}, /* MCLK=11.2896Mhz */
253 {12000000, 2822400, 0x03, 0x61, 0x1E, 1}, /* MCLK=12Mhz */
254 {12288000, 2822400, 0x0C, 0xCC, 0x1D, 1}, /* MCLK=12.288Mhz */
255 {13000000, 2822400, 0x19, 0x45, 0x1B, 1}, /* MCLK=13Mhz */
256 {13500000, 2822400, 0x18, 0x56, 0x1A, 1}, /* MCLK=13.5Mhz */
257 {14400000, 2822400, 0x02, 0xD0, 0x19, 1}, /* MCLK=14.4Mhz */
258 {19200000, 2822400, 0x1A, 0x1C, 0x12, 1}, /* MCLK=19.2Mhz */
259 {19680000, 2822400, 0x0B, 0x6D, 0x12, 1}, /* MCLK=19.68Mhz */
260 {19800000, 2822400, 0x07, 0xDD, 0x12, 1}, /* MCLK=19.8Mhz */
261 /* for MASTER mode, fs = 48Khz and its harmonics */
262 {11289600, 3072000, 0x1A, 0x8E, 0x22, 1}, /* MCLK=11.2896Mhz */
263 {12000000, 3072000, 0x18, 0x93, 0x20, 1}, /* MCLK=12Mhz */
264 {12288000, 3072000, 0x00, 0x00, 0x20, 1}, /* MCLK=12.288Mhz */
265 {13000000, 3072000, 0x07, 0xEA, 0x1E, 1}, /* MCLK=13Mhz */
266 {13500000, 3072000, 0x04, 0x11, 0x1D, 1}, /* MCLK=13.5Mhz */
267 {14400000, 3072000, 0x09, 0xD0, 0x1B, 1}, /* MCLK=14.4Mhz */
268 {19200000, 3072000, 0x0F, 0x5C, 0x14, 1}, /* MCLK=19.2Mhz */
269 {19680000, 3072000, 0x1F, 0x60, 0x13, 1}, /* MCLK=19.68Mhz */
270 {19800000, 3072000, 0x1B, 0x80, 0x13, 1}, /* MCLK=19.8Mhz */
271 /* for SLAVE mode with SRM */
272 {11289600, 2822400, 0x0D, 0x47, 0x21, 0}, /* MCLK=11.2896Mhz */
273 {12000000, 2822400, 0x0D, 0xFA, 0x1F, 0}, /* MCLK=12Mhz */
274 {12288000, 2822400, 0x16, 0x66, 0x1E, 0}, /* MCLK=12.288Mhz */
275 {13000000, 2822400, 0x00, 0x98, 0x1D, 0}, /* MCLK=13Mhz */
276 {13500000, 2822400, 0x1E, 0x33, 0x1B, 0}, /* MCLK=13.5Mhz */
277 {14400000, 2822400, 0x06, 0x50, 0x1A, 0}, /* MCLK=14.4Mhz */
278 {19200000, 2822400, 0x14, 0xBC, 0x13, 0}, /* MCLK=19.2Mhz */
279 {19680000, 2822400, 0x05, 0x66, 0x13, 0}, /* MCLK=19.68Mhz */
280 {19800000, 2822400, 0x01, 0xAE, 0x13, 0}, /* MCLK=19.8Mhz */
287 /* Gain and Volume */
289 static const unsigned int aux_vol_tlv[] = {
290 TLV_DB_RANGE_HEAD(2),
291 0x0, 0x10, TLV_DB_SCALE_ITEM(-5400, 0, 0),
293 0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
296 static const unsigned int digital_gain_tlv[] = {
297 TLV_DB_RANGE_HEAD(2),
298 0x0, 0x07, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
300 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
303 static const unsigned int alc_analog_gain_tlv[] = {
304 TLV_DB_RANGE_HEAD(2),
305 0x0, 0x0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
307 0x01, 0x07, TLV_DB_SCALE_ITEM(0, 600, 0)
310 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
311 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
312 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
313 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -5700, 100, 0);
314 static const DECLARE_TLV_DB_SCALE(lineout_vol_tlv, -4800, 100, 0);
315 static const DECLARE_TLV_DB_SCALE(alc_threshold_tlv, -9450, 150, 0);
316 static const DECLARE_TLV_DB_SCALE(alc_gain_tlv, 0, 600, 0);
318 /* ADC and DAC high pass filter cutoff value */
319 static const char * const da9055_hpf_cutoff_txt[] = {
320 "Fs/24000", "Fs/12000", "Fs/6000", "Fs/3000"
323 static const struct soc_enum da9055_dac_hpf_cutoff =
324 SOC_ENUM_SINGLE(DA9055_DAC_FILTERS1, 4, 4, da9055_hpf_cutoff_txt);
326 static const struct soc_enum da9055_adc_hpf_cutoff =
327 SOC_ENUM_SINGLE(DA9055_ADC_FILTERS1, 4, 4, da9055_hpf_cutoff_txt);
329 /* ADC and DAC voice mode (8kHz) high pass cutoff value */
330 static const char * const da9055_vf_cutoff_txt[] = {
331 "2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
334 static const struct soc_enum da9055_dac_vf_cutoff =
335 SOC_ENUM_SINGLE(DA9055_DAC_FILTERS1, 0, 8, da9055_vf_cutoff_txt);
337 static const struct soc_enum da9055_adc_vf_cutoff =
338 SOC_ENUM_SINGLE(DA9055_ADC_FILTERS1, 0, 8, da9055_vf_cutoff_txt);
340 /* Gain ramping rate value */
341 static const char * const da9055_gain_ramping_txt[] = {
342 "nominal rate", "nominal rate * 4", "nominal rate * 8",
346 static const struct soc_enum da9055_gain_ramping_rate =
347 SOC_ENUM_SINGLE(DA9055_GAIN_RAMP_CTRL, 0, 4, da9055_gain_ramping_txt);
349 /* DAC noise gate setup time value */
350 static const char * const da9055_dac_ng_setup_time_txt[] = {
351 "256 samples", "512 samples", "1024 samples", "2048 samples"
354 static const struct soc_enum da9055_dac_ng_setup_time =
355 SOC_ENUM_SINGLE(DA9055_DAC_NG_SETUP_TIME, 0, 4,
356 da9055_dac_ng_setup_time_txt);
358 /* DAC noise gate rampup rate value */
359 static const char * const da9055_dac_ng_rampup_txt[] = {
360 "0.02 ms/dB", "0.16 ms/dB"
363 static const struct soc_enum da9055_dac_ng_rampup_rate =
364 SOC_ENUM_SINGLE(DA9055_DAC_NG_SETUP_TIME, 2, 2,
365 da9055_dac_ng_rampup_txt);
367 /* DAC noise gate rampdown rate value */
368 static const char * const da9055_dac_ng_rampdown_txt[] = {
369 "0.64 ms/dB", "20.48 ms/dB"
372 static const struct soc_enum da9055_dac_ng_rampdown_rate =
373 SOC_ENUM_SINGLE(DA9055_DAC_NG_SETUP_TIME, 3, 2,
374 da9055_dac_ng_rampdown_txt);
376 /* DAC soft mute rate value */
377 static const char * const da9055_dac_soft_mute_rate_txt[] = {
378 "1", "2", "4", "8", "16", "32", "64"
381 static const struct soc_enum da9055_dac_soft_mute_rate =
382 SOC_ENUM_SINGLE(DA9055_DAC_FILTERS5, 4, 7,
383 da9055_dac_soft_mute_rate_txt);
385 /* DAC routing select */
386 static const char * const da9055_dac_src_txt[] = {
387 "ADC output left", "ADC output right", "AIF input left",
391 static const struct soc_enum da9055_dac_l_src =
392 SOC_ENUM_SINGLE(DA9055_DIG_ROUTING_DAC, 0, 4, da9055_dac_src_txt);
394 static const struct soc_enum da9055_dac_r_src =
395 SOC_ENUM_SINGLE(DA9055_DIG_ROUTING_DAC, 4, 4, da9055_dac_src_txt);
397 /* MIC PGA Left source select */
398 static const char * const da9055_mic_l_src_txt[] = {
399 "MIC1_P_N", "MIC1_P", "MIC1_N", "MIC2_L"
402 static const struct soc_enum da9055_mic_l_src =
403 SOC_ENUM_SINGLE(DA9055_MIXIN_L_SELECT, 4, 4, da9055_mic_l_src_txt);
405 /* MIC PGA Right source select */
406 static const char * const da9055_mic_r_src_txt[] = {
407 "MIC2_R_L", "MIC2_R", "MIC2_L"
410 static const struct soc_enum da9055_mic_r_src =
411 SOC_ENUM_SINGLE(DA9055_MIXIN_R_SELECT, 4, 3, da9055_mic_r_src_txt);
413 /* ALC Input Signal Tracking rate select */
414 static const char * const da9055_signal_tracking_rate_txt[] = {
415 "1/4", "1/16", "1/256", "1/65536"
418 static const struct soc_enum da9055_integ_attack_rate =
419 SOC_ENUM_SINGLE(DA9055_ALC_CTRL3, 4, 4,
420 da9055_signal_tracking_rate_txt);
422 static const struct soc_enum da9055_integ_release_rate =
423 SOC_ENUM_SINGLE(DA9055_ALC_CTRL3, 6, 4,
424 da9055_signal_tracking_rate_txt);
426 /* ALC Attack Rate select */
427 static const char * const da9055_attack_rate_txt[] = {
428 "44/fs", "88/fs", "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs",
429 "5632/fs", "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
432 static const struct soc_enum da9055_attack_rate =
433 SOC_ENUM_SINGLE(DA9055_ALC_CTRL2, 0, 13, da9055_attack_rate_txt);
435 /* ALC Release Rate select */
436 static const char * const da9055_release_rate_txt[] = {
437 "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs", "5632/fs",
438 "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
441 static const struct soc_enum da9055_release_rate =
442 SOC_ENUM_SINGLE(DA9055_ALC_CTRL2, 4, 11, da9055_release_rate_txt);
444 /* ALC Hold Time select */
445 static const char * const da9055_hold_time_txt[] = {
446 "62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs",
447 "7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs",
448 "253952/fs", "507904/fs", "1015808/fs", "2031616/fs"
451 static const struct soc_enum da9055_hold_time =
452 SOC_ENUM_SINGLE(DA9055_ALC_CTRL3, 0, 16, da9055_hold_time_txt);
454 static int da9055_get_alc_data(struct snd_soc_codec *codec, u8 reg_val)
456 int mid_data, top_data;
460 for (iteration = 0; iteration < DA9055_ALC_AVG_ITERATIONS;
462 /* Select the left or right channel and capture data */
463 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL, reg_val);
465 /* Select middle 8 bits for read back from data register */
466 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL,
467 reg_val | DA9055_ALC_DATA_MIDDLE);
468 mid_data = snd_soc_read(codec, DA9055_ALC_CIC_OP_LVL_DATA);
470 /* Select top 8 bits for read back from data register */
471 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL,
472 reg_val | DA9055_ALC_DATA_TOP);
473 top_data = snd_soc_read(codec, DA9055_ALC_CIC_OP_LVL_DATA);
475 sum += ((mid_data << 8) | (top_data << 16));
478 return sum / DA9055_ALC_AVG_ITERATIONS;
481 static int da9055_put_alc_sw(struct snd_kcontrol *kcontrol,
482 struct snd_ctl_elem_value *ucontrol)
484 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
485 u8 reg_val, adc_left, adc_right, mic_left, mic_right;
486 int avg_left_data, avg_right_data, offset_l, offset_r;
488 if (ucontrol->value.integer.value[0]) {
490 * While enabling ALC (or ALC sync mode), calibration of the DC
491 * offsets must be done first
494 /* Save current values from Mic control registers */
495 mic_left = snd_soc_read(codec, DA9055_MIC_L_CTRL);
496 mic_right = snd_soc_read(codec, DA9055_MIC_R_CTRL);
498 /* Mute Mic PGA Left and Right */
499 snd_soc_update_bits(codec, DA9055_MIC_L_CTRL,
500 DA9055_MIC_L_MUTE_EN, DA9055_MIC_L_MUTE_EN);
501 snd_soc_update_bits(codec, DA9055_MIC_R_CTRL,
502 DA9055_MIC_R_MUTE_EN, DA9055_MIC_R_MUTE_EN);
504 /* Save current values from ADC control registers */
505 adc_left = snd_soc_read(codec, DA9055_ADC_L_CTRL);
506 adc_right = snd_soc_read(codec, DA9055_ADC_R_CTRL);
508 /* Enable ADC Left and Right */
509 snd_soc_update_bits(codec, DA9055_ADC_L_CTRL,
510 DA9055_ADC_L_EN, DA9055_ADC_L_EN);
511 snd_soc_update_bits(codec, DA9055_ADC_R_CTRL,
512 DA9055_ADC_R_EN, DA9055_ADC_R_EN);
514 /* Calculate average for Left and Right data */
516 avg_left_data = da9055_get_alc_data(codec,
517 DA9055_ALC_CIC_OP_CHANNEL_LEFT);
519 avg_right_data = da9055_get_alc_data(codec,
520 DA9055_ALC_CIC_OP_CHANNEL_RIGHT);
522 /* Calculate DC offset */
523 offset_l = -avg_left_data;
524 offset_r = -avg_right_data;
526 reg_val = (offset_l & DA9055_ALC_OFFSET_15_8) >> 8;
527 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2M_L, reg_val);
528 reg_val = (offset_l & DA9055_ALC_OFFSET_17_16) >> 16;
529 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2U_L, reg_val);
531 reg_val = (offset_r & DA9055_ALC_OFFSET_15_8) >> 8;
532 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2M_R, reg_val);
533 reg_val = (offset_r & DA9055_ALC_OFFSET_17_16) >> 16;
534 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2U_R, reg_val);
536 /* Restore original values of ADC control registers */
537 snd_soc_write(codec, DA9055_ADC_L_CTRL, adc_left);
538 snd_soc_write(codec, DA9055_ADC_R_CTRL, adc_right);
540 /* Restore original values of Mic control registers */
541 snd_soc_write(codec, DA9055_MIC_L_CTRL, mic_left);
542 snd_soc_write(codec, DA9055_MIC_R_CTRL, mic_right);
545 return snd_soc_put_volsw(kcontrol, ucontrol);
548 static const struct snd_kcontrol_new da9055_snd_controls[] = {
550 /* Volume controls */
551 SOC_DOUBLE_R_TLV("Mic Volume",
552 DA9055_MIC_L_GAIN, DA9055_MIC_R_GAIN,
553 0, 0x7, 0, mic_vol_tlv),
554 SOC_DOUBLE_R_TLV("Aux Volume",
555 DA9055_AUX_L_GAIN, DA9055_AUX_R_GAIN,
556 0, 0x3f, 0, aux_vol_tlv),
557 SOC_DOUBLE_R_TLV("Mixin PGA Volume",
558 DA9055_MIXIN_L_GAIN, DA9055_MIXIN_R_GAIN,
559 0, 0xf, 0, mixin_gain_tlv),
560 SOC_DOUBLE_R_TLV("ADC Volume",
561 DA9055_ADC_L_GAIN, DA9055_ADC_R_GAIN,
562 0, 0x7f, 0, digital_gain_tlv),
564 SOC_DOUBLE_R_TLV("DAC Volume",
565 DA9055_DAC_L_GAIN, DA9055_DAC_R_GAIN,
566 0, 0x7f, 0, digital_gain_tlv),
567 SOC_DOUBLE_R_TLV("Headphone Volume",
568 DA9055_HP_L_GAIN, DA9055_HP_R_GAIN,
569 0, 0x3f, 0, hp_vol_tlv),
570 SOC_SINGLE_TLV("Lineout Volume", DA9055_LINE_GAIN, 0, 0x3f, 0,
573 /* DAC Equalizer controls */
574 SOC_SINGLE("DAC EQ Switch", DA9055_DAC_FILTERS4, 7, 1, 0),
575 SOC_SINGLE_TLV("DAC EQ1 Volume", DA9055_DAC_FILTERS2, 0, 0xf, 0,
577 SOC_SINGLE_TLV("DAC EQ2 Volume", DA9055_DAC_FILTERS2, 4, 0xf, 0,
579 SOC_SINGLE_TLV("DAC EQ3 Volume", DA9055_DAC_FILTERS3, 0, 0xf, 0,
581 SOC_SINGLE_TLV("DAC EQ4 Volume", DA9055_DAC_FILTERS3, 4, 0xf, 0,
583 SOC_SINGLE_TLV("DAC EQ5 Volume", DA9055_DAC_FILTERS4, 0, 0xf, 0,
586 /* High Pass Filter and Voice Mode controls */
587 SOC_SINGLE("ADC HPF Switch", DA9055_ADC_FILTERS1, 7, 1, 0),
588 SOC_ENUM("ADC HPF Cutoff", da9055_adc_hpf_cutoff),
589 SOC_SINGLE("ADC Voice Mode Switch", DA9055_ADC_FILTERS1, 3, 1, 0),
590 SOC_ENUM("ADC Voice Cutoff", da9055_adc_vf_cutoff),
592 SOC_SINGLE("DAC HPF Switch", DA9055_DAC_FILTERS1, 7, 1, 0),
593 SOC_ENUM("DAC HPF Cutoff", da9055_dac_hpf_cutoff),
594 SOC_SINGLE("DAC Voice Mode Switch", DA9055_DAC_FILTERS1, 3, 1, 0),
595 SOC_ENUM("DAC Voice Cutoff", da9055_dac_vf_cutoff),
598 SOC_DOUBLE_R("Mic Switch", DA9055_MIC_L_CTRL,
599 DA9055_MIC_R_CTRL, 6, 1, 0),
600 SOC_DOUBLE_R("Aux Switch", DA9055_AUX_L_CTRL,
601 DA9055_AUX_R_CTRL, 6, 1, 0),
602 SOC_DOUBLE_R("Mixin PGA Switch", DA9055_MIXIN_L_CTRL,
603 DA9055_MIXIN_R_CTRL, 6, 1, 0),
604 SOC_DOUBLE_R("ADC Switch", DA9055_ADC_L_CTRL,
605 DA9055_ADC_R_CTRL, 6, 1, 0),
606 SOC_DOUBLE_R("Headphone Switch", DA9055_HP_L_CTRL,
607 DA9055_HP_R_CTRL, 6, 1, 0),
608 SOC_SINGLE("Lineout Switch", DA9055_LINE_CTRL, 6, 1, 0),
609 SOC_SINGLE("DAC Soft Mute Switch", DA9055_DAC_FILTERS5, 7, 1, 0),
610 SOC_ENUM("DAC Soft Mute Rate", da9055_dac_soft_mute_rate),
612 /* Zero Cross controls */
613 SOC_DOUBLE_R("Aux ZC Switch", DA9055_AUX_L_CTRL,
614 DA9055_AUX_R_CTRL, 4, 1, 0),
615 SOC_DOUBLE_R("Mixin PGA ZC Switch", DA9055_MIXIN_L_CTRL,
616 DA9055_MIXIN_R_CTRL, 4, 1, 0),
617 SOC_DOUBLE_R("Headphone ZC Switch", DA9055_HP_L_CTRL,
618 DA9055_HP_R_CTRL, 4, 1, 0),
619 SOC_SINGLE("Lineout ZC Switch", DA9055_LINE_CTRL, 4, 1, 0),
621 /* Gain Ramping controls */
622 SOC_DOUBLE_R("Aux Gain Ramping Switch", DA9055_AUX_L_CTRL,
623 DA9055_AUX_R_CTRL, 5, 1, 0),
624 SOC_DOUBLE_R("Mixin Gain Ramping Switch", DA9055_MIXIN_L_CTRL,
625 DA9055_MIXIN_R_CTRL, 5, 1, 0),
626 SOC_DOUBLE_R("ADC Gain Ramping Switch", DA9055_ADC_L_CTRL,
627 DA9055_ADC_R_CTRL, 5, 1, 0),
628 SOC_DOUBLE_R("DAC Gain Ramping Switch", DA9055_DAC_L_CTRL,
629 DA9055_DAC_R_CTRL, 5, 1, 0),
630 SOC_DOUBLE_R("Headphone Gain Ramping Switch", DA9055_HP_L_CTRL,
631 DA9055_HP_R_CTRL, 5, 1, 0),
632 SOC_SINGLE("Lineout Gain Ramping Switch", DA9055_LINE_CTRL, 5, 1, 0),
633 SOC_ENUM("Gain Ramping Rate", da9055_gain_ramping_rate),
635 /* DAC Noise Gate controls */
636 SOC_SINGLE("DAC NG Switch", DA9055_DAC_NG_CTRL, 7, 1, 0),
637 SOC_SINGLE("DAC NG ON Threshold", DA9055_DAC_NG_ON_THRESHOLD,
639 SOC_SINGLE("DAC NG OFF Threshold", DA9055_DAC_NG_OFF_THRESHOLD,
641 SOC_ENUM("DAC NG Setup Time", da9055_dac_ng_setup_time),
642 SOC_ENUM("DAC NG Rampup Rate", da9055_dac_ng_rampup_rate),
643 SOC_ENUM("DAC NG Rampdown Rate", da9055_dac_ng_rampdown_rate),
645 /* DAC Invertion control */
646 SOC_SINGLE("DAC Left Invert", DA9055_DIG_CTRL, 3, 1, 0),
647 SOC_SINGLE("DAC Right Invert", DA9055_DIG_CTRL, 7, 1, 0),
650 SOC_DOUBLE_R("DMIC Switch", DA9055_MIXIN_L_SELECT,
651 DA9055_MIXIN_R_SELECT, 7, 1, 0),
654 SOC_DOUBLE_EXT("ALC Switch", DA9055_ALC_CTRL1, 3, 7, 1, 0,
655 snd_soc_get_volsw, da9055_put_alc_sw),
656 SOC_SINGLE_EXT("ALC Sync Mode Switch", DA9055_ALC_CTRL1, 1, 1, 0,
657 snd_soc_get_volsw, da9055_put_alc_sw),
658 SOC_SINGLE("ALC Offset Switch", DA9055_ALC_CTRL1, 0, 1, 0),
659 SOC_SINGLE("ALC Anticlip Mode Switch", DA9055_ALC_ANTICLIP_CTRL,
661 SOC_SINGLE("ALC Anticlip Level", DA9055_ALC_ANTICLIP_LEVEL,
663 SOC_SINGLE_TLV("ALC Min Threshold Volume", DA9055_ALC_TARGET_MIN,
664 0, 0x3f, 1, alc_threshold_tlv),
665 SOC_SINGLE_TLV("ALC Max Threshold Volume", DA9055_ALC_TARGET_MAX,
666 0, 0x3f, 1, alc_threshold_tlv),
667 SOC_SINGLE_TLV("ALC Noise Threshold Volume", DA9055_ALC_NOISE,
668 0, 0x3f, 1, alc_threshold_tlv),
669 SOC_SINGLE_TLV("ALC Max Gain Volume", DA9055_ALC_GAIN_LIMITS,
670 4, 0xf, 0, alc_gain_tlv),
671 SOC_SINGLE_TLV("ALC Max Attenuation Volume", DA9055_ALC_GAIN_LIMITS,
672 0, 0xf, 0, alc_gain_tlv),
673 SOC_SINGLE_TLV("ALC Min Analog Gain Volume",
674 DA9055_ALC_ANA_GAIN_LIMITS,
675 0, 0x7, 0, alc_analog_gain_tlv),
676 SOC_SINGLE_TLV("ALC Max Analog Gain Volume",
677 DA9055_ALC_ANA_GAIN_LIMITS,
678 4, 0x7, 0, alc_analog_gain_tlv),
679 SOC_ENUM("ALC Attack Rate", da9055_attack_rate),
680 SOC_ENUM("ALC Release Rate", da9055_release_rate),
681 SOC_ENUM("ALC Hold Time", da9055_hold_time),
683 * Rate at which input signal envelope is tracked as the signal gets
686 SOC_ENUM("ALC Integ Attack Rate", da9055_integ_attack_rate),
688 * Rate at which input signal envelope is tracked as the signal gets
691 SOC_ENUM("ALC Integ Release Rate", da9055_integ_release_rate),
696 /* Mic PGA Left Source */
697 static const struct snd_kcontrol_new da9055_mic_l_mux_controls =
698 SOC_DAPM_ENUM("Route", da9055_mic_l_src);
700 /* Mic PGA Right Source */
701 static const struct snd_kcontrol_new da9055_mic_r_mux_controls =
702 SOC_DAPM_ENUM("Route", da9055_mic_r_src);
705 static const struct snd_kcontrol_new da9055_dapm_mixinl_controls[] = {
706 SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXIN_L_SELECT, 0, 1, 0),
707 SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_L_SELECT, 1, 1, 0),
708 SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_L_SELECT, 2, 1, 0),
712 static const struct snd_kcontrol_new da9055_dapm_mixinr_controls[] = {
713 SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXIN_R_SELECT, 0, 1, 0),
714 SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_R_SELECT, 1, 1, 0),
715 SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_R_SELECT, 2, 1, 0),
716 SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXIN_R_SELECT, 3, 1, 0),
719 /* DAC Left Source */
720 static const struct snd_kcontrol_new da9055_dac_l_mux_controls =
721 SOC_DAPM_ENUM("Route", da9055_dac_l_src);
723 /* DAC Right Source */
724 static const struct snd_kcontrol_new da9055_dac_r_mux_controls =
725 SOC_DAPM_ENUM("Route", da9055_dac_r_src);
728 static const struct snd_kcontrol_new da9055_dapm_mixoutl_controls[] = {
729 SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXOUT_L_SELECT, 0, 1, 0),
730 SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_L_SELECT, 1, 1, 0),
731 SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_L_SELECT, 2, 1, 0),
732 SOC_DAPM_SINGLE("DAC Left Switch", DA9055_MIXOUT_L_SELECT, 3, 1, 0),
733 SOC_DAPM_SINGLE("Aux Left Invert Switch", DA9055_MIXOUT_L_SELECT,
735 SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_L_SELECT,
737 SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_L_SELECT,
741 /* Out Mixer Right */
742 static const struct snd_kcontrol_new da9055_dapm_mixoutr_controls[] = {
743 SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXOUT_R_SELECT, 0, 1, 0),
744 SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_R_SELECT, 1, 1, 0),
745 SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_R_SELECT, 2, 1, 0),
746 SOC_DAPM_SINGLE("DAC Right Switch", DA9055_MIXOUT_R_SELECT, 3, 1, 0),
747 SOC_DAPM_SINGLE("Aux Right Invert Switch", DA9055_MIXOUT_R_SELECT,
749 SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_R_SELECT,
751 SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_R_SELECT,
756 static const struct snd_soc_dapm_widget da9055_dapm_widgets[] = {
760 SND_SOC_DAPM_INPUT("MIC1"),
761 SND_SOC_DAPM_INPUT("MIC2"),
762 SND_SOC_DAPM_INPUT("AUXL"),
763 SND_SOC_DAPM_INPUT("AUXR"),
765 /* MUXs for Mic PGA source selection */
766 SND_SOC_DAPM_MUX("Mic Left Source", SND_SOC_NOPM, 0, 0,
767 &da9055_mic_l_mux_controls),
768 SND_SOC_DAPM_MUX("Mic Right Source", SND_SOC_NOPM, 0, 0,
769 &da9055_mic_r_mux_controls),
772 SND_SOC_DAPM_PGA("Mic Left", DA9055_MIC_L_CTRL, 7, 0, NULL, 0),
773 SND_SOC_DAPM_PGA("Mic Right", DA9055_MIC_R_CTRL, 7, 0, NULL, 0),
774 SND_SOC_DAPM_PGA("Aux Left", DA9055_AUX_L_CTRL, 7, 0, NULL, 0),
775 SND_SOC_DAPM_PGA("Aux Right", DA9055_AUX_R_CTRL, 7, 0, NULL, 0),
776 SND_SOC_DAPM_PGA("MIXIN Left", DA9055_MIXIN_L_CTRL, 7, 0, NULL, 0),
777 SND_SOC_DAPM_PGA("MIXIN Right", DA9055_MIXIN_R_CTRL, 7, 0, NULL, 0),
779 SND_SOC_DAPM_SUPPLY("Mic Bias", DA9055_MIC_BIAS_CTRL, 7, 0, NULL, 0),
780 SND_SOC_DAPM_SUPPLY("AIF", DA9055_AIF_CTRL, 7, 0, NULL, 0),
781 SND_SOC_DAPM_SUPPLY("Charge Pump", DA9055_CP_CTRL, 7, 0, NULL, 0),
784 SND_SOC_DAPM_MIXER("In Mixer Left", SND_SOC_NOPM, 0, 0,
785 &da9055_dapm_mixinl_controls[0],
786 ARRAY_SIZE(da9055_dapm_mixinl_controls)),
787 SND_SOC_DAPM_MIXER("In Mixer Right", SND_SOC_NOPM, 0, 0,
788 &da9055_dapm_mixinr_controls[0],
789 ARRAY_SIZE(da9055_dapm_mixinr_controls)),
792 SND_SOC_DAPM_ADC("ADC Left", "Capture", DA9055_ADC_L_CTRL, 7, 0),
793 SND_SOC_DAPM_ADC("ADC Right", "Capture", DA9055_ADC_R_CTRL, 7, 0),
797 /* MUXs for DAC source selection */
798 SND_SOC_DAPM_MUX("DAC Left Source", SND_SOC_NOPM, 0, 0,
799 &da9055_dac_l_mux_controls),
800 SND_SOC_DAPM_MUX("DAC Right Source", SND_SOC_NOPM, 0, 0,
801 &da9055_dac_r_mux_controls),
804 SND_SOC_DAPM_AIF_IN("AIFIN Left", "Playback", 0, SND_SOC_NOPM, 0, 0),
805 SND_SOC_DAPM_AIF_IN("AIFIN Right", "Playback", 0, SND_SOC_NOPM, 0, 0),
808 SND_SOC_DAPM_DAC("DAC Left", "Playback", DA9055_DAC_L_CTRL, 7, 0),
809 SND_SOC_DAPM_DAC("DAC Right", "Playback", DA9055_DAC_R_CTRL, 7, 0),
812 SND_SOC_DAPM_MIXER("Out Mixer Left", SND_SOC_NOPM, 0, 0,
813 &da9055_dapm_mixoutl_controls[0],
814 ARRAY_SIZE(da9055_dapm_mixoutl_controls)),
815 SND_SOC_DAPM_MIXER("Out Mixer Right", SND_SOC_NOPM, 0, 0,
816 &da9055_dapm_mixoutr_controls[0],
817 ARRAY_SIZE(da9055_dapm_mixoutr_controls)),
820 SND_SOC_DAPM_PGA("MIXOUT Left", DA9055_MIXOUT_L_CTRL, 7, 0, NULL, 0),
821 SND_SOC_DAPM_PGA("MIXOUT Right", DA9055_MIXOUT_R_CTRL, 7, 0, NULL, 0),
822 SND_SOC_DAPM_PGA("Lineout", DA9055_LINE_CTRL, 7, 0, NULL, 0),
823 SND_SOC_DAPM_PGA("Headphone Left", DA9055_HP_L_CTRL, 7, 0, NULL, 0),
824 SND_SOC_DAPM_PGA("Headphone Right", DA9055_HP_R_CTRL, 7, 0, NULL, 0),
827 SND_SOC_DAPM_OUTPUT("HPL"),
828 SND_SOC_DAPM_OUTPUT("HPR"),
829 SND_SOC_DAPM_OUTPUT("LINE"),
832 /* DAPM audio route definition */
833 static const struct snd_soc_dapm_route da9055_audio_map[] = {
834 /* Dest Connecting Widget source */
837 {"Mic Left Source", "MIC1_P_N", "MIC1"},
838 {"Mic Left Source", "MIC1_P", "MIC1"},
839 {"Mic Left Source", "MIC1_N", "MIC1"},
840 {"Mic Left Source", "MIC2_L", "MIC2"},
842 {"Mic Right Source", "MIC2_R_L", "MIC2"},
843 {"Mic Right Source", "MIC2_R", "MIC2"},
844 {"Mic Right Source", "MIC2_L", "MIC2"},
846 {"Mic Left", NULL, "Mic Left Source"},
847 {"Mic Right", NULL, "Mic Right Source"},
849 {"Aux Left", NULL, "AUXL"},
850 {"Aux Right", NULL, "AUXR"},
852 {"In Mixer Left", "Mic Left Switch", "Mic Left"},
853 {"In Mixer Left", "Mic Right Switch", "Mic Right"},
854 {"In Mixer Left", "Aux Left Switch", "Aux Left"},
856 {"In Mixer Right", "Mic Right Switch", "Mic Right"},
857 {"In Mixer Right", "Mic Left Switch", "Mic Left"},
858 {"In Mixer Right", "Aux Right Switch", "Aux Right"},
859 {"In Mixer Right", "Mixin Left Switch", "MIXIN Left"},
861 {"MIXIN Left", NULL, "In Mixer Left"},
862 {"ADC Left", NULL, "MIXIN Left"},
864 {"MIXIN Right", NULL, "In Mixer Right"},
865 {"ADC Right", NULL, "MIXIN Right"},
867 {"ADC Left", NULL, "AIF"},
868 {"ADC Right", NULL, "AIF"},
871 {"AIFIN Left", NULL, "AIF"},
872 {"AIFIN Right", NULL, "AIF"},
874 {"DAC Left Source", "ADC output left", "ADC Left"},
875 {"DAC Left Source", "ADC output right", "ADC Right"},
876 {"DAC Left Source", "AIF input left", "AIFIN Left"},
877 {"DAC Left Source", "AIF input right", "AIFIN Right"},
879 {"DAC Right Source", "ADC output left", "ADC Left"},
880 {"DAC Right Source", "ADC output right", "ADC Right"},
881 {"DAC Right Source", "AIF input left", "AIFIN Left"},
882 {"DAC Right Source", "AIF input right", "AIFIN Right"},
884 {"DAC Left", NULL, "DAC Left Source"},
885 {"DAC Right", NULL, "DAC Right Source"},
887 {"Out Mixer Left", "Aux Left Switch", "Aux Left"},
888 {"Out Mixer Left", "Mixin Left Switch", "MIXIN Left"},
889 {"Out Mixer Left", "Mixin Right Switch", "MIXIN Right"},
890 {"Out Mixer Left", "Aux Left Invert Switch", "Aux Left"},
891 {"Out Mixer Left", "Mixin Left Invert Switch", "MIXIN Left"},
892 {"Out Mixer Left", "Mixin Right Invert Switch", "MIXIN Right"},
893 {"Out Mixer Left", "DAC Left Switch", "DAC Left"},
895 {"Out Mixer Right", "Aux Right Switch", "Aux Right"},
896 {"Out Mixer Right", "Mixin Right Switch", "MIXIN Right"},
897 {"Out Mixer Right", "Mixin Left Switch", "MIXIN Left"},
898 {"Out Mixer Right", "Aux Right Invert Switch", "Aux Right"},
899 {"Out Mixer Right", "Mixin Right Invert Switch", "MIXIN Right"},
900 {"Out Mixer Right", "Mixin Left Invert Switch", "MIXIN Left"},
901 {"Out Mixer Right", "DAC Right Switch", "DAC Right"},
903 {"MIXOUT Left", NULL, "Out Mixer Left"},
904 {"Headphone Left", NULL, "MIXOUT Left"},
905 {"Headphone Left", NULL, "Charge Pump"},
906 {"HPL", NULL, "Headphone Left"},
908 {"MIXOUT Right", NULL, "Out Mixer Right"},
909 {"Headphone Right", NULL, "MIXOUT Right"},
910 {"Headphone Right", NULL, "Charge Pump"},
911 {"HPR", NULL, "Headphone Right"},
913 {"MIXOUT Right", NULL, "Out Mixer Right"},
914 {"Lineout", NULL, "MIXOUT Right"},
915 {"LINE", NULL, "Lineout"},
918 /* Codec private data */
920 struct regmap *regmap;
921 unsigned int mclk_rate;
923 struct da9055_platform_data *pdata;
926 static struct reg_default da9055_reg_defaults[] = {
1002 static bool da9055_volatile_register(struct device *dev,
1006 case DA9055_STATUS1:
1007 case DA9055_PLL_STATUS:
1008 case DA9055_AUX_L_GAIN_STATUS:
1009 case DA9055_AUX_R_GAIN_STATUS:
1010 case DA9055_MIC_L_GAIN_STATUS:
1011 case DA9055_MIC_R_GAIN_STATUS:
1012 case DA9055_MIXIN_L_GAIN_STATUS:
1013 case DA9055_MIXIN_R_GAIN_STATUS:
1014 case DA9055_ADC_L_GAIN_STATUS:
1015 case DA9055_ADC_R_GAIN_STATUS:
1016 case DA9055_DAC_L_GAIN_STATUS:
1017 case DA9055_DAC_R_GAIN_STATUS:
1018 case DA9055_HP_L_GAIN_STATUS:
1019 case DA9055_HP_R_GAIN_STATUS:
1020 case DA9055_LINE_GAIN_STATUS:
1021 case DA9055_ALC_CIC_OP_LVL_DATA:
1028 /* Set DAI word length */
1029 static int da9055_hw_params(struct snd_pcm_substream *substream,
1030 struct snd_pcm_hw_params *params,
1031 struct snd_soc_dai *dai)
1033 struct snd_soc_codec *codec = dai->codec;
1034 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1038 switch (params_format(params)) {
1039 case SNDRV_PCM_FORMAT_S16_LE:
1040 aif_ctrl = DA9055_AIF_WORD_S16_LE;
1042 case SNDRV_PCM_FORMAT_S20_3LE:
1043 aif_ctrl = DA9055_AIF_WORD_S20_3LE;
1045 case SNDRV_PCM_FORMAT_S24_LE:
1046 aif_ctrl = DA9055_AIF_WORD_S24_LE;
1048 case SNDRV_PCM_FORMAT_S32_LE:
1049 aif_ctrl = DA9055_AIF_WORD_S32_LE;
1055 /* Set AIF format */
1056 snd_soc_update_bits(codec, DA9055_AIF_CTRL, DA9055_AIF_WORD_LENGTH_MASK,
1059 switch (params_rate(params)) {
1061 fs = DA9055_SR_8000;
1065 fs = DA9055_SR_11025;
1069 fs = DA9055_SR_12000;
1073 fs = DA9055_SR_16000;
1077 fs = DA9055_SR_22050;
1081 fs = DA9055_SR_32000;
1085 fs = DA9055_SR_44100;
1089 fs = DA9055_SR_48000;
1093 fs = DA9055_SR_88200;
1097 fs = DA9055_SR_96000;
1104 if (da9055->mclk_rate) {
1105 /* PLL Mode, Write actual FS */
1106 snd_soc_write(codec, DA9055_SR, fs);
1110 * When PLL is bypassed, chip assumes constant MCLK of
1111 * 12.288MHz and uses sample rate value to divide this MCLK
1112 * to derive its sys clk. As sys clk has to be 256 * Fs, we
1113 * need to write constant sample rate i.e. 48KHz.
1115 snd_soc_write(codec, DA9055_SR, DA9055_SR_48000);
1118 if (da9055->mclk_rate && (da9055->mclk_rate != sysclk)) {
1120 if (!da9055->master) {
1121 /* PLL slave mode, enable PLL and also SRM */
1122 snd_soc_update_bits(codec, DA9055_PLL_CTRL,
1123 DA9055_PLL_EN | DA9055_PLL_SRM_EN,
1124 DA9055_PLL_EN | DA9055_PLL_SRM_EN);
1126 /* PLL master mode, only enable PLL */
1127 snd_soc_update_bits(codec, DA9055_PLL_CTRL,
1128 DA9055_PLL_EN, DA9055_PLL_EN);
1131 /* Non PLL Mode, disable PLL */
1132 snd_soc_update_bits(codec, DA9055_PLL_CTRL, DA9055_PLL_EN, 0);
1138 /* Set DAI mode and Format */
1139 static int da9055_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1141 struct snd_soc_codec *codec = codec_dai->codec;
1142 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1143 u8 aif_clk_mode, aif_ctrl, mode;
1145 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1146 case SND_SOC_DAIFMT_CBM_CFM:
1147 /* DA9055 in I2S Master Mode */
1149 aif_clk_mode = DA9055_AIF_CLK_EN_MASTER_MODE;
1151 case SND_SOC_DAIFMT_CBS_CFS:
1152 /* DA9055 in I2S Slave Mode */
1154 aif_clk_mode = DA9055_AIF_CLK_EN_SLAVE_MODE;
1160 /* Don't allow change of mode if PLL is enabled */
1161 if ((snd_soc_read(codec, DA9055_PLL_CTRL) & DA9055_PLL_EN) &&
1162 (da9055->master != mode))
1165 da9055->master = mode;
1167 /* Only I2S is supported */
1168 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1169 case SND_SOC_DAIFMT_I2S:
1170 aif_ctrl = DA9055_AIF_FORMAT_I2S_MODE;
1172 case SND_SOC_DAIFMT_LEFT_J:
1173 aif_ctrl = DA9055_AIF_FORMAT_LEFT_J;
1175 case SND_SOC_DAIFMT_RIGHT_J:
1176 aif_ctrl = DA9055_AIF_FORMAT_RIGHT_J;
1182 /* By default only 32 BCLK per WCLK is supported */
1183 aif_clk_mode |= DA9055_AIF_BCLKS_PER_WCLK_32;
1185 snd_soc_update_bits(codec, DA9055_AIF_CLK_MODE,
1186 (DA9055_AIF_CLK_MODE_MASK | DA9055_AIF_BCLK_MASK),
1188 snd_soc_update_bits(codec, DA9055_AIF_CTRL, DA9055_AIF_FORMAT_MASK,
1193 static int da9055_mute(struct snd_soc_dai *dai, int mute)
1195 struct snd_soc_codec *codec = dai->codec;
1198 snd_soc_update_bits(codec, DA9055_DAC_L_CTRL,
1199 DA9055_DAC_L_MUTE_EN, DA9055_DAC_L_MUTE_EN);
1200 snd_soc_update_bits(codec, DA9055_DAC_R_CTRL,
1201 DA9055_DAC_R_MUTE_EN, DA9055_DAC_R_MUTE_EN);
1203 snd_soc_update_bits(codec, DA9055_DAC_L_CTRL,
1204 DA9055_DAC_L_MUTE_EN, 0);
1205 snd_soc_update_bits(codec, DA9055_DAC_R_CTRL,
1206 DA9055_DAC_R_MUTE_EN, 0);
1212 #define DA9055_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1213 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1215 static int da9055_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1216 int clk_id, unsigned int freq, int dir)
1218 struct snd_soc_codec *codec = codec_dai->codec;
1219 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1222 case DA9055_CLKSRC_MCLK:
1233 da9055->mclk_rate = freq;
1236 dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
1242 dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
1248 * da9055_set_dai_pll : Configure the codec PLL
1249 * @param codec_dai : Pointer to codec DAI
1250 * @param pll_id : da9055 has only one pll, so pll_id is always zero
1251 * @param fref : Input MCLK frequency
1252 * @param fout : FsDM value
1253 * @return int : Zero for success, negative error code for error
1255 * Note: Supported PLL input frequencies are 11.2896MHz, 12MHz, 12.288MHz,
1256 * 13MHz, 13.5MHz, 14.4MHz, 19.2MHz, 19.6MHz and 19.8MHz
1258 static int da9055_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1259 int source, unsigned int fref, unsigned int fout)
1261 struct snd_soc_codec *codec = codec_dai->codec;
1262 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1264 u8 pll_frac_top, pll_frac_bot, pll_integer, cnt;
1266 /* Disable PLL before setting the divisors */
1267 snd_soc_update_bits(codec, DA9055_PLL_CTRL, DA9055_PLL_EN, 0);
1269 /* In slave mode, there is only one set of divisors */
1270 if (!da9055->master && (fout != 2822400))
1273 /* Search pll div array for correct divisors */
1274 for (cnt = 0; cnt < ARRAY_SIZE(da9055_pll_div); cnt++) {
1275 /* Check fref, mode and fout */
1276 if ((fref == da9055_pll_div[cnt].fref) &&
1277 (da9055->master == da9055_pll_div[cnt].mode) &&
1278 (fout == da9055_pll_div[cnt].fout)) {
1279 /* All match, pick up divisors */
1280 pll_frac_top = da9055_pll_div[cnt].frac_top;
1281 pll_frac_bot = da9055_pll_div[cnt].frac_bot;
1282 pll_integer = da9055_pll_div[cnt].integer;
1286 if (cnt >= ARRAY_SIZE(da9055_pll_div))
1289 /* Write PLL dividers */
1290 snd_soc_write(codec, DA9055_PLL_FRAC_TOP, pll_frac_top);
1291 snd_soc_write(codec, DA9055_PLL_FRAC_BOT, pll_frac_bot);
1292 snd_soc_write(codec, DA9055_PLL_INTEGER, pll_integer);
1296 dev_err(codec_dai->dev, "Error in setting up PLL\n");
1300 /* DAI operations */
1301 static const struct snd_soc_dai_ops da9055_dai_ops = {
1302 .hw_params = da9055_hw_params,
1303 .set_fmt = da9055_set_dai_fmt,
1304 .set_sysclk = da9055_set_dai_sysclk,
1305 .set_pll = da9055_set_dai_pll,
1306 .digital_mute = da9055_mute,
1309 static struct snd_soc_dai_driver da9055_dai = {
1310 .name = "da9055-hifi",
1311 /* Playback Capabilities */
1313 .stream_name = "Playback",
1316 .rates = SNDRV_PCM_RATE_8000_96000,
1317 .formats = DA9055_FORMATS,
1319 /* Capture Capabilities */
1321 .stream_name = "Capture",
1324 .rates = SNDRV_PCM_RATE_8000_96000,
1325 .formats = DA9055_FORMATS,
1327 .ops = &da9055_dai_ops,
1328 .symmetric_rates = 1,
1331 static int da9055_set_bias_level(struct snd_soc_codec *codec,
1332 enum snd_soc_bias_level level)
1335 case SND_SOC_BIAS_ON:
1336 case SND_SOC_BIAS_PREPARE:
1338 case SND_SOC_BIAS_STANDBY:
1339 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1340 /* Enable VMID reference & master bias */
1341 snd_soc_update_bits(codec, DA9055_REFERENCES,
1342 DA9055_VMID_EN | DA9055_BIAS_EN,
1343 DA9055_VMID_EN | DA9055_BIAS_EN);
1346 case SND_SOC_BIAS_OFF:
1347 /* Disable VMID reference & master bias */
1348 snd_soc_update_bits(codec, DA9055_REFERENCES,
1349 DA9055_VMID_EN | DA9055_BIAS_EN, 0);
1352 codec->dapm.bias_level = level;
1356 static int da9055_probe(struct snd_soc_codec *codec)
1359 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1361 codec->control_data = da9055->regmap;
1362 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1364 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1368 /* Enable all Gain Ramps */
1369 snd_soc_update_bits(codec, DA9055_AUX_L_CTRL,
1370 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1371 snd_soc_update_bits(codec, DA9055_AUX_R_CTRL,
1372 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1373 snd_soc_update_bits(codec, DA9055_MIXIN_L_CTRL,
1374 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1375 snd_soc_update_bits(codec, DA9055_MIXIN_R_CTRL,
1376 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1377 snd_soc_update_bits(codec, DA9055_ADC_L_CTRL,
1378 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1379 snd_soc_update_bits(codec, DA9055_ADC_R_CTRL,
1380 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1381 snd_soc_update_bits(codec, DA9055_DAC_L_CTRL,
1382 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1383 snd_soc_update_bits(codec, DA9055_DAC_R_CTRL,
1384 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1385 snd_soc_update_bits(codec, DA9055_HP_L_CTRL,
1386 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1387 snd_soc_update_bits(codec, DA9055_HP_R_CTRL,
1388 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1389 snd_soc_update_bits(codec, DA9055_LINE_CTRL,
1390 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1393 * There are two separate control bits for input and output mixers as
1394 * well as headphone and line outs.
1395 * One to enable corresponding amplifier and other to enable its
1396 * output. As amplifier bits are related to power control, they are
1397 * being managed by DAPM while other (non power related) bits are
1400 snd_soc_update_bits(codec, DA9055_MIXIN_L_CTRL,
1401 DA9055_MIXIN_L_MIX_EN, DA9055_MIXIN_L_MIX_EN);
1402 snd_soc_update_bits(codec, DA9055_MIXIN_R_CTRL,
1403 DA9055_MIXIN_R_MIX_EN, DA9055_MIXIN_R_MIX_EN);
1405 snd_soc_update_bits(codec, DA9055_MIXOUT_L_CTRL,
1406 DA9055_MIXOUT_L_MIX_EN, DA9055_MIXOUT_L_MIX_EN);
1407 snd_soc_update_bits(codec, DA9055_MIXOUT_R_CTRL,
1408 DA9055_MIXOUT_R_MIX_EN, DA9055_MIXOUT_R_MIX_EN);
1410 snd_soc_update_bits(codec, DA9055_HP_L_CTRL,
1411 DA9055_HP_L_AMP_OE, DA9055_HP_L_AMP_OE);
1412 snd_soc_update_bits(codec, DA9055_HP_R_CTRL,
1413 DA9055_HP_R_AMP_OE, DA9055_HP_R_AMP_OE);
1415 snd_soc_update_bits(codec, DA9055_LINE_CTRL,
1416 DA9055_LINE_AMP_OE, DA9055_LINE_AMP_OE);
1418 /* Set this as per your system configuration */
1419 snd_soc_write(codec, DA9055_PLL_CTRL, DA9055_PLL_INDIV_10_20_MHZ);
1421 /* Set platform data values */
1422 if (da9055->pdata) {
1423 /* set mic bias source */
1424 if (da9055->pdata->micbias_source) {
1425 snd_soc_update_bits(codec, DA9055_MIXIN_R_SELECT,
1427 DA9055_MICBIAS2_EN);
1429 snd_soc_update_bits(codec, DA9055_MIXIN_R_SELECT,
1430 DA9055_MICBIAS2_EN, 0);
1432 /* set mic bias voltage */
1433 switch (da9055->pdata->micbias) {
1434 case DA9055_MICBIAS_2_2V:
1435 case DA9055_MICBIAS_2_1V:
1436 case DA9055_MICBIAS_1_8V:
1437 case DA9055_MICBIAS_1_6V:
1438 snd_soc_update_bits(codec, DA9055_MIC_CONFIG,
1439 DA9055_MICBIAS_LEVEL_MASK,
1440 (da9055->pdata->micbias) << 4);
1447 static struct snd_soc_codec_driver soc_codec_dev_da9055 = {
1448 .probe = da9055_probe,
1449 .set_bias_level = da9055_set_bias_level,
1451 .controls = da9055_snd_controls,
1452 .num_controls = ARRAY_SIZE(da9055_snd_controls),
1454 .dapm_widgets = da9055_dapm_widgets,
1455 .num_dapm_widgets = ARRAY_SIZE(da9055_dapm_widgets),
1456 .dapm_routes = da9055_audio_map,
1457 .num_dapm_routes = ARRAY_SIZE(da9055_audio_map),
1460 static const struct regmap_config da9055_regmap_config = {
1464 .reg_defaults = da9055_reg_defaults,
1465 .num_reg_defaults = ARRAY_SIZE(da9055_reg_defaults),
1466 .volatile_reg = da9055_volatile_register,
1467 .cache_type = REGCACHE_RBTREE,
1470 static int __devinit da9055_i2c_probe(struct i2c_client *i2c,
1471 const struct i2c_device_id *id)
1473 struct da9055_priv *da9055;
1474 struct da9055_platform_data *pdata = dev_get_platdata(&i2c->dev);
1477 da9055 = devm_kzalloc(&i2c->dev, sizeof(struct da9055_priv),
1483 da9055->pdata = pdata;
1485 i2c_set_clientdata(i2c, da9055);
1487 da9055->regmap = devm_regmap_init_i2c(i2c, &da9055_regmap_config);
1488 if (IS_ERR(da9055->regmap)) {
1489 ret = PTR_ERR(da9055->regmap);
1490 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
1494 ret = snd_soc_register_codec(&i2c->dev,
1495 &soc_codec_dev_da9055, &da9055_dai, 1);
1497 dev_err(&i2c->dev, "Failed to register da9055 codec: %d\n",
1503 static int __devexit da9055_remove(struct i2c_client *client)
1505 snd_soc_unregister_codec(&client->dev);
1509 static const struct i2c_device_id da9055_i2c_id[] = {
1513 MODULE_DEVICE_TABLE(i2c, da9055_i2c_id);
1515 /* I2C codec control layer */
1516 static struct i2c_driver da9055_i2c_driver = {
1519 .owner = THIS_MODULE,
1521 .probe = da9055_i2c_probe,
1522 .remove = __devexit_p(da9055_remove),
1523 .id_table = da9055_i2c_id,
1526 module_i2c_driver(da9055_i2c_driver);
1528 MODULE_DESCRIPTION("ASoC DA9055 Codec driver");
1529 MODULE_AUTHOR("David Chen, Ashish Chavan");
1530 MODULE_LICENSE("GPL");