2 * arizona.c - Wolfson Arizona class device shared support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/gcd.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/tlv.h>
21 #include <linux/mfd/arizona/core.h>
22 #include <linux/mfd/arizona/gpio.h>
23 #include <linux/mfd/arizona/registers.h>
27 #define ARIZONA_AIF_BCLK_CTRL 0x00
28 #define ARIZONA_AIF_TX_PIN_CTRL 0x01
29 #define ARIZONA_AIF_RX_PIN_CTRL 0x02
30 #define ARIZONA_AIF_RATE_CTRL 0x03
31 #define ARIZONA_AIF_FORMAT 0x04
32 #define ARIZONA_AIF_TX_BCLK_RATE 0x05
33 #define ARIZONA_AIF_RX_BCLK_RATE 0x06
34 #define ARIZONA_AIF_FRAME_CTRL_1 0x07
35 #define ARIZONA_AIF_FRAME_CTRL_2 0x08
36 #define ARIZONA_AIF_FRAME_CTRL_3 0x09
37 #define ARIZONA_AIF_FRAME_CTRL_4 0x0A
38 #define ARIZONA_AIF_FRAME_CTRL_5 0x0B
39 #define ARIZONA_AIF_FRAME_CTRL_6 0x0C
40 #define ARIZONA_AIF_FRAME_CTRL_7 0x0D
41 #define ARIZONA_AIF_FRAME_CTRL_8 0x0E
42 #define ARIZONA_AIF_FRAME_CTRL_9 0x0F
43 #define ARIZONA_AIF_FRAME_CTRL_10 0x10
44 #define ARIZONA_AIF_FRAME_CTRL_11 0x11
45 #define ARIZONA_AIF_FRAME_CTRL_12 0x12
46 #define ARIZONA_AIF_FRAME_CTRL_13 0x13
47 #define ARIZONA_AIF_FRAME_CTRL_14 0x14
48 #define ARIZONA_AIF_FRAME_CTRL_15 0x15
49 #define ARIZONA_AIF_FRAME_CTRL_16 0x16
50 #define ARIZONA_AIF_FRAME_CTRL_17 0x17
51 #define ARIZONA_AIF_FRAME_CTRL_18 0x18
52 #define ARIZONA_AIF_TX_ENABLES 0x19
53 #define ARIZONA_AIF_RX_ENABLES 0x1A
54 #define ARIZONA_AIF_FORCE_WRITE 0x1B
56 #define arizona_fll_err(_fll, fmt, ...) \
57 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
58 #define arizona_fll_warn(_fll, fmt, ...) \
59 dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
60 #define arizona_fll_dbg(_fll, fmt, ...) \
61 dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
63 #define arizona_aif_err(_dai, fmt, ...) \
64 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
65 #define arizona_aif_warn(_dai, fmt, ...) \
66 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
67 #define arizona_aif_dbg(_dai, fmt, ...) \
68 dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
70 static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
71 struct snd_kcontrol *kcontrol,
74 struct snd_soc_codec *codec = w->codec;
75 struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
76 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
77 bool manual_ena = false;
80 switch (arizona->type) {
82 switch (arizona->rev) {
94 case SND_SOC_DAPM_PRE_PMU:
95 if (!priv->spk_ena && manual_ena) {
96 snd_soc_write(codec, 0x4f5, 0x25a);
97 priv->spk_ena_pending = true;
100 case SND_SOC_DAPM_POST_PMU:
101 val = snd_soc_read(codec, ARIZONA_INTERRUPT_RAW_STATUS_3);
102 if (val & ARIZONA_SPK_SHUTDOWN_STS) {
103 dev_crit(arizona->dev,
104 "Speaker not enabled due to temperature\n");
108 snd_soc_update_bits(codec, ARIZONA_OUTPUT_ENABLES_1,
109 1 << w->shift, 1 << w->shift);
111 if (priv->spk_ena_pending) {
113 snd_soc_write(codec, 0x4f5, 0xda);
114 priv->spk_ena_pending = false;
118 case SND_SOC_DAPM_PRE_PMD:
122 snd_soc_write(codec, 0x4f5, 0x25a);
125 snd_soc_update_bits(codec, ARIZONA_OUTPUT_ENABLES_1,
128 case SND_SOC_DAPM_POST_PMD:
131 snd_soc_write(codec, 0x4f5, 0x0da);
139 static irqreturn_t arizona_thermal_warn(int irq, void *data)
141 struct arizona *arizona = data;
145 ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
148 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
150 } else if (val & ARIZONA_SPK_SHUTDOWN_WARN_STS) {
151 dev_crit(arizona->dev, "Thermal warning\n");
157 static irqreturn_t arizona_thermal_shutdown(int irq, void *data)
159 struct arizona *arizona = data;
163 ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
166 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
168 } else if (val & ARIZONA_SPK_SHUTDOWN_STS) {
169 dev_crit(arizona->dev, "Thermal shutdown\n");
170 ret = regmap_update_bits(arizona->regmap,
171 ARIZONA_OUTPUT_ENABLES_1,
173 ARIZONA_OUT4R_ENA, 0);
175 dev_crit(arizona->dev,
176 "Failed to disable speaker outputs: %d\n",
183 static const struct snd_soc_dapm_widget arizona_spkl =
184 SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
185 ARIZONA_OUT4L_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
186 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
188 static const struct snd_soc_dapm_widget arizona_spkr =
189 SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM,
190 ARIZONA_OUT4R_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
191 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
193 int arizona_init_spk(struct snd_soc_codec *codec)
195 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
196 struct arizona *arizona = priv->arizona;
199 ret = snd_soc_dapm_new_controls(&codec->dapm, &arizona_spkl, 1);
203 ret = snd_soc_dapm_new_controls(&codec->dapm, &arizona_spkr, 1);
207 ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_SHUTDOWN_WARN,
208 "Thermal warning", arizona_thermal_warn,
211 dev_err(arizona->dev,
212 "Failed to get thermal warning IRQ: %d\n",
215 ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_SHUTDOWN,
216 "Thermal shutdown", arizona_thermal_shutdown,
219 dev_err(arizona->dev,
220 "Failed to get thermal shutdown IRQ: %d\n",
225 EXPORT_SYMBOL_GPL(arizona_init_spk);
227 int arizona_init_gpio(struct snd_soc_codec *codec)
229 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
230 struct arizona *arizona = priv->arizona;
233 switch (arizona->type) {
235 snd_soc_dapm_disable_pin(&codec->dapm, "DRC2 Signal Activity");
238 snd_soc_dapm_disable_pin(&codec->dapm, "DRC1 Signal Activity");
240 for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
241 switch (arizona->pdata.gpio_defaults[i] & ARIZONA_GPN_FN_MASK) {
242 case ARIZONA_GP_FN_DRC1_SIGNAL_DETECT:
243 snd_soc_dapm_enable_pin(&codec->dapm,
244 "DRC1 Signal Activity");
246 case ARIZONA_GP_FN_DRC2_SIGNAL_DETECT:
247 snd_soc_dapm_enable_pin(&codec->dapm,
248 "DRC2 Signal Activity");
257 EXPORT_SYMBOL_GPL(arizona_init_gpio);
259 const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = {
360 EXPORT_SYMBOL_GPL(arizona_mixer_texts);
362 int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = {
368 0x0c, /* Noise mixer */
369 0x0d, /* Comfort noise */
438 0xa0, /* ISRC1INT1 */
442 0xa4, /* ISRC1DEC1 */
446 0xa8, /* ISRC2DEC1 */
450 0xac, /* ISRC2INT1 */
454 0xb0, /* ISRC3DEC1 */
458 0xb4, /* ISRC3INT1 */
463 EXPORT_SYMBOL_GPL(arizona_mixer_values);
465 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0);
466 EXPORT_SYMBOL_GPL(arizona_mixer_tlv);
468 const char *arizona_rate_text[ARIZONA_RATE_ENUM_SIZE] = {
469 "SYNCCLK rate", "8kHz", "16kHz", "ASYNCCLK rate",
471 EXPORT_SYMBOL_GPL(arizona_rate_text);
473 const int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE] = {
476 EXPORT_SYMBOL_GPL(arizona_rate_val);
479 const struct soc_enum arizona_isrc_fsl[] = {
480 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2,
481 ARIZONA_ISRC1_FSL_SHIFT, 0xf,
482 ARIZONA_RATE_ENUM_SIZE,
483 arizona_rate_text, arizona_rate_val),
484 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2,
485 ARIZONA_ISRC2_FSL_SHIFT, 0xf,
486 ARIZONA_RATE_ENUM_SIZE,
487 arizona_rate_text, arizona_rate_val),
488 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2,
489 ARIZONA_ISRC3_FSL_SHIFT, 0xf,
490 ARIZONA_RATE_ENUM_SIZE,
491 arizona_rate_text, arizona_rate_val),
493 EXPORT_SYMBOL_GPL(arizona_isrc_fsl);
495 static const char *arizona_vol_ramp_text[] = {
496 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
497 "15ms/6dB", "30ms/6dB",
500 const struct soc_enum arizona_in_vd_ramp =
501 SOC_ENUM_SINGLE(ARIZONA_INPUT_VOLUME_RAMP,
502 ARIZONA_IN_VD_RAMP_SHIFT, 7, arizona_vol_ramp_text);
503 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp);
505 const struct soc_enum arizona_in_vi_ramp =
506 SOC_ENUM_SINGLE(ARIZONA_INPUT_VOLUME_RAMP,
507 ARIZONA_IN_VI_RAMP_SHIFT, 7, arizona_vol_ramp_text);
508 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp);
510 const struct soc_enum arizona_out_vd_ramp =
511 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_VOLUME_RAMP,
512 ARIZONA_OUT_VD_RAMP_SHIFT, 7, arizona_vol_ramp_text);
513 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp);
515 const struct soc_enum arizona_out_vi_ramp =
516 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_VOLUME_RAMP,
517 ARIZONA_OUT_VI_RAMP_SHIFT, 7, arizona_vol_ramp_text);
518 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp);
520 static const char *arizona_lhpf_mode_text[] = {
521 "Low-pass", "High-pass"
524 const struct soc_enum arizona_lhpf1_mode =
525 SOC_ENUM_SINGLE(ARIZONA_HPLPF1_1, ARIZONA_LHPF1_MODE_SHIFT, 2,
526 arizona_lhpf_mode_text);
527 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode);
529 const struct soc_enum arizona_lhpf2_mode =
530 SOC_ENUM_SINGLE(ARIZONA_HPLPF2_1, ARIZONA_LHPF2_MODE_SHIFT, 2,
531 arizona_lhpf_mode_text);
532 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode);
534 const struct soc_enum arizona_lhpf3_mode =
535 SOC_ENUM_SINGLE(ARIZONA_HPLPF3_1, ARIZONA_LHPF3_MODE_SHIFT, 2,
536 arizona_lhpf_mode_text);
537 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode);
539 const struct soc_enum arizona_lhpf4_mode =
540 SOC_ENUM_SINGLE(ARIZONA_HPLPF4_1, ARIZONA_LHPF4_MODE_SHIFT, 2,
541 arizona_lhpf_mode_text);
542 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode);
544 static const char *arizona_ng_hold_text[] = {
545 "30ms", "120ms", "250ms", "500ms",
548 const struct soc_enum arizona_ng_hold =
549 SOC_ENUM_SINGLE(ARIZONA_NOISE_GATE_CONTROL, ARIZONA_NGATE_HOLD_SHIFT,
550 4, arizona_ng_hold_text);
551 EXPORT_SYMBOL_GPL(arizona_ng_hold);
553 static void arizona_in_set_vu(struct snd_soc_codec *codec, int ena)
555 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
564 for (i = 0; i < priv->num_inputs; i++)
565 snd_soc_update_bits(codec,
566 ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 4),
570 int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
573 struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec);
577 reg = ARIZONA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8);
579 reg = ARIZONA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8);
582 case SND_SOC_DAPM_PRE_PMU:
585 case SND_SOC_DAPM_POST_PMU:
586 snd_soc_update_bits(w->codec, reg, ARIZONA_IN1L_MUTE, 0);
588 /* If this is the last input pending then allow VU */
590 if (priv->in_pending == 0) {
592 arizona_in_set_vu(w->codec, 1);
595 case SND_SOC_DAPM_PRE_PMD:
596 snd_soc_update_bits(w->codec, reg,
597 ARIZONA_IN1L_MUTE | ARIZONA_IN_VU,
598 ARIZONA_IN1L_MUTE | ARIZONA_IN_VU);
600 case SND_SOC_DAPM_POST_PMD:
601 /* Disable volume updates if no inputs are enabled */
602 reg = snd_soc_read(w->codec, ARIZONA_INPUT_ENABLES);
604 arizona_in_set_vu(w->codec, 0);
609 EXPORT_SYMBOL_GPL(arizona_in_ev);
611 int arizona_out_ev(struct snd_soc_dapm_widget *w,
612 struct snd_kcontrol *kcontrol,
616 case SND_SOC_DAPM_POST_PMU:
618 case ARIZONA_OUT1L_ENA_SHIFT:
619 case ARIZONA_OUT1R_ENA_SHIFT:
620 case ARIZONA_OUT2L_ENA_SHIFT:
621 case ARIZONA_OUT2R_ENA_SHIFT:
622 case ARIZONA_OUT3L_ENA_SHIFT:
623 case ARIZONA_OUT3R_ENA_SHIFT:
635 EXPORT_SYMBOL_GPL(arizona_out_ev);
637 int arizona_hp_ev(struct snd_soc_dapm_widget *w,
638 struct snd_kcontrol *kcontrol,
641 struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec);
642 unsigned int mask = 1 << w->shift;
646 case SND_SOC_DAPM_POST_PMU:
649 case SND_SOC_DAPM_PRE_PMD:
656 /* Store the desired state for the HP outputs */
657 priv->arizona->hp_ena &= ~mask;
658 priv->arizona->hp_ena |= val;
660 /* Force off if HPDET magic is active */
661 if (priv->arizona->hpdet_magic)
664 snd_soc_update_bits(w->codec, ARIZONA_OUTPUT_ENABLES_1, mask, val);
666 return arizona_out_ev(w, kcontrol, event);
668 EXPORT_SYMBOL_GPL(arizona_hp_ev);
670 static unsigned int arizona_sysclk_48k_rates[] = {
680 static unsigned int arizona_sysclk_44k1_rates[] = {
690 static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk,
693 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
696 int ref, div, refclk;
699 case ARIZONA_CLK_OPCLK:
700 reg = ARIZONA_OUTPUT_SYSTEM_CLOCK;
701 refclk = priv->sysclk;
703 case ARIZONA_CLK_ASYNC_OPCLK:
704 reg = ARIZONA_OUTPUT_ASYNC_CLOCK;
705 refclk = priv->asyncclk;
712 rates = arizona_sysclk_44k1_rates;
714 rates = arizona_sysclk_48k_rates;
716 for (ref = 0; ref < ARRAY_SIZE(arizona_sysclk_48k_rates) &&
717 rates[ref] <= refclk; ref++) {
719 while (rates[ref] / div >= freq && div < 32) {
720 if (rates[ref] / div == freq) {
721 dev_dbg(codec->dev, "Configured %dHz OPCLK\n",
723 snd_soc_update_bits(codec, reg,
724 ARIZONA_OPCLK_DIV_MASK |
725 ARIZONA_OPCLK_SEL_MASK,
727 ARIZONA_OPCLK_DIV_SHIFT) |
735 dev_err(codec->dev, "Unable to generate %dHz OPCLK\n", freq);
739 int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
740 int source, unsigned int freq, int dir)
742 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
743 struct arizona *arizona = priv->arizona;
746 unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK;
747 unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT;
751 case ARIZONA_CLK_SYSCLK:
753 reg = ARIZONA_SYSTEM_CLOCK_1;
755 mask |= ARIZONA_SYSCLK_FRAC;
757 case ARIZONA_CLK_ASYNCCLK:
759 reg = ARIZONA_ASYNC_CLOCK_1;
760 clk = &priv->asyncclk;
762 case ARIZONA_CLK_OPCLK:
763 case ARIZONA_CLK_ASYNC_OPCLK:
764 return arizona_set_opclk(codec, clk_id, freq);
775 val |= ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
779 val |= ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
783 val |= ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
787 val |= ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
791 val |= ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
795 val |= ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
798 dev_dbg(arizona->dev, "%s cleared\n", name);
808 val |= ARIZONA_SYSCLK_FRAC;
810 dev_dbg(arizona->dev, "%s set to %uHz", name, freq);
812 return regmap_update_bits(arizona->regmap, reg, mask, val);
814 EXPORT_SYMBOL_GPL(arizona_set_sysclk);
816 static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
818 struct snd_soc_codec *codec = dai->codec;
819 int lrclk, bclk, mode, base;
821 base = dai->driver->base;
826 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
827 case SND_SOC_DAIFMT_DSP_A:
830 case SND_SOC_DAIFMT_I2S:
834 arizona_aif_err(dai, "Unsupported DAI format %d\n",
835 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
839 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
840 case SND_SOC_DAIFMT_CBS_CFS:
842 case SND_SOC_DAIFMT_CBS_CFM:
843 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
845 case SND_SOC_DAIFMT_CBM_CFS:
846 bclk |= ARIZONA_AIF1_BCLK_MSTR;
848 case SND_SOC_DAIFMT_CBM_CFM:
849 bclk |= ARIZONA_AIF1_BCLK_MSTR;
850 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
853 arizona_aif_err(dai, "Unsupported master mode %d\n",
854 fmt & SND_SOC_DAIFMT_MASTER_MASK);
858 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
859 case SND_SOC_DAIFMT_NB_NF:
861 case SND_SOC_DAIFMT_IB_IF:
862 bclk |= ARIZONA_AIF1_BCLK_INV;
863 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
865 case SND_SOC_DAIFMT_IB_NF:
866 bclk |= ARIZONA_AIF1_BCLK_INV;
868 case SND_SOC_DAIFMT_NB_IF:
869 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
875 snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL,
876 ARIZONA_AIF1_BCLK_INV | ARIZONA_AIF1_BCLK_MSTR,
878 snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_PIN_CTRL,
879 ARIZONA_AIF1TX_LRCLK_INV |
880 ARIZONA_AIF1TX_LRCLK_MSTR, lrclk);
881 snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_PIN_CTRL,
882 ARIZONA_AIF1RX_LRCLK_INV |
883 ARIZONA_AIF1RX_LRCLK_MSTR, lrclk);
884 snd_soc_update_bits(codec, base + ARIZONA_AIF_FORMAT,
885 ARIZONA_AIF1_FMT_MASK, mode);
890 static const int arizona_48k_bclk_rates[] = {
912 static const unsigned int arizona_48k_rates[] = {
930 static const struct snd_pcm_hw_constraint_list arizona_48k_constraint = {
931 .count = ARRAY_SIZE(arizona_48k_rates),
932 .list = arizona_48k_rates,
935 static const int arizona_44k1_bclk_rates[] = {
957 static const unsigned int arizona_44k1_rates[] = {
967 static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint = {
968 .count = ARRAY_SIZE(arizona_44k1_rates),
969 .list = arizona_44k1_rates,
972 static int arizona_sr_vals[] = {
999 static int arizona_startup(struct snd_pcm_substream *substream,
1000 struct snd_soc_dai *dai)
1002 struct snd_soc_codec *codec = dai->codec;
1003 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1004 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1005 const struct snd_pcm_hw_constraint_list *constraint;
1006 unsigned int base_rate;
1008 switch (dai_priv->clk) {
1009 case ARIZONA_CLK_SYSCLK:
1010 base_rate = priv->sysclk;
1012 case ARIZONA_CLK_ASYNCCLK:
1013 base_rate = priv->asyncclk;
1022 if (base_rate % 8000)
1023 constraint = &arizona_44k1_constraint;
1025 constraint = &arizona_48k_constraint;
1027 return snd_pcm_hw_constraint_list(substream->runtime, 0,
1028 SNDRV_PCM_HW_PARAM_RATE,
1032 static int arizona_hw_params_rate(struct snd_pcm_substream *substream,
1033 struct snd_pcm_hw_params *params,
1034 struct snd_soc_dai *dai)
1036 struct snd_soc_codec *codec = dai->codec;
1037 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1038 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1039 int base = dai->driver->base;
1043 * We will need to be more flexible than this in future,
1044 * currently we use a single sample rate for SYSCLK.
1046 for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
1047 if (arizona_sr_vals[i] == params_rate(params))
1049 if (i == ARRAY_SIZE(arizona_sr_vals)) {
1050 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1051 params_rate(params));
1056 switch (dai_priv->clk) {
1057 case ARIZONA_CLK_SYSCLK:
1058 snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1,
1059 ARIZONA_SAMPLE_RATE_1_MASK, sr_val);
1061 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1062 ARIZONA_AIF1_RATE_MASK, 0);
1064 case ARIZONA_CLK_ASYNCCLK:
1065 snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
1066 ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val);
1068 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1069 ARIZONA_AIF1_RATE_MASK,
1070 8 << ARIZONA_AIF1_RATE_SHIFT);
1073 arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
1080 static int arizona_hw_params(struct snd_pcm_substream *substream,
1081 struct snd_pcm_hw_params *params,
1082 struct snd_soc_dai *dai)
1084 struct snd_soc_codec *codec = dai->codec;
1085 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1086 struct arizona *arizona = priv->arizona;
1087 int base = dai->driver->base;
1090 int chan_limit = arizona->pdata.max_channels_clocked[dai->id - 1];
1091 int bclk, lrclk, wl, frame, bclk_target;
1093 if (params_rate(params) % 8000)
1094 rates = &arizona_44k1_bclk_rates[0];
1096 rates = &arizona_48k_bclk_rates[0];
1098 bclk_target = snd_soc_params_to_bclk(params);
1099 if (chan_limit && chan_limit < params_channels(params)) {
1100 arizona_aif_dbg(dai, "Limiting to %d channels\n", chan_limit);
1101 bclk_target /= params_channels(params);
1102 bclk_target *= chan_limit;
1105 /* Force stereo for I2S mode */
1106 val = snd_soc_read(codec, base + ARIZONA_AIF_FORMAT);
1107 if (params_channels(params) == 1 && (val & ARIZONA_AIF1_FMT_MASK)) {
1108 arizona_aif_dbg(dai, "Forcing stereo mode\n");
1112 for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) {
1113 if (rates[i] >= bclk_target &&
1114 rates[i] % params_rate(params) == 0) {
1119 if (i == ARRAY_SIZE(arizona_44k1_bclk_rates)) {
1120 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1121 params_rate(params));
1125 lrclk = rates[bclk] / params_rate(params);
1127 arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
1128 rates[bclk], rates[bclk] / lrclk);
1130 wl = snd_pcm_format_width(params_format(params));
1131 frame = wl << ARIZONA_AIF1TX_WL_SHIFT | wl;
1133 ret = arizona_hw_params_rate(substream, params, dai);
1137 snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL,
1138 ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
1139 snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_BCLK_RATE,
1140 ARIZONA_AIF1TX_BCPF_MASK, lrclk);
1141 snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_BCLK_RATE,
1142 ARIZONA_AIF1RX_BCPF_MASK, lrclk);
1143 snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_1,
1144 ARIZONA_AIF1TX_WL_MASK |
1145 ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
1146 snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_2,
1147 ARIZONA_AIF1RX_WL_MASK |
1148 ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
1153 static const char *arizona_dai_clk_str(int clk_id)
1156 case ARIZONA_CLK_SYSCLK:
1158 case ARIZONA_CLK_ASYNCCLK:
1161 return "Unknown clock";
1165 static int arizona_dai_set_sysclk(struct snd_soc_dai *dai,
1166 int clk_id, unsigned int freq, int dir)
1168 struct snd_soc_codec *codec = dai->codec;
1169 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1170 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1171 struct snd_soc_dapm_route routes[2];
1174 case ARIZONA_CLK_SYSCLK:
1175 case ARIZONA_CLK_ASYNCCLK:
1181 if (clk_id == dai_priv->clk)
1185 dev_err(codec->dev, "Can't change clock on active DAI %d\n",
1190 dev_dbg(codec->dev, "Setting AIF%d to %s\n", dai->id + 1,
1191 arizona_dai_clk_str(clk_id));
1193 memset(&routes, 0, sizeof(routes));
1194 routes[0].sink = dai->driver->capture.stream_name;
1195 routes[1].sink = dai->driver->playback.stream_name;
1197 routes[0].source = arizona_dai_clk_str(dai_priv->clk);
1198 routes[1].source = arizona_dai_clk_str(dai_priv->clk);
1199 snd_soc_dapm_del_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
1201 routes[0].source = arizona_dai_clk_str(clk_id);
1202 routes[1].source = arizona_dai_clk_str(clk_id);
1203 snd_soc_dapm_add_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
1205 dai_priv->clk = clk_id;
1207 return snd_soc_dapm_sync(&codec->dapm);
1210 static int arizona_set_tristate(struct snd_soc_dai *dai, int tristate)
1212 struct snd_soc_codec *codec = dai->codec;
1213 int base = dai->driver->base;
1217 reg = ARIZONA_AIF1_TRI;
1221 return snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1222 ARIZONA_AIF1_TRI, reg);
1225 const struct snd_soc_dai_ops arizona_dai_ops = {
1226 .startup = arizona_startup,
1227 .set_fmt = arizona_set_fmt,
1228 .hw_params = arizona_hw_params,
1229 .set_sysclk = arizona_dai_set_sysclk,
1230 .set_tristate = arizona_set_tristate,
1232 EXPORT_SYMBOL_GPL(arizona_dai_ops);
1234 const struct snd_soc_dai_ops arizona_simple_dai_ops = {
1235 .startup = arizona_startup,
1236 .hw_params = arizona_hw_params_rate,
1237 .set_sysclk = arizona_dai_set_sysclk,
1239 EXPORT_SYMBOL_GPL(arizona_simple_dai_ops);
1241 int arizona_init_dai(struct arizona_priv *priv, int id)
1243 struct arizona_dai_priv *dai_priv = &priv->dai[id];
1245 dai_priv->clk = ARIZONA_CLK_SYSCLK;
1249 EXPORT_SYMBOL_GPL(arizona_init_dai);
1251 static irqreturn_t arizona_fll_clock_ok(int irq, void *data)
1253 struct arizona_fll *fll = data;
1255 arizona_fll_dbg(fll, "clock OK\n");
1268 { 0, 64000, 4, 16 },
1269 { 64000, 128000, 3, 8 },
1270 { 128000, 256000, 2, 4 },
1271 { 256000, 1000000, 1, 2 },
1272 { 1000000, 13500000, 0, 1 },
1281 { 256000, 1000000, 2 },
1282 { 1000000, 13500000, 4 },
1285 struct arizona_fll_cfg {
1295 static int arizona_calc_fll(struct arizona_fll *fll,
1296 struct arizona_fll_cfg *cfg,
1300 unsigned int target, div, gcd_fll;
1303 arizona_fll_dbg(fll, "Fref=%u Fout=%u\n", Fref, Fout);
1305 /* Fref must be <=13.5MHz */
1308 while ((Fref / div) > 13500000) {
1313 arizona_fll_err(fll,
1314 "Can't scale %dMHz in to <=13.5MHz\n",
1320 /* Apply the division for our remaining calculations */
1323 /* Fvco should be over the targt; don't check the upper bound */
1325 while (Fout * div < 90000000 * fll->vco_mult) {
1328 arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n",
1333 target = Fout * div / fll->vco_mult;
1336 arizona_fll_dbg(fll, "Fvco=%dHz\n", target);
1338 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1339 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1340 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1341 cfg->fratio = fll_fratios[i].fratio;
1342 ratio = fll_fratios[i].ratio;
1346 if (i == ARRAY_SIZE(fll_fratios)) {
1347 arizona_fll_err(fll, "Unable to find FRATIO for Fref=%uHz\n",
1352 for (i = 0; i < ARRAY_SIZE(fll_gains); i++) {
1353 if (fll_gains[i].min <= Fref && Fref <= fll_gains[i].max) {
1354 cfg->gain = fll_gains[i].gain;
1358 if (i == ARRAY_SIZE(fll_gains)) {
1359 arizona_fll_err(fll, "Unable to find gain for Fref=%uHz\n",
1364 cfg->n = target / (ratio * Fref);
1366 if (target % (ratio * Fref)) {
1367 gcd_fll = gcd(target, ratio * Fref);
1368 arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll);
1370 cfg->theta = (target - (cfg->n * ratio * Fref))
1372 cfg->lambda = (ratio * Fref) / gcd_fll;
1378 /* Round down to 16bit range with cost of accuracy lost.
1379 * Denominator must be bigger than numerator so we only
1382 while (cfg->lambda >= (1 << 16)) {
1387 arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n",
1388 cfg->n, cfg->theta, cfg->lambda);
1389 arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
1390 cfg->fratio, cfg->fratio, cfg->outdiv, cfg->refdiv);
1391 arizona_fll_dbg(fll, "GAIN=%d\n", cfg->gain);
1397 static void arizona_apply_fll(struct arizona *arizona, unsigned int base,
1398 struct arizona_fll_cfg *cfg, int source,
1401 regmap_update_bits(arizona->regmap, base + 3,
1402 ARIZONA_FLL1_THETA_MASK, cfg->theta);
1403 regmap_update_bits(arizona->regmap, base + 4,
1404 ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda);
1405 regmap_update_bits(arizona->regmap, base + 5,
1406 ARIZONA_FLL1_FRATIO_MASK,
1407 cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT);
1408 regmap_update_bits(arizona->regmap, base + 6,
1409 ARIZONA_FLL1_CLK_REF_DIV_MASK |
1410 ARIZONA_FLL1_CLK_REF_SRC_MASK,
1411 cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
1412 source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
1415 regmap_update_bits(arizona->regmap, base + 0x7,
1416 ARIZONA_FLL1_GAIN_MASK,
1417 cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
1419 regmap_update_bits(arizona->regmap, base + 0x9,
1420 ARIZONA_FLL1_GAIN_MASK,
1421 cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
1423 regmap_update_bits(arizona->regmap, base + 2,
1424 ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
1425 ARIZONA_FLL1_CTRL_UPD | cfg->n);
1428 static bool arizona_is_enabled_fll(struct arizona_fll *fll)
1430 struct arizona *arizona = fll->arizona;
1434 ret = regmap_read(arizona->regmap, fll->base + 1, ®);
1436 arizona_fll_err(fll, "Failed to read current state: %d\n",
1441 return reg & ARIZONA_FLL1_ENA;
1444 static void arizona_enable_fll(struct arizona_fll *fll,
1445 struct arizona_fll_cfg *ref,
1446 struct arizona_fll_cfg *sync)
1448 struct arizona *arizona = fll->arizona;
1452 * If we have both REFCLK and SYNCCLK then enable both,
1453 * otherwise apply the SYNCCLK settings to REFCLK.
1455 if (fll->ref_src >= 0 && fll->ref_src != fll->sync_src) {
1456 regmap_update_bits(arizona->regmap, fll->base + 5,
1457 ARIZONA_FLL1_OUTDIV_MASK,
1458 ref->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
1460 arizona_apply_fll(arizona, fll->base, ref, fll->ref_src,
1462 if (fll->sync_src >= 0)
1463 arizona_apply_fll(arizona, fll->base + 0x10, sync,
1464 fll->sync_src, true);
1465 } else if (fll->sync_src >= 0) {
1466 regmap_update_bits(arizona->regmap, fll->base + 5,
1467 ARIZONA_FLL1_OUTDIV_MASK,
1468 sync->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
1470 arizona_apply_fll(arizona, fll->base, sync,
1471 fll->sync_src, false);
1473 regmap_update_bits(arizona->regmap, fll->base + 0x11,
1474 ARIZONA_FLL1_SYNC_ENA, 0);
1476 arizona_fll_err(fll, "No clocks provided\n");
1481 * Increase the bandwidth if we're not using a low frequency
1484 if (fll->sync_src >= 0 && fll->sync_freq > 100000)
1485 regmap_update_bits(arizona->regmap, fll->base + 0x17,
1486 ARIZONA_FLL1_SYNC_BW, 0);
1488 regmap_update_bits(arizona->regmap, fll->base + 0x17,
1489 ARIZONA_FLL1_SYNC_BW, ARIZONA_FLL1_SYNC_BW);
1491 if (!arizona_is_enabled_fll(fll))
1492 pm_runtime_get(arizona->dev);
1494 /* Clear any pending completions */
1495 try_wait_for_completion(&fll->ok);
1497 regmap_update_bits(arizona->regmap, fll->base + 1,
1498 ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
1499 if (fll->ref_src >= 0 && fll->sync_src >= 0 &&
1500 fll->ref_src != fll->sync_src)
1501 regmap_update_bits(arizona->regmap, fll->base + 0x11,
1502 ARIZONA_FLL1_SYNC_ENA,
1503 ARIZONA_FLL1_SYNC_ENA);
1505 ret = wait_for_completion_timeout(&fll->ok,
1506 msecs_to_jiffies(250));
1508 arizona_fll_warn(fll, "Timed out waiting for lock\n");
1511 static void arizona_disable_fll(struct arizona_fll *fll)
1513 struct arizona *arizona = fll->arizona;
1516 regmap_update_bits_check(arizona->regmap, fll->base + 1,
1517 ARIZONA_FLL1_ENA, 0, &change);
1518 regmap_update_bits(arizona->regmap, fll->base + 0x11,
1519 ARIZONA_FLL1_SYNC_ENA, 0);
1522 pm_runtime_put_autosuspend(arizona->dev);
1525 int arizona_set_fll_refclk(struct arizona_fll *fll, int source,
1526 unsigned int Fref, unsigned int Fout)
1528 struct arizona_fll_cfg ref, sync;
1531 if (fll->ref_src == source && fll->ref_freq == Fref)
1534 if (fll->fout && Fref > 0) {
1535 ret = arizona_calc_fll(fll, &ref, Fref, fll->fout);
1539 if (fll->sync_src >= 0) {
1540 ret = arizona_calc_fll(fll, &sync, fll->sync_freq,
1547 fll->ref_src = source;
1548 fll->ref_freq = Fref;
1550 if (fll->fout && Fref > 0) {
1551 arizona_enable_fll(fll, &ref, &sync);
1556 EXPORT_SYMBOL_GPL(arizona_set_fll_refclk);
1558 int arizona_set_fll(struct arizona_fll *fll, int source,
1559 unsigned int Fref, unsigned int Fout)
1561 struct arizona_fll_cfg ref, sync;
1564 if (fll->sync_src == source &&
1565 fll->sync_freq == Fref && fll->fout == Fout)
1569 if (fll->ref_src >= 0) {
1570 ret = arizona_calc_fll(fll, &ref, fll->ref_freq,
1576 ret = arizona_calc_fll(fll, &sync, Fref, Fout);
1581 fll->sync_src = source;
1582 fll->sync_freq = Fref;
1586 arizona_enable_fll(fll, &ref, &sync);
1588 arizona_disable_fll(fll);
1593 EXPORT_SYMBOL_GPL(arizona_set_fll);
1595 int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
1596 int ok_irq, struct arizona_fll *fll)
1601 init_completion(&fll->ok);
1605 fll->arizona = arizona;
1606 fll->sync_src = ARIZONA_FLL_SRC_NONE;
1608 /* Configure default refclk to 32kHz if we have one */
1609 regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val);
1610 switch (val & ARIZONA_CLK_32K_SRC_MASK) {
1611 case ARIZONA_CLK_SRC_MCLK1:
1612 case ARIZONA_CLK_SRC_MCLK2:
1613 fll->ref_src = val & ARIZONA_CLK_32K_SRC_MASK;
1616 fll->ref_src = ARIZONA_FLL_SRC_NONE;
1618 fll->ref_freq = 32768;
1620 snprintf(fll->lock_name, sizeof(fll->lock_name), "FLL%d lock", id);
1621 snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name),
1622 "FLL%d clock OK", id);
1624 ret = arizona_request_irq(arizona, ok_irq, fll->clock_ok_name,
1625 arizona_fll_clock_ok, fll);
1627 dev_err(arizona->dev, "Failed to get FLL%d clock OK IRQ: %d\n",
1631 regmap_update_bits(arizona->regmap, fll->base + 1,
1632 ARIZONA_FLL1_FREERUN, 0);
1636 EXPORT_SYMBOL_GPL(arizona_init_fll);
1639 * arizona_set_output_mode - Set the mode of the specified output
1641 * @codec: Device to configure
1642 * @output: Output number
1643 * @diff: True to set the output to differential mode
1645 * Some systems use external analogue switches to connect more
1646 * analogue devices to the CODEC than are supported by the device. In
1647 * some systems this requires changing the switched output from single
1648 * ended to differential mode dynamically at runtime, an operation
1649 * supported using this function.
1651 * Most systems have a single static configuration and should use
1652 * platform data instead.
1654 int arizona_set_output_mode(struct snd_soc_codec *codec, int output, bool diff)
1656 unsigned int reg, val;
1658 if (output < 1 || output > 6)
1661 reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8;
1664 val = ARIZONA_OUT1_MONO;
1668 return snd_soc_update_bits(codec, reg, ARIZONA_OUT1_MONO, val);
1670 EXPORT_SYMBOL_GPL(arizona_set_output_mode);
1672 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
1673 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1674 MODULE_LICENSE("GPL");