2 * C-Media CMI8788 driver - PCM code
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <sound/control.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
27 /* most DMA channels have a 16-bit counter for 32-bit words */
28 #define BUFFER_BYTES_MAX ((1 << 16) * 4)
29 /* the multichannel DMA channel has a 24-bit counter */
30 #define BUFFER_BYTES_MAX_MULTICH ((1 << 24) * 4)
32 #define PERIOD_BYTES_MIN 64
34 #define DEFAULT_BUFFER_BYTES (BUFFER_BYTES_MAX / 2)
35 #define DEFAULT_BUFFER_BYTES_MULTICH (1024 * 1024)
37 static const struct snd_pcm_hardware oxygen_stereo_hardware = {
38 .info = SNDRV_PCM_INFO_MMAP |
39 SNDRV_PCM_INFO_MMAP_VALID |
40 SNDRV_PCM_INFO_INTERLEAVED |
41 SNDRV_PCM_INFO_PAUSE |
42 SNDRV_PCM_INFO_SYNC_START |
43 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
44 .formats = SNDRV_PCM_FMTBIT_S16_LE |
45 SNDRV_PCM_FMTBIT_S32_LE,
46 .rates = SNDRV_PCM_RATE_32000 |
47 SNDRV_PCM_RATE_44100 |
48 SNDRV_PCM_RATE_48000 |
49 SNDRV_PCM_RATE_64000 |
50 SNDRV_PCM_RATE_88200 |
51 SNDRV_PCM_RATE_96000 |
52 SNDRV_PCM_RATE_176400 |
53 SNDRV_PCM_RATE_192000,
58 .buffer_bytes_max = BUFFER_BYTES_MAX,
59 .period_bytes_min = PERIOD_BYTES_MIN,
60 .period_bytes_max = BUFFER_BYTES_MAX,
62 .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
64 static const struct snd_pcm_hardware oxygen_multichannel_hardware = {
65 .info = SNDRV_PCM_INFO_MMAP |
66 SNDRV_PCM_INFO_MMAP_VALID |
67 SNDRV_PCM_INFO_INTERLEAVED |
68 SNDRV_PCM_INFO_PAUSE |
69 SNDRV_PCM_INFO_SYNC_START |
70 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
71 .formats = SNDRV_PCM_FMTBIT_S16_LE |
72 SNDRV_PCM_FMTBIT_S32_LE,
73 .rates = SNDRV_PCM_RATE_32000 |
74 SNDRV_PCM_RATE_44100 |
75 SNDRV_PCM_RATE_48000 |
76 SNDRV_PCM_RATE_64000 |
77 SNDRV_PCM_RATE_88200 |
78 SNDRV_PCM_RATE_96000 |
79 SNDRV_PCM_RATE_176400 |
80 SNDRV_PCM_RATE_192000,
85 .buffer_bytes_max = BUFFER_BYTES_MAX_MULTICH,
86 .period_bytes_min = PERIOD_BYTES_MIN,
87 .period_bytes_max = BUFFER_BYTES_MAX_MULTICH,
89 .periods_max = BUFFER_BYTES_MAX_MULTICH / PERIOD_BYTES_MIN,
91 static const struct snd_pcm_hardware oxygen_ac97_hardware = {
92 .info = SNDRV_PCM_INFO_MMAP |
93 SNDRV_PCM_INFO_MMAP_VALID |
94 SNDRV_PCM_INFO_INTERLEAVED |
95 SNDRV_PCM_INFO_PAUSE |
96 SNDRV_PCM_INFO_SYNC_START |
97 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
98 .formats = SNDRV_PCM_FMTBIT_S16_LE,
99 .rates = SNDRV_PCM_RATE_48000,
104 .buffer_bytes_max = BUFFER_BYTES_MAX,
105 .period_bytes_min = PERIOD_BYTES_MIN,
106 .period_bytes_max = BUFFER_BYTES_MAX,
108 .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
111 static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = {
112 [PCM_A] = &oxygen_stereo_hardware,
113 [PCM_B] = &oxygen_stereo_hardware,
114 [PCM_C] = &oxygen_stereo_hardware,
115 [PCM_SPDIF] = &oxygen_stereo_hardware,
116 [PCM_MULTICH] = &oxygen_multichannel_hardware,
117 [PCM_AC97] = &oxygen_ac97_hardware,
120 static inline unsigned int
121 oxygen_substream_channel(struct snd_pcm_substream *substream)
123 return (unsigned int)(uintptr_t)substream->runtime->private_data;
126 static int oxygen_open(struct snd_pcm_substream *substream,
127 unsigned int channel)
129 struct oxygen *chip = snd_pcm_substream_chip(substream);
130 struct snd_pcm_runtime *runtime = substream->runtime;
133 runtime->private_data = (void *)(uintptr_t)channel;
134 if (channel == PCM_B && chip->has_ac97_1 &&
135 (chip->model.device_config & CAPTURE_2_FROM_AC97_1))
136 runtime->hw = oxygen_ac97_hardware;
138 runtime->hw = *oxygen_hardware[channel];
141 runtime->hw.rates &= ~(SNDRV_PCM_RATE_32000 |
142 SNDRV_PCM_RATE_64000);
143 runtime->hw.rate_min = 44100;
146 runtime->hw.channels_max = chip->model.dac_channels;
149 if (chip->model.pcm_hardware_filter)
150 chip->model.pcm_hardware_filter(channel, &runtime->hw);
151 err = snd_pcm_hw_constraint_step(runtime, 0,
152 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
155 err = snd_pcm_hw_constraint_step(runtime, 0,
156 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
159 if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
160 err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
164 if (runtime->hw.channels_max > 2) {
165 err = snd_pcm_hw_constraint_step(runtime, 0,
166 SNDRV_PCM_HW_PARAM_CHANNELS,
171 if (channel == PCM_MULTICH) {
172 err = snd_pcm_hw_constraint_minmax
173 (runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 0, 8192000);
177 snd_pcm_set_sync(substream);
178 chip->streams[channel] = substream;
180 mutex_lock(&chip->mutex);
181 chip->pcm_active |= 1 << channel;
182 if (channel == PCM_SPDIF) {
183 chip->spdif_pcm_bits = chip->spdif_bits;
184 chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
185 ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
186 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
187 SNDRV_CTL_EVENT_MASK_INFO,
188 &chip->controls[CONTROL_SPDIF_PCM]->id);
190 mutex_unlock(&chip->mutex);
195 static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
197 return oxygen_open(substream, PCM_A);
200 static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
202 return oxygen_open(substream, PCM_B);
205 static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
207 return oxygen_open(substream, PCM_C);
210 static int oxygen_spdif_open(struct snd_pcm_substream *substream)
212 return oxygen_open(substream, PCM_SPDIF);
215 static int oxygen_multich_open(struct snd_pcm_substream *substream)
217 return oxygen_open(substream, PCM_MULTICH);
220 static int oxygen_ac97_open(struct snd_pcm_substream *substream)
222 return oxygen_open(substream, PCM_AC97);
225 static int oxygen_close(struct snd_pcm_substream *substream)
227 struct oxygen *chip = snd_pcm_substream_chip(substream);
228 unsigned int channel = oxygen_substream_channel(substream);
230 mutex_lock(&chip->mutex);
231 chip->pcm_active &= ~(1 << channel);
232 if (channel == PCM_SPDIF) {
233 chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
234 SNDRV_CTL_ELEM_ACCESS_INACTIVE;
235 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
236 SNDRV_CTL_EVENT_MASK_INFO,
237 &chip->controls[CONTROL_SPDIF_PCM]->id);
239 if (channel == PCM_SPDIF || channel == PCM_MULTICH)
240 oxygen_update_spdif_source(chip);
241 mutex_unlock(&chip->mutex);
243 chip->streams[channel] = NULL;
247 static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
249 if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
250 return OXYGEN_FORMAT_24;
252 return OXYGEN_FORMAT_16;
255 static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
257 switch (params_rate(hw_params)) {
259 return OXYGEN_RATE_32000;
261 return OXYGEN_RATE_44100;
263 return OXYGEN_RATE_48000;
265 return OXYGEN_RATE_64000;
267 return OXYGEN_RATE_88200;
269 return OXYGEN_RATE_96000;
271 return OXYGEN_RATE_176400;
273 return OXYGEN_RATE_192000;
277 unsigned int oxygen_default_i2s_mclk(struct oxygen *chip,
278 unsigned int channel,
279 struct snd_pcm_hw_params *hw_params)
281 if (params_rate(hw_params) <= 96000)
282 return OXYGEN_I2S_MCLK_256;
284 return OXYGEN_I2S_MCLK_128;
286 EXPORT_SYMBOL(oxygen_default_i2s_mclk);
288 static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
290 if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
291 return OXYGEN_I2S_BITS_24;
293 return OXYGEN_I2S_BITS_16;
296 static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
298 switch (params_channels(hw_params)) {
300 return OXYGEN_PLAY_CHANNELS_2;
302 return OXYGEN_PLAY_CHANNELS_4;
304 return OXYGEN_PLAY_CHANNELS_6;
306 return OXYGEN_PLAY_CHANNELS_8;
310 static const unsigned int channel_base_registers[PCM_COUNT] = {
311 [PCM_A] = OXYGEN_DMA_A_ADDRESS,
312 [PCM_B] = OXYGEN_DMA_B_ADDRESS,
313 [PCM_C] = OXYGEN_DMA_C_ADDRESS,
314 [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
315 [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
316 [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
319 static int oxygen_hw_params(struct snd_pcm_substream *substream,
320 struct snd_pcm_hw_params *hw_params)
322 struct oxygen *chip = snd_pcm_substream_chip(substream);
323 unsigned int channel = oxygen_substream_channel(substream);
326 err = snd_pcm_lib_malloc_pages(substream,
327 params_buffer_bytes(hw_params));
331 oxygen_write32(chip, channel_base_registers[channel],
332 (u32)substream->runtime->dma_addr);
333 if (channel == PCM_MULTICH) {
334 oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
335 params_buffer_bytes(hw_params) / 4 - 1);
336 oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
337 params_period_bytes(hw_params) / 4 - 1);
339 oxygen_write16(chip, channel_base_registers[channel] + 4,
340 params_buffer_bytes(hw_params) / 4 - 1);
341 oxygen_write16(chip, channel_base_registers[channel] + 6,
342 params_period_bytes(hw_params) / 4 - 1);
347 static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
348 struct snd_pcm_hw_params *hw_params)
350 struct oxygen *chip = snd_pcm_substream_chip(substream);
353 err = oxygen_hw_params(substream, hw_params);
357 spin_lock_irq(&chip->reg_lock);
358 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
359 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
360 OXYGEN_REC_FORMAT_A_MASK);
361 oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
362 oxygen_rate(hw_params) |
363 chip->model.get_i2s_mclk(chip, PCM_A, hw_params) |
364 chip->model.adc_i2s_format |
365 oxygen_i2s_bits(hw_params),
366 OXYGEN_I2S_RATE_MASK |
367 OXYGEN_I2S_FORMAT_MASK |
368 OXYGEN_I2S_MCLK_MASK |
369 OXYGEN_I2S_BITS_MASK);
370 spin_unlock_irq(&chip->reg_lock);
372 mutex_lock(&chip->mutex);
373 chip->model.set_adc_params(chip, hw_params);
374 mutex_unlock(&chip->mutex);
378 static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
379 struct snd_pcm_hw_params *hw_params)
381 struct oxygen *chip = snd_pcm_substream_chip(substream);
385 err = oxygen_hw_params(substream, hw_params);
389 is_ac97 = chip->has_ac97_1 &&
390 (chip->model.device_config & CAPTURE_2_FROM_AC97_1);
392 spin_lock_irq(&chip->reg_lock);
393 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
394 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
395 OXYGEN_REC_FORMAT_B_MASK);
397 oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
398 oxygen_rate(hw_params) |
399 chip->model.get_i2s_mclk(chip, PCM_B,
401 chip->model.adc_i2s_format |
402 oxygen_i2s_bits(hw_params),
403 OXYGEN_I2S_RATE_MASK |
404 OXYGEN_I2S_FORMAT_MASK |
405 OXYGEN_I2S_MCLK_MASK |
406 OXYGEN_I2S_BITS_MASK);
407 spin_unlock_irq(&chip->reg_lock);
410 mutex_lock(&chip->mutex);
411 chip->model.set_adc_params(chip, hw_params);
412 mutex_unlock(&chip->mutex);
417 static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
418 struct snd_pcm_hw_params *hw_params)
420 struct oxygen *chip = snd_pcm_substream_chip(substream);
423 err = oxygen_hw_params(substream, hw_params);
427 spin_lock_irq(&chip->reg_lock);
428 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
429 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
430 OXYGEN_REC_FORMAT_C_MASK);
431 spin_unlock_irq(&chip->reg_lock);
435 static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
436 struct snd_pcm_hw_params *hw_params)
438 struct oxygen *chip = snd_pcm_substream_chip(substream);
441 err = oxygen_hw_params(substream, hw_params);
445 mutex_lock(&chip->mutex);
446 spin_lock_irq(&chip->reg_lock);
447 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
448 OXYGEN_SPDIF_OUT_ENABLE);
449 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
450 oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
451 OXYGEN_SPDIF_FORMAT_MASK);
452 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
453 oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
454 OXYGEN_SPDIF_OUT_RATE_MASK);
455 oxygen_update_spdif_source(chip);
456 spin_unlock_irq(&chip->reg_lock);
457 mutex_unlock(&chip->mutex);
461 static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
462 struct snd_pcm_hw_params *hw_params)
464 struct oxygen *chip = snd_pcm_substream_chip(substream);
467 err = oxygen_hw_params(substream, hw_params);
471 mutex_lock(&chip->mutex);
472 spin_lock_irq(&chip->reg_lock);
473 oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
474 oxygen_play_channels(hw_params),
475 OXYGEN_PLAY_CHANNELS_MASK);
476 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
477 oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
478 OXYGEN_MULTICH_FORMAT_MASK);
479 oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
480 oxygen_rate(hw_params) |
481 chip->model.dac_i2s_format |
482 chip->model.get_i2s_mclk(chip, PCM_MULTICH,
484 oxygen_i2s_bits(hw_params),
485 OXYGEN_I2S_RATE_MASK |
486 OXYGEN_I2S_FORMAT_MASK |
487 OXYGEN_I2S_MCLK_MASK |
488 OXYGEN_I2S_BITS_MASK);
489 oxygen_update_spdif_source(chip);
490 spin_unlock_irq(&chip->reg_lock);
492 chip->model.set_dac_params(chip, hw_params);
493 oxygen_update_dac_routing(chip);
494 mutex_unlock(&chip->mutex);
498 static int oxygen_hw_free(struct snd_pcm_substream *substream)
500 struct oxygen *chip = snd_pcm_substream_chip(substream);
501 unsigned int channel = oxygen_substream_channel(substream);
502 unsigned int channel_mask = 1 << channel;
504 spin_lock_irq(&chip->reg_lock);
505 chip->interrupt_mask &= ~channel_mask;
506 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
508 oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
509 oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
510 spin_unlock_irq(&chip->reg_lock);
512 return snd_pcm_lib_free_pages(substream);
515 static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
517 struct oxygen *chip = snd_pcm_substream_chip(substream);
519 spin_lock_irq(&chip->reg_lock);
520 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
521 OXYGEN_SPDIF_OUT_ENABLE);
522 spin_unlock_irq(&chip->reg_lock);
523 return oxygen_hw_free(substream);
526 static int oxygen_prepare(struct snd_pcm_substream *substream)
528 struct oxygen *chip = snd_pcm_substream_chip(substream);
529 unsigned int channel = oxygen_substream_channel(substream);
530 unsigned int channel_mask = 1 << channel;
532 spin_lock_irq(&chip->reg_lock);
533 oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
534 oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
536 if (substream->runtime->no_period_wakeup)
537 chip->interrupt_mask &= ~channel_mask;
539 chip->interrupt_mask |= channel_mask;
540 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
541 spin_unlock_irq(&chip->reg_lock);
545 static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
547 struct oxygen *chip = snd_pcm_substream_chip(substream);
548 struct snd_pcm_substream *s;
549 unsigned int mask = 0;
553 case SNDRV_PCM_TRIGGER_STOP:
554 case SNDRV_PCM_TRIGGER_START:
555 case SNDRV_PCM_TRIGGER_SUSPEND:
558 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
559 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
566 snd_pcm_group_for_each_entry(s, substream) {
567 if (snd_pcm_substream_chip(s) == chip) {
568 mask |= 1 << oxygen_substream_channel(s);
569 snd_pcm_trigger_done(s, substream);
573 spin_lock(&chip->reg_lock);
575 if (cmd == SNDRV_PCM_TRIGGER_START)
576 chip->pcm_running |= mask;
578 chip->pcm_running &= ~mask;
579 oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
581 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
582 oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
584 oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
586 spin_unlock(&chip->reg_lock);
590 static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
592 struct oxygen *chip = snd_pcm_substream_chip(substream);
593 struct snd_pcm_runtime *runtime = substream->runtime;
594 unsigned int channel = oxygen_substream_channel(substream);
597 /* no spinlock, this read should be atomic */
598 curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
599 return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
602 static struct snd_pcm_ops oxygen_rec_a_ops = {
603 .open = oxygen_rec_a_open,
604 .close = oxygen_close,
605 .ioctl = snd_pcm_lib_ioctl,
606 .hw_params = oxygen_rec_a_hw_params,
607 .hw_free = oxygen_hw_free,
608 .prepare = oxygen_prepare,
609 .trigger = oxygen_trigger,
610 .pointer = oxygen_pointer,
613 static struct snd_pcm_ops oxygen_rec_b_ops = {
614 .open = oxygen_rec_b_open,
615 .close = oxygen_close,
616 .ioctl = snd_pcm_lib_ioctl,
617 .hw_params = oxygen_rec_b_hw_params,
618 .hw_free = oxygen_hw_free,
619 .prepare = oxygen_prepare,
620 .trigger = oxygen_trigger,
621 .pointer = oxygen_pointer,
624 static struct snd_pcm_ops oxygen_rec_c_ops = {
625 .open = oxygen_rec_c_open,
626 .close = oxygen_close,
627 .ioctl = snd_pcm_lib_ioctl,
628 .hw_params = oxygen_rec_c_hw_params,
629 .hw_free = oxygen_hw_free,
630 .prepare = oxygen_prepare,
631 .trigger = oxygen_trigger,
632 .pointer = oxygen_pointer,
635 static struct snd_pcm_ops oxygen_spdif_ops = {
636 .open = oxygen_spdif_open,
637 .close = oxygen_close,
638 .ioctl = snd_pcm_lib_ioctl,
639 .hw_params = oxygen_spdif_hw_params,
640 .hw_free = oxygen_spdif_hw_free,
641 .prepare = oxygen_prepare,
642 .trigger = oxygen_trigger,
643 .pointer = oxygen_pointer,
646 static struct snd_pcm_ops oxygen_multich_ops = {
647 .open = oxygen_multich_open,
648 .close = oxygen_close,
649 .ioctl = snd_pcm_lib_ioctl,
650 .hw_params = oxygen_multich_hw_params,
651 .hw_free = oxygen_hw_free,
652 .prepare = oxygen_prepare,
653 .trigger = oxygen_trigger,
654 .pointer = oxygen_pointer,
657 static struct snd_pcm_ops oxygen_ac97_ops = {
658 .open = oxygen_ac97_open,
659 .close = oxygen_close,
660 .ioctl = snd_pcm_lib_ioctl,
661 .hw_params = oxygen_hw_params,
662 .hw_free = oxygen_hw_free,
663 .prepare = oxygen_prepare,
664 .trigger = oxygen_trigger,
665 .pointer = oxygen_pointer,
668 static void oxygen_pcm_free(struct snd_pcm *pcm)
670 snd_pcm_lib_preallocate_free_for_all(pcm);
673 int oxygen_pcm_init(struct oxygen *chip)
679 outs = !!(chip->model.device_config & PLAYBACK_0_TO_I2S);
680 ins = !!(chip->model.device_config & (CAPTURE_0_FROM_I2S_1 |
681 CAPTURE_0_FROM_I2S_2));
683 err = snd_pcm_new(chip->card, "Multichannel",
688 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
689 &oxygen_multich_ops);
690 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
691 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
693 else if (chip->model.device_config & CAPTURE_0_FROM_I2S_2)
694 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
696 pcm->private_data = chip;
697 pcm->private_free = oxygen_pcm_free;
698 strcpy(pcm->name, "Multichannel");
700 snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
702 snd_dma_pci_data(chip->pci),
703 DEFAULT_BUFFER_BYTES_MULTICH,
704 BUFFER_BYTES_MAX_MULTICH);
706 snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
708 snd_dma_pci_data(chip->pci),
709 DEFAULT_BUFFER_BYTES,
713 outs = !!(chip->model.device_config & PLAYBACK_1_TO_SPDIF);
714 ins = !!(chip->model.device_config & CAPTURE_1_FROM_SPDIF);
716 err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
720 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
723 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
725 pcm->private_data = chip;
726 pcm->private_free = oxygen_pcm_free;
727 strcpy(pcm->name, "Digital");
728 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
729 snd_dma_pci_data(chip->pci),
730 DEFAULT_BUFFER_BYTES,
734 if (chip->has_ac97_1) {
735 outs = !!(chip->model.device_config & PLAYBACK_2_TO_AC97_1);
736 ins = !!(chip->model.device_config & CAPTURE_2_FROM_AC97_1);
739 ins = !!(chip->model.device_config & CAPTURE_2_FROM_I2S_2);
742 err = snd_pcm_new(chip->card, outs ? "AC97" : "Analog2",
747 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
749 oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
750 OXYGEN_REC_B_ROUTE_AC97_1,
751 OXYGEN_REC_B_ROUTE_MASK);
754 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
756 pcm->private_data = chip;
757 pcm->private_free = oxygen_pcm_free;
758 strcpy(pcm->name, outs ? "Front Panel" : "Analog 2");
759 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
760 snd_dma_pci_data(chip->pci),
761 DEFAULT_BUFFER_BYTES,