Pileus Git - ~andy/linux/blob - sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #include <linux/pm_runtime.h>
  50 #include <linux/clocksource.h>
  51 #include <linux/time.h>
  52 #include <linux/completion.h>
  53
  54 #ifdef CONFIG_X86
  55 /* for snoop control */
  56 #include <asm/pgtable.h>
  57 #include <asm/cacheflush.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <linux/vgaarb.h>
  62 #include <linux/vga_switcheroo.h>
  63 #include <linux/firmware.h>
  64 #include "hda_codec.h"
  65
  66
  67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  70 static char *model[SNDRV_CARDS];
  71 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  72 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  73 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  74 static int probe_only[SNDRV_CARDS];
  75 static int jackpoll_ms[SNDRV_CARDS];
  76 static bool single_cmd;
  77 static int enable_msi = -1;
  78 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  79 static char *patch[SNDRV_CARDS];
  80 #endif
  81 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  82 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  83                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  84 #endif
  85
  86 module_param_array(index, int, NULL, 0444);
  87 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  88 module_param_array(id, charp, NULL, 0444);
  89 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  90 module_param_array(enable, bool, NULL, 0444);
  91 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  92 module_param_array(model, charp, NULL, 0444);
  93 MODULE_PARM_DESC(model, "Use the given board model.");
  94 module_param_array(position_fix, int, NULL, 0444);
  95 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  96                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
  97 module_param_array(bdl_pos_adj, int, NULL, 0644);
  98 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  99 module_param_array(probe_mask, int, NULL, 0444);
 100 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 101 module_param_array(probe_only, int, NULL, 0444);
 102 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 103 module_param_array(jackpoll_ms, int, NULL, 0444);
 104 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 105 module_param(single_cmd, bool, 0444);
 106 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 107                  "(for debugging only).");
 108 module_param(enable_msi, bint, 0444);
 109 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 111 module_param_array(patch, charp, NULL, 0444);
 112 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 113 #endif
 114 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 115 module_param_array(beep_mode, bool, NULL, 0444);
 116 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 117                             "(0=off, 1=on) (default=1).");
 118 #endif
 119
 120 #ifdef CONFIG_PM
 121 static int param_set_xint(const char *val, const struct kernel_param *kp);
 122 static struct kernel_param_ops param_ops_xint = {
 123         .set = param_set_xint,
 124         .get = param_get_int,
 125 };
 126 #define param_check_xint param_check_int
 127
 128 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 129 module_param(power_save, xint, 0644);
 130 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 131                  "(in second, 0 = disable).");
 132
 133 /* reset the HD-audio controller in power save mode.
 134  * this may give more power-saving, but will take longer time to
 135  * wake up.
 136  */
 137 static bool power_save_controller = 1;
 138 module_param(power_save_controller, bool, 0644);
 139 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 140 #endif /* CONFIG_PM */
 141
 142 static int align_buffer_size = -1;
 143 module_param(align_buffer_size, bint, 0644);
 144 MODULE_PARM_DESC(align_buffer_size,
 145                 "Force buffer and period sizes to be multiple of 128 bytes.");
 146
 147 #ifdef CONFIG_X86
 148 static bool hda_snoop = true;
 149 module_param_named(snoop, hda_snoop, bool, 0444);
 150 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 151 #define azx_snoop(chip)         (chip)->snoop
 152 #else
 153 #define hda_snoop               true
 154 #define azx_snoop(chip)         true
 155 #endif
 156
 157
 158 MODULE_LICENSE("GPL");
 159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 160                          "{Intel, ICH6M},"
 161                          "{Intel, ICH7},"
 162                          "{Intel, ESB2},"
 163                          "{Intel, ICH8},"
 164                          "{Intel, ICH9},"
 165                          "{Intel, ICH10},"
 166                          "{Intel, PCH},"
 167                          "{Intel, CPT},"
 168                          "{Intel, PPT},"
 169                          "{Intel, LPT},"
 170                          "{Intel, LPT_LP},"
 171                          "{Intel, HPT},"
 172                          "{Intel, PBG},"
 173                          "{Intel, SCH},"
 174                          "{ATI, SB450},"
 175                          "{ATI, SB600},"
 176                          "{ATI, RS600},"
 177                          "{ATI, RS690},"
 178                          "{ATI, RS780},"
 179                          "{ATI, R600},"
 180                          "{ATI, RV630},"
 181                          "{ATI, RV610},"
 182                          "{ATI, RV670},"
 183                          "{ATI, RV635},"
 184                          "{ATI, RV620},"
 185                          "{ATI, RV770},"
 186                          "{VIA, VT8251},"
 187                          "{VIA, VT8237A},"
 188                          "{SiS, SIS966},"
 189                          "{ULI, M5461}}");
 190 MODULE_DESCRIPTION("Intel HDA driver");
 191
 192 #ifdef CONFIG_SND_VERBOSE_PRINTK
 193 #define SFX     /* nop */
 194 #else
 195 #define SFX     "hda-intel: "
 196 #endif
 197
 198 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 199 #ifdef CONFIG_SND_HDA_CODEC_HDMI
 200 #define SUPPORT_VGA_SWITCHEROO
 201 #endif
 202 #endif
 203
 204
 205 /*
 206  * registers
 207  */
 208 #define ICH6_REG_GCAP                   0x00
 209 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 210 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 211 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 212 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 213 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 214 #define ICH6_REG_VMIN                   0x02
 215 #define ICH6_REG_VMAJ                   0x03
 216 #define ICH6_REG_OUTPAY                 0x04
 217 #define ICH6_REG_INPAY                  0x06
 218 #define ICH6_REG_GCTL                   0x08
 219 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 220 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 221 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 222 #define ICH6_REG_WAKEEN                 0x0c
 223 #define ICH6_REG_STATESTS               0x0e
 224 #define ICH6_REG_GSTS                   0x10
 225 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 226 #define ICH6_REG_INTCTL                 0x20
 227 #define ICH6_REG_INTSTS                 0x24
 228 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 229 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 230 #define ICH6_REG_SSYNC                  0x38
 231 #define ICH6_REG_CORBLBASE              0x40
 232 #define ICH6_REG_CORBUBASE              0x44
 233 #define ICH6_REG_CORBWP                 0x48
 234 #define ICH6_REG_CORBRP                 0x4a
 235 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 236 #define ICH6_REG_CORBCTL                0x4c
 237 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 238 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 239 #define ICH6_REG_CORBSTS                0x4d
 240 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 241 #define ICH6_REG_CORBSIZE               0x4e
 242
 243 #define ICH6_REG_RIRBLBASE              0x50
 244 #define ICH6_REG_RIRBUBASE              0x54
 245 #define ICH6_REG_RIRBWP                 0x58
 246 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 247 #define ICH6_REG_RINTCNT                0x5a
 248 #define ICH6_REG_RIRBCTL                0x5c
 249 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 250 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 251 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 252 #define ICH6_REG_RIRBSTS                0x5d
 253 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 254 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 255 #define ICH6_REG_RIRBSIZE               0x5e
 256
 257 #define ICH6_REG_IC                     0x60
 258 #define ICH6_REG_IR                     0x64
 259 #define ICH6_REG_IRS                    0x68
 260 #define   ICH6_IRS_VALID        (1<<1)
 261 #define   ICH6_IRS_BUSY         (1<<0)
 262
 263 #define ICH6_REG_DPLBASE                0x70
 264 #define ICH6_REG_DPUBASE                0x74
 265 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 266
 267 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 268 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 269
 270 /* stream register offsets from stream base */
 271 #define ICH6_REG_SD_CTL                 0x00
 272 #define ICH6_REG_SD_STS                 0x03
 273 #define ICH6_REG_SD_LPIB                0x04
 274 #define ICH6_REG_SD_CBL                 0x08
 275 #define ICH6_REG_SD_LVI                 0x0c
 276 #define ICH6_REG_SD_FIFOW               0x0e
 277 #define ICH6_REG_SD_FIFOSIZE            0x10
 278 #define ICH6_REG_SD_FORMAT              0x12
 279 #define ICH6_REG_SD_BDLPL               0x18
 280 #define ICH6_REG_SD_BDLPU               0x1c
 281
 282 /* PCI space */
 283 #define ICH6_PCIREG_TCSEL       0x44
 284
 285 /*
 286  * other constants
 287  */
 288
 289 /* max number of SDs */
 290 /* ICH, ATI and VIA have 4 playback and 4 capture */
 291 #define ICH6_NUM_CAPTURE        4
 292 #define ICH6_NUM_PLAYBACK       4
 293
 294 /* ULI has 6 playback and 5 capture */
 295 #define ULI_NUM_CAPTURE         5
 296 #define ULI_NUM_PLAYBACK        6
 297
 298 /* ATI HDMI has 1 playback and 0 capture */
 299 #define ATIHDMI_NUM_CAPTURE     0
 300 #define ATIHDMI_NUM_PLAYBACK    1
 301
 302 /* TERA has 4 playback and 3 capture */
 303 #define TERA_NUM_CAPTURE        3
 304 #define TERA_NUM_PLAYBACK       4
 305
 306 /* this number is statically defined for simplicity */
 307 #define MAX_AZX_DEV             16
 308
 309 /* max number of fragments - we may use more if allocating more pages for BDL */
 310 #define BDL_SIZE                4096
 311 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 312 #define AZX_MAX_FRAG            32
 313 /* max buffer size - no h/w limit, you can increase as you like */
 314 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 315
 316 /* RIRB int mask: overrun[2], response[0] */
 317 #define RIRB_INT_RESPONSE       0x01
 318 #define RIRB_INT_OVERRUN        0x04
 319 #define RIRB_INT_MASK           0x05
 320
 321 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 322 #define AZX_MAX_CODECS          8
 323 #define AZX_DEFAULT_CODECS      4
 324 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 325
 326 /* SD_CTL bits */
 327 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 328 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 329 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 330 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 331 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 332 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 333 #define SD_CTL_STREAM_TAG_SHIFT 20
 334
 335 /* SD_CTL and SD_STS */
 336 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 337 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 338 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 339 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 340                                  SD_INT_COMPLETE)
 341
 342 /* SD_STS */
 343 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 344
 345 /* INTCTL and INTSTS */
 346 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 347 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 348 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 349
 350 /* below are so far hardcoded - should read registers in future */
 351 #define ICH6_MAX_CORB_ENTRIES   256
 352 #define ICH6_MAX_RIRB_ENTRIES   256
 353
 354 /* position fix mode */
 355 enum {
 356         POS_FIX_AUTO,
 357         POS_FIX_LPIB,
 358         POS_FIX_POSBUF,
 359         POS_FIX_VIACOMBO,
 360         POS_FIX_COMBO,
 361 };
 362
 363 /* Defines for ATI HD Audio support in SB450 south bridge */
 364 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 365 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 366
 367 /* Defines for Nvidia HDA support */
 368 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 369 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 370 #define NVIDIA_HDA_ISTRM_COH          0x4d
 371 #define NVIDIA_HDA_OSTRM_COH          0x4c
 372 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 373
 374 /* Defines for Intel SCH HDA snoop control */
 375 #define INTEL_SCH_HDA_DEVC      0x78
 376 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 377
 378 /* Define IN stream 0 FIFO size offset in VIA controller */
 379 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 380 /* Define VIA HD Audio Device ID*/
 381 #define VIA_HDAC_DEVICE_ID              0x3288
 382
 383 /* HD Audio class code */
 384 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 385
 386 /*
 387  */
 388
 389 struct azx_dev {
 390         struct snd_dma_buffer bdl; /* BDL buffer */
 391         u32 *posbuf;            /* position buffer pointer */
 392
 393         unsigned int bufsize;   /* size of the play buffer in bytes */
 394         unsigned int period_bytes; /* size of the period in bytes */
 395         unsigned int frags;     /* number for period in the play buffer */
 396         unsigned int fifo_size; /* FIFO size */
 397         unsigned long start_wallclk;    /* start + minimum wallclk */
 398         unsigned long period_wallclk;   /* wallclk for period */
 399
 400         void __iomem *sd_addr;  /* stream descriptor pointer */
 401
 402         u32 sd_int_sta_mask;    /* stream int status mask */
 403
 404         /* pcm support */
 405         struct snd_pcm_substream *substream;    /* assigned substream,
 406                                                  * set in PCM open
 407                                                  */
 408         unsigned int format_val;        /* format value to be set in the
 409                                          * controller and the codec
 410                                          */
 411         unsigned char stream_tag;       /* assigned stream */
 412         unsigned char index;            /* stream index */
 413         int assigned_key;               /* last device# key assigned to */
 414
 415         unsigned int opened :1;
 416         unsigned int running :1;
 417         unsigned int irq_pending :1;
 418         /*
 419          * For VIA:
 420          *  A flag to ensure DMA position is 0
 421          *  when link position is not greater than FIFO size
 422          */
 423         unsigned int insufficient :1;
 424         unsigned int wc_marked:1;
 425         unsigned int no_period_wakeup:1;
 426
 427         struct timecounter  azx_tc;
 428         struct cyclecounter azx_cc;
 429 };
 430
 431 /* CORB/RIRB */
 432 struct azx_rb {
 433         u32 *buf;               /* CORB/RIRB buffer
 434                                  * Each CORB entry is 4byte, RIRB is 8byte
 435                                  */
 436         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 437         /* for RIRB */
 438         unsigned short rp, wp;  /* read/write pointers */
 439         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 440         u32 res[AZX_MAX_CODECS];        /* last read value */
 441 };
 442
 443 struct azx_pcm {
 444         struct azx *chip;
 445         struct snd_pcm *pcm;
 446         struct hda_codec *codec;
 447         struct hda_pcm_stream *hinfo[2];
 448         struct list_head list;
 449 };
 450
 451 struct azx {
 452         struct snd_card *card;
 453         struct pci_dev *pci;
 454         int dev_index;
 455
 456         /* chip type specific */
 457         int driver_type;
 458         unsigned int driver_caps;
 459         int playback_streams;
 460         int playback_index_offset;
 461         int capture_streams;
 462         int capture_index_offset;
 463         int num_streams;
 464
 465         /* pci resources */
 466         unsigned long addr;
 467         void __iomem *remap_addr;
 468         int irq;
 469
 470         /* locks */
 471         spinlock_t reg_lock;
 472         struct mutex open_mutex;
 473         struct completion probe_wait;
 474
 475         /* streams (x num_streams) */
 476         struct azx_dev *azx_dev;
 477
 478         /* PCM */
 479         struct list_head pcm_list; /* azx_pcm list */
 480
 481         /* HD codec */
 482         unsigned short codec_mask;
 483         int  codec_probe_mask; /* copied from probe_mask option */
 484         struct hda_bus *bus;
 485         unsigned int beep_mode;
 486
 487         /* CORB/RIRB */
 488         struct azx_rb corb;
 489         struct azx_rb rirb;
 490
 491         /* CORB/RIRB and position buffers */
 492         struct snd_dma_buffer rb;
 493         struct snd_dma_buffer posbuf;
 494
 495 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 496         const struct firmware *fw;
 497 #endif
 498
 499         /* flags */
 500         int position_fix[2]; /* for both playback/capture streams */
 501         int poll_count;
 502         unsigned int running :1;
 503         unsigned int initialized :1;
 504         unsigned int single_cmd :1;
 505         unsigned int polling_mode :1;
 506         unsigned int msi :1;
 507         unsigned int irq_pending_warned :1;
 508         unsigned int probing :1; /* codec probing phase */
 509         unsigned int snoop:1;
 510         unsigned int align_buffer_size:1;
 511         unsigned int region_requested:1;
 512
 513         /* VGA-switcheroo setup */
 514         unsigned int use_vga_switcheroo:1;
 515         unsigned int vga_switcheroo_registered:1;
 516         unsigned int init_failed:1; /* delayed init failed */
 517         unsigned int disabled:1; /* disabled by VGA-switcher */
 518
 519         /* for debugging */
 520         unsigned int last_cmd[AZX_MAX_CODECS];
 521
 522         /* for pending irqs */
 523         struct work_struct irq_pending_work;
 524
 525         /* reboot notifier (for mysterious hangup problem at power-down) */
 526         struct notifier_block reboot_notifier;
 527
 528         /* card list (for power_save trigger) */
 529         struct list_head list;
 530 };
 531
 532 #define CREATE_TRACE_POINTS
 533 #include "hda_intel_trace.h"
 534
 535 /* driver types */
 536 enum {
 537         AZX_DRIVER_ICH,
 538         AZX_DRIVER_PCH,
 539         AZX_DRIVER_SCH,
 540         AZX_DRIVER_ATI,
 541         AZX_DRIVER_ATIHDMI,
 542         AZX_DRIVER_ATIHDMI_NS,
 543         AZX_DRIVER_VIA,
 544         AZX_DRIVER_SIS,
 545         AZX_DRIVER_ULI,
 546         AZX_DRIVER_NVIDIA,
 547         AZX_DRIVER_TERA,
 548         AZX_DRIVER_CTX,
 549         AZX_DRIVER_CTHDA,
 550         AZX_DRIVER_GENERIC,
 551         AZX_NUM_DRIVERS, /* keep this as last entry */
 552 };
 553
 554 /* driver quirks (capabilities) */
 555 /* bits 0-7 are used for indicating driver type */
 556 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 557 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 558 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 559 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 560 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 561 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 562 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 563 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 564 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 565 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 566 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 567 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 568 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 569 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 570 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
 571 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
 572 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
 573 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
 574
 575 /* quirks for Intel PCH */
 576 #define AZX_DCAPS_INTEL_PCH \
 577         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
 578          AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME)
 579
 580 /* quirks for ATI SB / AMD Hudson */
 581 #define AZX_DCAPS_PRESET_ATI_SB \
 582         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 583          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 584
 585 /* quirks for ATI/AMD HDMI */
 586 #define AZX_DCAPS_PRESET_ATI_HDMI \
 587         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 588
 589 /* quirks for Nvidia */
 590 #define AZX_DCAPS_PRESET_NVIDIA \
 591         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
 592          AZX_DCAPS_ALIGN_BUFSIZE)
 593
 594 #define AZX_DCAPS_PRESET_CTHDA \
 595         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
 596
 597 /*
 598  * VGA-switcher support
 599  */
 600 #ifdef SUPPORT_VGA_SWITCHEROO
 601 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 602 #else
 603 #define use_vga_switcheroo(chip)        0
 604 #endif
 605
 606 #if defined(SUPPORT_VGA_SWITCHEROO) || defined(CONFIG_SND_HDA_PATCH_LOADER)
 607 #define DELAYED_INIT_MARK
 608 #define DELAYED_INITDATA_MARK
 609 #else
 610 #define DELAYED_INIT_MARK       __devinit
 611 #define DELAYED_INITDATA_MARK   __devinitdata
 612 #endif
 613
 614 static char *driver_short_names[] DELAYED_INITDATA_MARK = {
 615         [AZX_DRIVER_ICH] = "HDA Intel",
 616         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 617         [AZX_DRIVER_SCH] = "HDA Intel MID",
 618         [AZX_DRIVER_ATI] = "HDA ATI SB",
 619         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 620         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 621         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 622         [AZX_DRIVER_SIS] = "HDA SIS966",
 623         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 624         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 625         [AZX_DRIVER_TERA] = "HDA Teradici",
 626         [AZX_DRIVER_CTX] = "HDA Creative",
 627         [AZX_DRIVER_CTHDA] = "HDA Creative",
 628         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 629 };
 630
 631 /*
 632  * macros for easy use
 633  */
 634 #define azx_writel(chip,reg,value) \
 635         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 636 #define azx_readl(chip,reg) \
 637         readl((chip)->remap_addr + ICH6_REG_##reg)
 638 #define azx_writew(chip,reg,value) \
 639         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 640 #define azx_readw(chip,reg) \
 641         readw((chip)->remap_addr + ICH6_REG_##reg)
 642 #define azx_writeb(chip,reg,value) \
 643         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 644 #define azx_readb(chip,reg) \
 645         readb((chip)->remap_addr + ICH6_REG_##reg)
 646
 647 #define azx_sd_writel(dev,reg,value) \
 648         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 649 #define azx_sd_readl(dev,reg) \
 650         readl((dev)->sd_addr + ICH6_REG_##reg)
 651 #define azx_sd_writew(dev,reg,value) \
 652         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 653 #define azx_sd_readw(dev,reg) \
 654         readw((dev)->sd_addr + ICH6_REG_##reg)
 655 #define azx_sd_writeb(dev,reg,value) \
 656         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 657 #define azx_sd_readb(dev,reg) \
 658         readb((dev)->sd_addr + ICH6_REG_##reg)
 659
 660 /* for pcm support */
 661 #define get_azx_dev(substream) (substream->runtime->private_data)
 662
 663 #ifdef CONFIG_X86
 664 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
 665 {
 666         if (azx_snoop(chip))
 667                 return;
 668         if (addr && size) {
 669                 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 670                 if (on)
 671                         set_memory_wc((unsigned long)addr, pages);
 672                 else
 673                         set_memory_wb((unsigned long)addr, pages);
 674         }
 675 }
 676
 677 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 678                                  bool on)
 679 {
 680         __mark_pages_wc(chip, buf->area, buf->bytes, on);
 681 }
 682 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 683                                    struct snd_pcm_runtime *runtime, bool on)
 684 {
 685         if (azx_dev->wc_marked != on) {
 686                 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
 687                 azx_dev->wc_marked = on;
 688         }
 689 }
 690 #else
 691 /* NOP for other archs */
 692 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 693                                  bool on)
 694 {
 695 }
 696 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 697                                    struct snd_pcm_runtime *runtime, bool on)
 698 {
 699 }
 700 #endif
 701
 702 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 703 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 704 /*
 705  * Interface for HD codec
 706  */
 707
 708 /*
 709  * CORB / RIRB interface
 710  */
 711 static int azx_alloc_cmd_io(struct azx *chip)
 712 {
 713         int err;
 714
 715         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 716         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 717                                   snd_dma_pci_data(chip->pci),
 718                                   PAGE_SIZE, &chip->rb);
 719         if (err < 0) {
 720                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 721                 return err;
 722         }
 723         mark_pages_wc(chip, &chip->rb, true);
 724         return 0;
 725 }
 726
 727 static void azx_init_cmd_io(struct azx *chip)
 728 {
 729         spin_lock_irq(&chip->reg_lock);
 730         /* CORB set up */
 731         chip->corb.addr = chip->rb.addr;
 732         chip->corb.buf = (u32 *)chip->rb.area;
 733         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 734         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 735
 736         /* set the corb size to 256 entries (ULI requires explicitly) */
 737         azx_writeb(chip, CORBSIZE, 0x02);
 738         /* set the corb write pointer to 0 */
 739         azx_writew(chip, CORBWP, 0);
 740         /* reset the corb hw read pointer */
 741         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 742         /* enable corb dma */
 743         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 744
 745         /* RIRB set up */
 746         chip->rirb.addr = chip->rb.addr + 2048;
 747         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 748         chip->rirb.wp = chip->rirb.rp = 0;
 749         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 750         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 751         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 752
 753         /* set the rirb size to 256 entries (ULI requires explicitly) */
 754         azx_writeb(chip, RIRBSIZE, 0x02);
 755         /* reset the rirb hw write pointer */
 756         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 757         /* set N=1, get RIRB response interrupt for new entry */
 758         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 759                 azx_writew(chip, RINTCNT, 0xc0);
 760         else
 761                 azx_writew(chip, RINTCNT, 1);
 762         /* enable rirb dma and response irq */
 763         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 764         spin_unlock_irq(&chip->reg_lock);
 765 }
 766
 767 static void azx_free_cmd_io(struct azx *chip)
 768 {
 769         spin_lock_irq(&chip->reg_lock);
 770         /* disable ringbuffer DMAs */
 771         azx_writeb(chip, RIRBCTL, 0);
 772         azx_writeb(chip, CORBCTL, 0);
 773         spin_unlock_irq(&chip->reg_lock);
 774 }
 775
 776 static unsigned int azx_command_addr(u32 cmd)
 777 {
 778         unsigned int addr = cmd >> 28;
 779
 780         if (addr >= AZX_MAX_CODECS) {
 781                 snd_BUG();
 782                 addr = 0;
 783         }
 784
 785         return addr;
 786 }
 787
 788 static unsigned int azx_response_addr(u32 res)
 789 {
 790         unsigned int addr = res & 0xf;
 791
 792         if (addr >= AZX_MAX_CODECS) {
 793                 snd_BUG();
 794                 addr = 0;
 795         }
 796
 797         return addr;
 798 }
 799
 800 /* send a command */
 801 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 802 {
 803         struct azx *chip = bus->private_data;
 804         unsigned int addr = azx_command_addr(val);
 805         unsigned int wp;
 806
 807         spin_lock_irq(&chip->reg_lock);
 808
 809         /* add command to corb */
 810         wp = azx_readb(chip, CORBWP);
 811         wp++;
 812         wp %= ICH6_MAX_CORB_ENTRIES;
 813
 814         chip->rirb.cmds[addr]++;
 815         chip->corb.buf[wp] = cpu_to_le32(val);
 816         azx_writel(chip, CORBWP, wp);
 817
 818         spin_unlock_irq(&chip->reg_lock);
 819
 820         return 0;
 821 }
 822
 823 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 824
 825 /* retrieve RIRB entry - called from interrupt handler */
 826 static void azx_update_rirb(struct azx *chip)
 827 {
 828         unsigned int rp, wp;
 829         unsigned int addr;
 830         u32 res, res_ex;
 831
 832         wp = azx_readb(chip, RIRBWP);
 833         if (wp == chip->rirb.wp)
 834                 return;
 835         chip->rirb.wp = wp;
 836
 837         while (chip->rirb.rp != wp) {
 838                 chip->rirb.rp++;
 839                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 840
 841                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 842                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 843                 res = le32_to_cpu(chip->rirb.buf[rp]);
 844                 addr = azx_response_addr(res_ex);
 845                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 846                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 847                 else if (chip->rirb.cmds[addr]) {
 848                         chip->rirb.res[addr] = res;
 849                         smp_wmb();
 850                         chip->rirb.cmds[addr]--;
 851                 } else
 852                         snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
 853                                    "last cmd=%#08x\n",
 854                                    pci_name(chip->pci),
 855                                    res, res_ex,
 856                                    chip->last_cmd[addr]);
 857         }
 858 }
 859
 860 /* receive a response */
 861 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 862                                           unsigned int addr)
 863 {
 864         struct azx *chip = bus->private_data;
 865         unsigned long timeout;
 866         unsigned long loopcounter;
 867         int do_poll = 0;
 868
 869  again:
 870         timeout = jiffies + msecs_to_jiffies(1000);
 871
 872         for (loopcounter = 0;; loopcounter++) {
 873                 if (chip->polling_mode || do_poll) {
 874                         spin_lock_irq(&chip->reg_lock);
 875                         azx_update_rirb(chip);
 876                         spin_unlock_irq(&chip->reg_lock);
 877                 }
 878                 if (!chip->rirb.cmds[addr]) {
 879                         smp_rmb();
 880                         bus->rirb_error = 0;
 881
 882                         if (!do_poll)
 883                                 chip->poll_count = 0;
 884                         return chip->rirb.res[addr]; /* the last value */
 885                 }
 886                 if (time_after(jiffies, timeout))
 887                         break;
 888                 if (bus->needs_damn_long_delay || loopcounter > 3000)
 889                         msleep(2); /* temporary workaround */
 890                 else {
 891                         udelay(10);
 892                         cond_resched();
 893                 }
 894         }
 895
 896         if (!chip->polling_mode && chip->poll_count < 2) {
 897                 snd_printdd(SFX "azx_get_response timeout, "
 898                            "polling the codec once: last cmd=0x%08x\n",
 899                            chip->last_cmd[addr]);
 900                 do_poll = 1;
 901                 chip->poll_count++;
 902                 goto again;
 903         }
 904
 905
 906         if (!chip->polling_mode) {
 907                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 908                            "switching to polling mode: last cmd=0x%08x\n",
 909                            chip->last_cmd[addr]);
 910                 chip->polling_mode = 1;
 911                 goto again;
 912         }
 913
 914         if (chip->msi) {
 915                 snd_printk(KERN_WARNING SFX "No response from codec, "
 916                            "disabling MSI: last cmd=0x%08x\n",
 917                            chip->last_cmd[addr]);
 918                 free_irq(chip->irq, chip);
 919                 chip->irq = -1;
 920                 pci_disable_msi(chip->pci);
 921                 chip->msi = 0;
 922                 if (azx_acquire_irq(chip, 1) < 0) {
 923                         bus->rirb_error = 1;
 924                         return -1;
 925                 }
 926                 goto again;
 927         }
 928
 929         if (chip->probing) {
 930                 /* If this critical timeout happens during the codec probing
 931                  * phase, this is likely an access to a non-existing codec
 932                  * slot.  Better to return an error and reset the system.
 933                  */
 934                 return -1;
 935         }
 936
 937         /* a fatal communication error; need either to reset or to fallback
 938          * to the single_cmd mode
 939          */
 940         bus->rirb_error = 1;
 941         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 942                 bus->response_reset = 1;
 943                 return -1; /* give a chance to retry */
 944         }
 945
 946         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 947                    "switching to single_cmd mode: last cmd=0x%08x\n",
 948                    chip->last_cmd[addr]);
 949         chip->single_cmd = 1;
 950         bus->response_reset = 0;
 951         /* release CORB/RIRB */
 952         azx_free_cmd_io(chip);
 953         /* disable unsolicited responses */
 954         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 955         return -1;
 956 }
 957
 958 /*
 959  * Use the single immediate command instead of CORB/RIRB for simplicity
 960  *
 961  * Note: according to Intel, this is not preferred use.  The command was
 962  *       intended for the BIOS only, and may get confused with unsolicited
 963  *       responses.  So, we shouldn't use it for normal operation from the
 964  *       driver.
 965  *       I left the codes, however, for debugging/testing purposes.
 966  */
 967
 968 /* receive a response */
 969 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 970 {
 971         int timeout = 50;
 972
 973         while (timeout--) {
 974                 /* check IRV busy bit */
 975                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 976                         /* reuse rirb.res as the response return value */
 977                         chip->rirb.res[addr] = azx_readl(chip, IR);
 978                         return 0;
 979                 }
 980                 udelay(1);
 981         }
 982         if (printk_ratelimit())
 983                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 984                            azx_readw(chip, IRS));
 985         chip->rirb.res[addr] = -1;
 986         return -EIO;
 987 }
 988
 989 /* send a command */
 990 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 991 {
 992         struct azx *chip = bus->private_data;
 993         unsigned int addr = azx_command_addr(val);
 994         int timeout = 50;
 995
 996         bus->rirb_error = 0;
 997         while (timeout--) {
 998                 /* check ICB busy bit */
 999                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1000                         /* Clear IRV valid bit */
1001                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1002                                    ICH6_IRS_VALID);
1003                         azx_writel(chip, IC, val);
1004                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1005                                    ICH6_IRS_BUSY);
1006                         return azx_single_wait_for_response(chip, addr);
1007                 }
1008                 udelay(1);
1009         }
1010         if (printk_ratelimit())
1011                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
1012                            azx_readw(chip, IRS), val);
1013         return -EIO;
1014 }
1015
1016 /* receive a response */
1017 static unsigned int azx_single_get_response(struct hda_bus *bus,
1018                                             unsigned int addr)
1019 {
1020         struct azx *chip = bus->private_data;
1021         return chip->rirb.res[addr];
1022 }
1023
1024 /*
1025  * The below are the main callbacks from hda_codec.
1026  *
1027  * They are just the skeleton to call sub-callbacks according to the
1028  * current setting of chip->single_cmd.
1029  */
1030
1031 /* send a command */
1032 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1033 {
1034         struct azx *chip = bus->private_data;
1035
1036         if (chip->disabled)
1037                 return 0;
1038         chip->last_cmd[azx_command_addr(val)] = val;
1039         if (chip->single_cmd)
1040                 return azx_single_send_cmd(bus, val);
1041         else
1042                 return azx_corb_send_cmd(bus, val);
1043 }
1044
1045 /* get a response */
1046 static unsigned int azx_get_response(struct hda_bus *bus,
1047                                      unsigned int addr)
1048 {
1049         struct azx *chip = bus->private_data;
1050         if (chip->disabled)
1051                 return 0;
1052         if (chip->single_cmd)
1053                 return azx_single_get_response(bus, addr);
1054         else
1055                 return azx_rirb_get_response(bus, addr);
1056 }
1057
1058 #ifdef CONFIG_PM
1059 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1060 #endif
1061
1062 /* reset codec link */
1063 static int azx_reset(struct azx *chip, int full_reset)
1064 {
1065         int count;
1066
1067         if (!full_reset)
1068                 goto __skip;
1069
1070         /* clear STATESTS */
1071         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1072
1073         /* reset controller */
1074         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1075
1076         count = 50;
1077         while (azx_readb(chip, GCTL) && --count)
1078                 msleep(1);
1079
1080         /* delay for >= 100us for codec PLL to settle per spec
1081          * Rev 0.9 section 5.5.1
1082          */
1083         msleep(1);
1084
1085         /* Bring controller out of reset */
1086         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1087
1088         count = 50;
1089         while (!azx_readb(chip, GCTL) && --count)
1090                 msleep(1);
1091
1092         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1093         msleep(1);
1094
1095       __skip:
1096         /* check to see if controller is ready */
1097         if (!azx_readb(chip, GCTL)) {
1098                 snd_printd(SFX "azx_reset: controller not ready!\n");
1099                 return -EBUSY;
1100         }
1101
1102         /* Accept unsolicited responses */
1103         if (!chip->single_cmd)
1104                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1105                            ICH6_GCTL_UNSOL);
1106
1107         /* detect codecs */
1108         if (!chip->codec_mask) {
1109                 chip->codec_mask = azx_readw(chip, STATESTS);
1110                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1111         }
1112
1113         return 0;
1114 }
1115
1116
1117 /*
1118  * Lowlevel interface
1119  */
1120
1121 /* enable interrupts */
1122 static void azx_int_enable(struct azx *chip)
1123 {
1124         /* enable controller CIE and GIE */
1125         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1126                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1127 }
1128
1129 /* disable interrupts */
1130 static void azx_int_disable(struct azx *chip)
1131 {
1132         int i;
1133
1134         /* disable interrupts in stream descriptor */
1135         for (i = 0; i < chip->num_streams; i++) {
1136                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1137                 azx_sd_writeb(azx_dev, SD_CTL,
1138                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1139         }
1140
1141         /* disable SIE for all streams */
1142         azx_writeb(chip, INTCTL, 0);
1143
1144         /* disable controller CIE and GIE */
1145         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1146                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1147 }
1148
1149 /* clear interrupts */
1150 static void azx_int_clear(struct azx *chip)
1151 {
1152         int i;
1153
1154         /* clear stream status */
1155         for (i = 0; i < chip->num_streams; i++) {
1156                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1157                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1158         }
1159
1160         /* clear STATESTS */
1161         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1162
1163         /* clear rirb status */
1164         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1165
1166         /* clear int status */
1167         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1168 }
1169
1170 /* start a stream */
1171 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1172 {
1173         /*
1174          * Before stream start, initialize parameter
1175          */
1176         azx_dev->insufficient = 1;
1177
1178         /* enable SIE */
1179         azx_writel(chip, INTCTL,
1180                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1181         /* set DMA start and interrupt mask */
1182         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1183                       SD_CTL_DMA_START | SD_INT_MASK);
1184 }
1185
1186 /* stop DMA */
1187 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1188 {
1189         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1190                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1191         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1192 }
1193
1194 /* stop a stream */
1195 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1196 {
1197         azx_stream_clear(chip, azx_dev);
1198         /* disable SIE */
1199         azx_writel(chip, INTCTL,
1200                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1201 }
1202
1203
1204 /*
1205  * reset and start the controller registers
1206  */
1207 static void azx_init_chip(struct azx *chip, int full_reset)
1208 {
1209         if (chip->initialized)
1210                 return;
1211
1212         /* reset controller */
1213         azx_reset(chip, full_reset);
1214
1215         /* initialize interrupts */
1216         azx_int_clear(chip);
1217         azx_int_enable(chip);
1218
1219         /* initialize the codec command I/O */
1220         if (!chip->single_cmd)
1221                 azx_init_cmd_io(chip);
1222
1223         /* program the position buffer */
1224         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1225         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1226
1227         chip->initialized = 1;
1228 }
1229
1230 /*
1231  * initialize the PCI registers
1232  */
1233 /* update bits in a PCI register byte */
1234 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1235                             unsigned char mask, unsigned char val)
1236 {
1237         unsigned char data;
1238
1239         pci_read_config_byte(pci, reg, &data);
1240         data &= ~mask;
1241         data |= (val & mask);
1242         pci_write_config_byte(pci, reg, data);
1243 }
1244
1245 static void azx_init_pci(struct azx *chip)
1246 {
1247         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1248          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1249          * Ensuring these bits are 0 clears playback static on some HD Audio
1250          * codecs.
1251          * The PCI register TCSEL is defined in the Intel manuals.
1252          */
1253         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1254                 snd_printdd(SFX "Clearing TCSEL\n");
1255                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1256         }
1257
1258         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1259          * we need to enable snoop.
1260          */
1261         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1262                 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1263                 update_pci_byte(chip->pci,
1264                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1265                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1266         }
1267
1268         /* For NVIDIA HDA, enable snoop */
1269         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1270                 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1271                 update_pci_byte(chip->pci,
1272                                 NVIDIA_HDA_TRANSREG_ADDR,
1273                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1274                 update_pci_byte(chip->pci,
1275                                 NVIDIA_HDA_ISTRM_COH,
1276                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1277                 update_pci_byte(chip->pci,
1278                                 NVIDIA_HDA_OSTRM_COH,
1279                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1280         }
1281
1282         /* Enable SCH/PCH snoop if needed */
1283         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1284                 unsigned short snoop;
1285                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1286                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1287                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1288                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1289                         if (!azx_snoop(chip))
1290                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1291                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1292                         pci_read_config_word(chip->pci,
1293                                 INTEL_SCH_HDA_DEVC, &snoop);
1294                 }
1295                 snd_printdd(SFX "SCH snoop: %s\n",
1296                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1297                                 ? "Disabled" : "Enabled");
1298         }
1299 }
1300
1301
1302 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1303
1304 /*
1305  * interrupt handler
1306  */
1307 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1308 {
1309         struct azx *chip = dev_id;
1310         struct azx_dev *azx_dev;
1311         u32 status;
1312         u8 sd_status;
1313         int i, ok;
1314
1315 #ifdef CONFIG_PM_RUNTIME
1316         if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1317                 return IRQ_NONE;
1318 #endif
1319
1320         spin_lock(&chip->reg_lock);
1321
1322         if (chip->disabled) {
1323                 spin_unlock(&chip->reg_lock);
1324                 return IRQ_NONE;
1325         }
1326
1327         status = azx_readl(chip, INTSTS);
1328         if (status == 0) {
1329                 spin_unlock(&chip->reg_lock);
1330                 return IRQ_NONE;
1331         }
1332
1333         for (i = 0; i < chip->num_streams; i++) {
1334                 azx_dev = &chip->azx_dev[i];
1335                 if (status & azx_dev->sd_int_sta_mask) {
1336                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1337                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1338                         if (!azx_dev->substream || !azx_dev->running ||
1339                             !(sd_status & SD_INT_COMPLETE))
1340                                 continue;
1341                         /* check whether this IRQ is really acceptable */
1342                         ok = azx_position_ok(chip, azx_dev);
1343                         if (ok == 1) {
1344                                 azx_dev->irq_pending = 0;
1345                                 spin_unlock(&chip->reg_lock);
1346                                 snd_pcm_period_elapsed(azx_dev->substream);
1347                                 spin_lock(&chip->reg_lock);
1348                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1349                                 /* bogus IRQ, process it later */
1350                                 azx_dev->irq_pending = 1;
1351                                 queue_work(chip->bus->workq,
1352                                            &chip->irq_pending_work);
1353                         }
1354                 }
1355         }
1356
1357         /* clear rirb int */
1358         status = azx_readb(chip, RIRBSTS);
1359         if (status & RIRB_INT_MASK) {
1360                 if (status & RIRB_INT_RESPONSE) {
1361                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1362                                 udelay(80);
1363                         azx_update_rirb(chip);
1364                 }
1365                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1366         }
1367
1368 #if 0
1369         /* clear state status int */
1370         if (azx_readb(chip, STATESTS) & 0x04)
1371                 azx_writeb(chip, STATESTS, 0x04);
1372 #endif
1373         spin_unlock(&chip->reg_lock);
1374
1375         return IRQ_HANDLED;
1376 }
1377
1378
1379 /*
1380  * set up a BDL entry
1381  */
1382 static int setup_bdle(struct azx *chip,
1383                       struct snd_pcm_substream *substream,
1384                       struct azx_dev *azx_dev, u32 **bdlp,
1385                       int ofs, int size, int with_ioc)
1386 {
1387         u32 *bdl = *bdlp;
1388
1389         while (size > 0) {
1390                 dma_addr_t addr;
1391                 int chunk;
1392
1393                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1394                         return -EINVAL;
1395
1396                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1397                 /* program the address field of the BDL entry */
1398                 bdl[0] = cpu_to_le32((u32)addr);
1399                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1400                 /* program the size field of the BDL entry */
1401                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1402                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1403                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1404                         u32 remain = 0x1000 - (ofs & 0xfff);
1405                         if (chunk > remain)
1406                                 chunk = remain;
1407                 }
1408                 bdl[2] = cpu_to_le32(chunk);
1409                 /* program the IOC to enable interrupt
1410                  * only when the whole fragment is processed
1411                  */
1412                 size -= chunk;
1413                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1414                 bdl += 4;
1415                 azx_dev->frags++;
1416                 ofs += chunk;
1417         }
1418         *bdlp = bdl;
1419         return ofs;
1420 }
1421
1422 /*
1423  * set up BDL entries
1424  */
1425 static int azx_setup_periods(struct azx *chip,
1426                              struct snd_pcm_substream *substream,
1427                              struct azx_dev *azx_dev)
1428 {
1429         u32 *bdl;
1430         int i, ofs, periods, period_bytes;
1431         int pos_adj;
1432
1433         /* reset BDL address */
1434         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1435         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1436
1437         period_bytes = azx_dev->period_bytes;
1438         periods = azx_dev->bufsize / period_bytes;
1439
1440         /* program the initial BDL entries */
1441         bdl = (u32 *)azx_dev->bdl.area;
1442         ofs = 0;
1443         azx_dev->frags = 0;
1444         pos_adj = bdl_pos_adj[chip->dev_index];
1445         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1446                 struct snd_pcm_runtime *runtime = substream->runtime;
1447                 int pos_align = pos_adj;
1448                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1449                 if (!pos_adj)
1450                         pos_adj = pos_align;
1451                 else
1452                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1453                                 pos_align;
1454                 pos_adj = frames_to_bytes(runtime, pos_adj);
1455                 if (pos_adj >= period_bytes) {
1456                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1457                                    bdl_pos_adj[chip->dev_index]);
1458                         pos_adj = 0;
1459                 } else {
1460                         ofs = setup_bdle(chip, substream, azx_dev,
1461                                          &bdl, ofs, pos_adj, true);
1462                         if (ofs < 0)
1463                                 goto error;
1464                 }
1465         } else
1466                 pos_adj = 0;
1467         for (i = 0; i < periods; i++) {
1468                 if (i == periods - 1 && pos_adj)
1469                         ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1470                                          period_bytes - pos_adj, 0);
1471                 else
1472                         ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1473                                          period_bytes,
1474                                          !azx_dev->no_period_wakeup);
1475                 if (ofs < 0)
1476                         goto error;
1477         }
1478         return 0;
1479
1480  error:
1481         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1482                    azx_dev->bufsize, period_bytes);
1483         return -EINVAL;
1484 }
1485
1486 /* reset stream */
1487 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1488 {
1489         unsigned char val;
1490         int timeout;
1491
1492         azx_stream_clear(chip, azx_dev);
1493
1494         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1495                       SD_CTL_STREAM_RESET);
1496         udelay(3);
1497         timeout = 300;
1498         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1499                --timeout)
1500                 ;
1501         val &= ~SD_CTL_STREAM_RESET;
1502         azx_sd_writeb(azx_dev, SD_CTL, val);
1503         udelay(3);
1504
1505         timeout = 300;
1506         /* waiting for hardware to report that the stream is out of reset */
1507         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1508                --timeout)
1509                 ;
1510
1511         /* reset first position - may not be synced with hw at this time */
1512         *azx_dev->posbuf = 0;
1513 }
1514
1515 /*
1516  * set up the SD for streaming
1517  */
1518 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1519 {
1520         unsigned int val;
1521         /* make sure the run bit is zero for SD */
1522         azx_stream_clear(chip, azx_dev);
1523         /* program the stream_tag */
1524         val = azx_sd_readl(azx_dev, SD_CTL);
1525         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1526                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1527         if (!azx_snoop(chip))
1528                 val |= SD_CTL_TRAFFIC_PRIO;
1529         azx_sd_writel(azx_dev, SD_CTL, val);
1530
1531         /* program the length of samples in cyclic buffer */
1532         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1533
1534         /* program the stream format */
1535         /* this value needs to be the same as the one programmed */
1536         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1537
1538         /* program the stream LVI (last valid index) of the BDL */
1539         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1540
1541         /* program the BDL address */
1542         /* lower BDL address */
1543         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1544         /* upper BDL address */
1545         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1546
1547         /* enable the position buffer */
1548         if (chip->position_fix[0] != POS_FIX_LPIB ||
1549             chip->position_fix[1] != POS_FIX_LPIB) {
1550                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1551                         azx_writel(chip, DPLBASE,
1552                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1553         }
1554
1555         /* set the interrupt enable bits in the descriptor control register */
1556         azx_sd_writel(azx_dev, SD_CTL,
1557                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1558
1559         return 0;
1560 }
1561
1562 /*
1563  * Probe the given codec address
1564  */
1565 static int probe_codec(struct azx *chip, int addr)
1566 {
1567         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1568                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1569         unsigned int res;
1570
1571         mutex_lock(&chip->bus->cmd_mutex);
1572         chip->probing = 1;
1573         azx_send_cmd(chip->bus, cmd);
1574         res = azx_get_response(chip->bus, addr);
1575         chip->probing = 0;
1576         mutex_unlock(&chip->bus->cmd_mutex);
1577         if (res == -1)
1578                 return -EIO;
1579         snd_printdd(SFX "codec #%d probed OK\n", addr);
1580         return 0;
1581 }
1582
1583 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1584                                  struct hda_pcm *cpcm);
1585 static void azx_stop_chip(struct azx *chip);
1586
1587 static void azx_bus_reset(struct hda_bus *bus)
1588 {
1589         struct azx *chip = bus->private_data;
1590
1591         bus->in_reset = 1;
1592         azx_stop_chip(chip);
1593         azx_init_chip(chip, 1);
1594 #ifdef CONFIG_PM
1595         if (chip->initialized) {
1596                 struct azx_pcm *p;
1597                 list_for_each_entry(p, &chip->pcm_list, list)
1598                         snd_pcm_suspend_all(p->pcm);
1599                 snd_hda_suspend(chip->bus);
1600                 snd_hda_resume(chip->bus);
1601         }
1602 #endif
1603         bus->in_reset = 0;
1604 }
1605
1606 static int get_jackpoll_interval(struct azx *chip)
1607 {
1608         int i = jackpoll_ms[chip->dev_index];
1609         unsigned int j;
1610         if (i == 0)
1611                 return 0;
1612         if (i < 50 || i > 60000)
1613                 j = 0;
1614         else
1615                 j = msecs_to_jiffies(i);
1616         if (j == 0)
1617                 snd_printk(KERN_WARNING SFX
1618                            "jackpoll_ms value out of range: %d\n", i);
1619         return j;
1620 }
1621
1622 /*
1623  * Codec initialization
1624  */
1625
1626 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1627 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
1628         [AZX_DRIVER_NVIDIA] = 8,
1629         [AZX_DRIVER_TERA] = 1,
1630 };
1631
1632 static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1633 {
1634         struct hda_bus_template bus_temp;
1635         int c, codecs, err;
1636         int max_slots;
1637
1638         memset(&bus_temp, 0, sizeof(bus_temp));
1639         bus_temp.private_data = chip;
1640         bus_temp.modelname = model;
1641         bus_temp.pci = chip->pci;
1642         bus_temp.ops.command = azx_send_cmd;
1643         bus_temp.ops.get_response = azx_get_response;
1644         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1645         bus_temp.ops.bus_reset = azx_bus_reset;
1646 #ifdef CONFIG_PM
1647         bus_temp.power_save = &power_save;
1648         bus_temp.ops.pm_notify = azx_power_notify;
1649 #endif
1650
1651         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1652         if (err < 0)
1653                 return err;
1654
1655         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1656                 snd_printd(SFX "Enable delay in RIRB handling\n");
1657                 chip->bus->needs_damn_long_delay = 1;
1658         }
1659
1660         codecs = 0;
1661         max_slots = azx_max_codecs[chip->driver_type];
1662         if (!max_slots)
1663                 max_slots = AZX_DEFAULT_CODECS;
1664
1665         /* First try to probe all given codec slots */
1666         for (c = 0; c < max_slots; c++) {
1667                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1668                         if (probe_codec(chip, c) < 0) {
1669                                 /* Some BIOSen give you wrong codec addresses
1670                                  * that don't exist
1671                                  */
1672                                 snd_printk(KERN_WARNING SFX
1673                                            "Codec #%d probe error; "
1674                                            "disabling it...\n", c);
1675                                 chip->codec_mask &= ~(1 << c);
1676                                 /* More badly, accessing to a non-existing
1677                                  * codec often screws up the controller chip,
1678                                  * and disturbs the further communications.
1679                                  * Thus if an error occurs during probing,
1680                                  * better to reset the controller chip to
1681                                  * get back to the sanity state.
1682                                  */
1683                                 azx_stop_chip(chip);
1684                                 azx_init_chip(chip, 1);
1685                         }
1686                 }
1687         }
1688
1689         /* AMD chipsets often cause the communication stalls upon certain
1690          * sequence like the pin-detection.  It seems that forcing the synced
1691          * access works around the stall.  Grrr...
1692          */
1693         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1694                 snd_printd(SFX "Enable sync_write for stable communication\n");
1695                 chip->bus->sync_write = 1;
1696                 chip->bus->allow_bus_reset = 1;
1697         }
1698
1699         /* Then create codec instances */
1700         for (c = 0; c < max_slots; c++) {
1701                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1702                         struct hda_codec *codec;
1703                         err = snd_hda_codec_new(chip->bus, c, &codec);
1704                         if (err < 0)
1705                                 continue;
1706                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1707                         codec->beep_mode = chip->beep_mode;
1708                         codecs++;
1709                 }
1710         }
1711         if (!codecs) {
1712                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1713                 return -ENXIO;
1714         }
1715         return 0;
1716 }
1717
1718 /* configure each codec instance */
1719 static int __devinit azx_codec_configure(struct azx *chip)
1720 {
1721         struct hda_codec *codec;
1722         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1723                 snd_hda_codec_configure(codec);
1724         }
1725         return 0;
1726 }
1727
1728
1729 /*
1730  * PCM support
1731  */
1732
1733 /* assign a stream for the PCM */
1734 static inline struct azx_dev *
1735 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1736 {
1737         int dev, i, nums;
1738         struct azx_dev *res = NULL;
1739         /* make a non-zero unique key for the substream */
1740         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1741                 (substream->stream + 1);
1742
1743         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1744                 dev = chip->playback_index_offset;
1745                 nums = chip->playback_streams;
1746         } else {
1747                 dev = chip->capture_index_offset;
1748                 nums = chip->capture_streams;
1749         }
1750         for (i = 0; i < nums; i++, dev++)
1751                 if (!chip->azx_dev[dev].opened) {
1752                         res = &chip->azx_dev[dev];
1753                         if (res->assigned_key == key)
1754                                 break;
1755                 }
1756         if (res) {
1757                 res->opened = 1;
1758                 res->assigned_key = key;
1759         }
1760         return res;
1761 }
1762
1763 /* release the assigned stream */
1764 static inline void azx_release_device(struct azx_dev *azx_dev)
1765 {
1766         azx_dev->opened = 0;
1767 }
1768
1769 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1770 {
1771         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1772         struct snd_pcm_substream *substream = azx_dev->substream;
1773         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1774         struct azx *chip = apcm->chip;
1775
1776         return azx_readl(chip, WALLCLK);
1777 }
1778
1779 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1780                                 bool force, cycle_t last)
1781 {
1782         struct azx_dev *azx_dev = get_azx_dev(substream);
1783         struct timecounter *tc = &azx_dev->azx_tc;
1784         struct cyclecounter *cc = &azx_dev->azx_cc;
1785         u64 nsec;
1786
1787         cc->read = azx_cc_read;
1788         cc->mask = CLOCKSOURCE_MASK(32);
1789
1790         /*
1791          * Converting from 24 MHz to ns means applying a 125/3 factor.
1792          * To avoid any saturation issues in intermediate operations,
1793          * the 125 factor is applied first. The division is applied
1794          * last after reading the timecounter value.
1795          * Applying the 1/3 factor as part of the multiplication
1796          * requires at least 20 bits for a decent precision, however
1797          * overflows occur after about 4 hours or less, not a option.
1798          */
1799
1800         cc->mult = 125; /* saturation after 195 years */
1801         cc->shift = 0;
1802
1803         nsec = 0; /* audio time is elapsed time since trigger */
1804         timecounter_init(tc, cc, nsec);
1805         if (force)
1806                 /*
1807                  * force timecounter to use predefined value,
1808                  * used for synchronized starts
1809                  */
1810                 tc->cycle_last = last;
1811 }
1812
1813 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1814                                 struct timespec *ts)
1815 {
1816         struct azx_dev *azx_dev = get_azx_dev(substream);
1817         u64 nsec;
1818
1819         nsec = timecounter_read(&azx_dev->azx_tc);
1820         nsec = div_u64(nsec, 3); /* can be optimized */
1821
1822         *ts = ns_to_timespec(nsec);
1823
1824         return 0;
1825 }
1826
1827 static struct snd_pcm_hardware azx_pcm_hw = {
1828         .info =                 (SNDRV_PCM_INFO_MMAP |
1829                                  SNDRV_PCM_INFO_INTERLEAVED |
1830                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1831                                  SNDRV_PCM_INFO_MMAP_VALID |
1832                                  /* No full-resume yet implemented */
1833                                  /* SNDRV_PCM_INFO_RESUME |*/
1834                                  SNDRV_PCM_INFO_PAUSE |
1835                                  SNDRV_PCM_INFO_SYNC_START |
1836                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1837                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1838         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1839         .rates =                SNDRV_PCM_RATE_48000,
1840         .rate_min =             48000,
1841         .rate_max =             48000,
1842         .channels_min =         2,
1843         .channels_max =         2,
1844         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1845         .period_bytes_min =     128,
1846         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1847         .periods_min =          2,
1848         .periods_max =          AZX_MAX_FRAG,
1849         .fifo_size =            0,
1850 };
1851
1852 static int azx_pcm_open(struct snd_pcm_substream *substream)
1853 {
1854         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1855         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1856         struct azx *chip = apcm->chip;
1857         struct azx_dev *azx_dev;
1858         struct snd_pcm_runtime *runtime = substream->runtime;
1859         unsigned long flags;
1860         int err;
1861         int buff_step;
1862
1863         mutex_lock(&chip->open_mutex);
1864         azx_dev = azx_assign_device(chip, substream);
1865         if (azx_dev == NULL) {
1866                 mutex_unlock(&chip->open_mutex);
1867                 return -EBUSY;
1868         }
1869         runtime->hw = azx_pcm_hw;
1870         runtime->hw.channels_min = hinfo->channels_min;
1871         runtime->hw.channels_max = hinfo->channels_max;
1872         runtime->hw.formats = hinfo->formats;
1873         runtime->hw.rates = hinfo->rates;
1874         snd_pcm_limit_hw_rates(runtime);
1875         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1876
1877         /* avoid wrap-around with wall-clock */
1878         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1879                                 20,
1880                                 178000000);
1881
1882         if (chip->align_buffer_size)
1883                 /* constrain buffer sizes to be multiple of 128
1884                    bytes. This is more efficient in terms of memory
1885                    access but isn't required by the HDA spec and
1886                    prevents users from specifying exact period/buffer
1887                    sizes. For example for 44.1kHz, a period size set
1888                    to 20ms will be rounded to 19.59ms. */
1889                 buff_step = 128;
1890         else
1891                 /* Don't enforce steps on buffer sizes, still need to
1892                    be multiple of 4 bytes (HDA spec). Tested on Intel
1893                    HDA controllers, may not work on all devices where
1894                    option needs to be disabled */
1895                 buff_step = 4;
1896
1897         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1898                                    buff_step);
1899         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1900                                    buff_step);
1901         snd_hda_power_up_d3wait(apcm->codec);
1902         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1903         if (err < 0) {
1904                 azx_release_device(azx_dev);
1905                 snd_hda_power_down(apcm->codec);
1906                 mutex_unlock(&chip->open_mutex);
1907                 return err;
1908         }
1909         snd_pcm_limit_hw_rates(runtime);
1910         /* sanity check */
1911         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1912             snd_BUG_ON(!runtime->hw.channels_max) ||
1913             snd_BUG_ON(!runtime->hw.formats) ||
1914             snd_BUG_ON(!runtime->hw.rates)) {
1915                 azx_release_device(azx_dev);
1916                 hinfo->ops.close(hinfo, apcm->codec, substream);
1917                 snd_hda_power_down(apcm->codec);
1918                 mutex_unlock(&chip->open_mutex);
1919                 return -EINVAL;
1920         }
1921
1922         /* disable WALLCLOCK timestamps for capture streams
1923            until we figure out how to handle digital inputs */
1924         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1925                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1926
1927         spin_lock_irqsave(&chip->reg_lock, flags);
1928         azx_dev->substream = substream;
1929         azx_dev->running = 0;
1930         spin_unlock_irqrestore(&chip->reg_lock, flags);
1931
1932         runtime->private_data = azx_dev;
1933         snd_pcm_set_sync(substream);
1934         mutex_unlock(&chip->open_mutex);
1935         return 0;
1936 }
1937
1938 static int azx_pcm_close(struct snd_pcm_substream *substream)
1939 {
1940         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1941         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1942         struct azx *chip = apcm->chip;
1943         struct azx_dev *azx_dev = get_azx_dev(substream);
1944         unsigned long flags;
1945
1946         mutex_lock(&chip->open_mutex);
1947         spin_lock_irqsave(&chip->reg_lock, flags);
1948         azx_dev->substream = NULL;
1949         azx_dev->running = 0;
1950         spin_unlock_irqrestore(&chip->reg_lock, flags);
1951         azx_release_device(azx_dev);
1952         hinfo->ops.close(hinfo, apcm->codec, substream);
1953         snd_hda_power_down(apcm->codec);
1954         mutex_unlock(&chip->open_mutex);
1955         return 0;
1956 }
1957
1958 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1959                              struct snd_pcm_hw_params *hw_params)
1960 {
1961         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1962         struct azx *chip = apcm->chip;
1963         struct snd_pcm_runtime *runtime = substream->runtime;
1964         struct azx_dev *azx_dev = get_azx_dev(substream);
1965         int ret;
1966
1967         mark_runtime_wc(chip, azx_dev, runtime, false);
1968         azx_dev->bufsize = 0;
1969         azx_dev->period_bytes = 0;
1970         azx_dev->format_val = 0;
1971         ret = snd_pcm_lib_malloc_pages(substream,
1972                                         params_buffer_bytes(hw_params));
1973         if (ret < 0)
1974                 return ret;
1975         mark_runtime_wc(chip, azx_dev, runtime, true);
1976         return ret;
1977 }
1978
1979 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1980 {
1981         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1982         struct azx_dev *azx_dev = get_azx_dev(substream);
1983         struct azx *chip = apcm->chip;
1984         struct snd_pcm_runtime *runtime = substream->runtime;
1985         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1986
1987         /* reset BDL address */
1988         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1989         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1990         azx_sd_writel(azx_dev, SD_CTL, 0);
1991         azx_dev->bufsize = 0;
1992         azx_dev->period_bytes = 0;
1993         azx_dev->format_val = 0;
1994
1995         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1996
1997         mark_runtime_wc(chip, azx_dev, runtime, false);
1998         return snd_pcm_lib_free_pages(substream);
1999 }
2000
2001 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2002 {
2003         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2004         struct azx *chip = apcm->chip;
2005         struct azx_dev *azx_dev = get_azx_dev(substream);
2006         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2007         struct snd_pcm_runtime *runtime = substream->runtime;
2008         unsigned int bufsize, period_bytes, format_val, stream_tag;
2009         int err;
2010         struct hda_spdif_out *spdif =
2011                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2012         unsigned short ctls = spdif ? spdif->ctls : 0;
2013
2014         azx_stream_reset(chip, azx_dev);
2015         format_val = snd_hda_calc_stream_format(runtime->rate,
2016                                                 runtime->channels,
2017                                                 runtime->format,
2018                                                 hinfo->maxbps,
2019                                                 ctls);
2020         if (!format_val) {
2021                 snd_printk(KERN_ERR SFX
2022                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
2023                            runtime->rate, runtime->channels, runtime->format);
2024                 return -EINVAL;
2025         }
2026
2027         bufsize = snd_pcm_lib_buffer_bytes(substream);
2028         period_bytes = snd_pcm_lib_period_bytes(substream);
2029
2030         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2031                     bufsize, format_val);
2032
2033         if (bufsize != azx_dev->bufsize ||
2034             period_bytes != azx_dev->period_bytes ||
2035             format_val != azx_dev->format_val ||
2036             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2037                 azx_dev->bufsize = bufsize;
2038                 azx_dev->period_bytes = period_bytes;
2039                 azx_dev->format_val = format_val;
2040                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2041                 err = azx_setup_periods(chip, substream, azx_dev);
2042                 if (err < 0)
2043                         return err;
2044         }
2045
2046         /* wallclk has 24Mhz clock source */
2047         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2048                                                 runtime->rate) * 1000);
2049         azx_setup_controller(chip, azx_dev);
2050         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2051                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2052         else
2053                 azx_dev->fifo_size = 0;
2054
2055         stream_tag = azx_dev->stream_tag;
2056         /* CA-IBG chips need the playback stream starting from 1 */
2057         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2058             stream_tag > chip->capture_streams)
2059                 stream_tag -= chip->capture_streams;
2060         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2061                                      azx_dev->format_val, substream);
2062 }
2063
2064 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2065 {
2066         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2067         struct azx *chip = apcm->chip;
2068         struct azx_dev *azx_dev;
2069         struct snd_pcm_substream *s;
2070         int rstart = 0, start, nsync = 0, sbits = 0;
2071         int nwait, timeout;
2072
2073         azx_dev = get_azx_dev(substream);
2074         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2075
2076         switch (cmd) {
2077         case SNDRV_PCM_TRIGGER_START:
2078                 rstart = 1;
2079         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2080         case SNDRV_PCM_TRIGGER_RESUME:
2081                 start = 1;
2082                 break;
2083         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2084         case SNDRV_PCM_TRIGGER_SUSPEND:
2085         case SNDRV_PCM_TRIGGER_STOP:
2086                 start = 0;
2087                 break;
2088         default:
2089                 return -EINVAL;
2090         }
2091
2092         snd_pcm_group_for_each_entry(s, substream) {
2093                 if (s->pcm->card != substream->pcm->card)
2094                         continue;
2095                 azx_dev = get_azx_dev(s);
2096                 sbits |= 1 << azx_dev->index;
2097                 nsync++;
2098                 snd_pcm_trigger_done(s, substream);
2099         }
2100
2101         spin_lock(&chip->reg_lock);
2102
2103         /* first, set SYNC bits of corresponding streams */
2104         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2105                 azx_writel(chip, OLD_SSYNC,
2106                         azx_readl(chip, OLD_SSYNC) | sbits);
2107         else
2108                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2109
2110         snd_pcm_group_for_each_entry(s, substream) {
2111                 if (s->pcm->card != substream->pcm->card)
2112                         continue;
2113                 azx_dev = get_azx_dev(s);
2114                 if (start) {
2115                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2116                         if (!rstart)
2117                                 azx_dev->start_wallclk -=
2118                                                 azx_dev->period_wallclk;
2119                         azx_stream_start(chip, azx_dev);
2120                 } else {
2121                         azx_stream_stop(chip, azx_dev);
2122                 }
2123                 azx_dev->running = start;
2124         }
2125         spin_unlock(&chip->reg_lock);
2126         if (start) {
2127                 /* wait until all FIFOs get ready */
2128                 for (timeout = 5000; timeout; timeout--) {
2129                         nwait = 0;
2130                         snd_pcm_group_for_each_entry(s, substream) {
2131                                 if (s->pcm->card != substream->pcm->card)
2132                                         continue;
2133                                 azx_dev = get_azx_dev(s);
2134                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2135                                       SD_STS_FIFO_READY))
2136                                         nwait++;
2137                         }
2138                         if (!nwait)
2139                                 break;
2140                         cpu_relax();
2141                 }
2142         } else {
2143                 /* wait until all RUN bits are cleared */
2144                 for (timeout = 5000; timeout; timeout--) {
2145                         nwait = 0;
2146                         snd_pcm_group_for_each_entry(s, substream) {
2147                                 if (s->pcm->card != substream->pcm->card)
2148                                         continue;
2149                                 azx_dev = get_azx_dev(s);
2150                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2151                                     SD_CTL_DMA_START)
2152                                         nwait++;
2153                         }
2154                         if (!nwait)
2155                                 break;
2156                         cpu_relax();
2157                 }
2158         }
2159         spin_lock(&chip->reg_lock);
2160         /* reset SYNC bits */
2161         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2162                 azx_writel(chip, OLD_SSYNC,
2163                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2164         else
2165                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2166         if (start) {
2167                 azx_timecounter_init(substream, 0, 0);
2168                 if (nsync > 1) {
2169                         cycle_t cycle_last;
2170
2171                         /* same start cycle for master and group */
2172                         azx_dev = get_azx_dev(substream);
2173                         cycle_last = azx_dev->azx_tc.cycle_last;
2174
2175                         snd_pcm_group_for_each_entry(s, substream) {
2176                                 if (s->pcm->card != substream->pcm->card)
2177                                         continue;
2178                                 azx_timecounter_init(s, 1, cycle_last);
2179                         }
2180                 }
2181         }
2182         spin_unlock(&chip->reg_lock);
2183         return 0;
2184 }
2185
2186 /* get the current DMA position with correction on VIA chips */
2187 static unsigned int azx_via_get_position(struct azx *chip,
2188                                          struct azx_dev *azx_dev)
2189 {
2190         unsigned int link_pos, mini_pos, bound_pos;
2191         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2192         unsigned int fifo_size;
2193
2194         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2195         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2196                 /* Playback, no problem using link position */
2197                 return link_pos;
2198         }
2199
2200         /* Capture */
2201         /* For new chipset,
2202          * use mod to get the DMA position just like old chipset
2203          */
2204         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2205         mod_dma_pos %= azx_dev->period_bytes;
2206
2207         /* azx_dev->fifo_size can't get FIFO size of in stream.
2208          * Get from base address + offset.
2209          */
2210         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2211
2212         if (azx_dev->insufficient) {
2213                 /* Link position never gather than FIFO size */
2214                 if (link_pos <= fifo_size)
2215                         return 0;
2216
2217                 azx_dev->insufficient = 0;
2218         }
2219
2220         if (link_pos <= fifo_size)
2221                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2222         else
2223                 mini_pos = link_pos - fifo_size;
2224
2225         /* Find nearest previous boudary */
2226         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2227         mod_link_pos = link_pos % azx_dev->period_bytes;
2228         if (mod_link_pos >= fifo_size)
2229                 bound_pos = link_pos - mod_link_pos;
2230         else if (mod_dma_pos >= mod_mini_pos)
2231                 bound_pos = mini_pos - mod_mini_pos;
2232         else {
2233                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2234                 if (bound_pos >= azx_dev->bufsize)
2235                         bound_pos = 0;
2236         }
2237
2238         /* Calculate real DMA position we want */
2239         return bound_pos + mod_dma_pos;
2240 }
2241
2242 static unsigned int azx_get_position(struct azx *chip,
2243                                      struct azx_dev *azx_dev,
2244                                      bool with_check)
2245 {
2246         unsigned int pos;
2247         int stream = azx_dev->substream->stream;
2248         int delay = 0;
2249
2250         switch (chip->position_fix[stream]) {
2251         case POS_FIX_LPIB:
2252                 /* read LPIB */
2253                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2254                 break;
2255         case POS_FIX_VIACOMBO:
2256                 pos = azx_via_get_position(chip, azx_dev);
2257                 break;
2258         default:
2259                 /* use the position buffer */
2260                 pos = le32_to_cpu(*azx_dev->posbuf);
2261                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2262                         if (!pos || pos == (u32)-1) {
2263                                 printk(KERN_WARNING
2264                                        "hda-intel: Invalid position buffer, "
2265                                        "using LPIB read method instead.\n");
2266                                 chip->position_fix[stream] = POS_FIX_LPIB;
2267                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2268                         } else
2269                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2270                 }
2271                 break;
2272         }
2273
2274         if (pos >= azx_dev->bufsize)
2275                 pos = 0;
2276
2277         /* calculate runtime delay from LPIB */
2278         if (azx_dev->substream->runtime &&
2279             chip->position_fix[stream] == POS_FIX_POSBUF &&
2280             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2281                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2282                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2283                         delay = pos - lpib_pos;
2284                 else
2285                         delay = lpib_pos - pos;
2286                 if (delay < 0)
2287                         delay += azx_dev->bufsize;
2288                 if (delay >= azx_dev->period_bytes) {
2289                         snd_printk(KERN_WARNING SFX
2290                                    "Unstable LPIB (%d >= %d); "
2291                                    "disabling LPIB delay counting\n",
2292                                    delay, azx_dev->period_bytes);
2293                         delay = 0;
2294                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2295                 }
2296                 azx_dev->substream->runtime->delay =
2297                         bytes_to_frames(azx_dev->substream->runtime, delay);
2298         }
2299         trace_azx_get_position(chip, azx_dev, pos, delay);
2300         return pos;
2301 }
2302
2303 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2304 {
2305         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2306         struct azx *chip = apcm->chip;
2307         struct azx_dev *azx_dev = get_azx_dev(substream);
2308         return bytes_to_frames(substream->runtime,
2309                                azx_get_position(chip, azx_dev, false));
2310 }
2311
2312 /*
2313  * Check whether the current DMA position is acceptable for updating
2314  * periods.  Returns non-zero if it's OK.
2315  *
2316  * Many HD-audio controllers appear pretty inaccurate about
2317  * the update-IRQ timing.  The IRQ is issued before actually the
2318  * data is processed.  So, we need to process it afterwords in a
2319  * workqueue.
2320  */
2321 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2322 {
2323         u32 wallclk;
2324         unsigned int pos;
2325
2326         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2327         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2328                 return -1;      /* bogus (too early) interrupt */
2329
2330         pos = azx_get_position(chip, azx_dev, true);
2331
2332         if (WARN_ONCE(!azx_dev->period_bytes,
2333                       "hda-intel: zero azx_dev->period_bytes"))
2334                 return -1; /* this shouldn't happen! */
2335         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2336             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2337                 /* NG - it's below the first next period boundary */
2338                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2339         azx_dev->start_wallclk += wallclk;
2340         return 1; /* OK, it's fine */
2341 }
2342
2343 /*
2344  * The work for pending PCM period updates.
2345  */
2346 static void azx_irq_pending_work(struct work_struct *work)
2347 {
2348         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2349         int i, pending, ok;
2350
2351         if (!chip->irq_pending_warned) {
2352                 printk(KERN_WARNING
2353                        "hda-intel: IRQ timing workaround is activated "
2354                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2355                        chip->card->number);
2356                 chip->irq_pending_warned = 1;
2357         }
2358
2359         for (;;) {
2360                 pending = 0;
2361                 spin_lock_irq(&chip->reg_lock);
2362                 for (i = 0; i < chip->num_streams; i++) {
2363                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2364                         if (!azx_dev->irq_pending ||
2365                             !azx_dev->substream ||
2366                             !azx_dev->running)
2367                                 continue;
2368                         ok = azx_position_ok(chip, azx_dev);
2369                         if (ok > 0) {
2370                                 azx_dev->irq_pending = 0;
2371                                 spin_unlock(&chip->reg_lock);
2372                                 snd_pcm_period_elapsed(azx_dev->substream);
2373                                 spin_lock(&chip->reg_lock);
2374                         } else if (ok < 0) {
2375                                 pending = 0;    /* too early */
2376                         } else
2377                                 pending++;
2378                 }
2379                 spin_unlock_irq(&chip->reg_lock);
2380                 if (!pending)
2381                         return;
2382                 msleep(1);
2383         }
2384 }
2385
2386 /* clear irq_pending flags and assure no on-going workq */
2387 static void azx_clear_irq_pending(struct azx *chip)
2388 {
2389         int i;
2390
2391         spin_lock_irq(&chip->reg_lock);
2392         for (i = 0; i < chip->num_streams; i++)
2393                 chip->azx_dev[i].irq_pending = 0;
2394         spin_unlock_irq(&chip->reg_lock);
2395 }
2396
2397 #ifdef CONFIG_X86
2398 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2399                         struct vm_area_struct *area)
2400 {
2401         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2402         struct azx *chip = apcm->chip;
2403         if (!azx_snoop(chip))
2404                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2405         return snd_pcm_lib_default_mmap(substream, area);
2406 }
2407 #else
2408 #define azx_pcm_mmap    NULL
2409 #endif
2410
2411 static struct snd_pcm_ops azx_pcm_ops = {
2412         .open = azx_pcm_open,
2413         .close = azx_pcm_close,
2414         .ioctl = snd_pcm_lib_ioctl,
2415         .hw_params = azx_pcm_hw_params,
2416         .hw_free = azx_pcm_hw_free,
2417         .prepare = azx_pcm_prepare,
2418         .trigger = azx_pcm_trigger,
2419         .pointer = azx_pcm_pointer,
2420         .wall_clock =  azx_get_wallclock_tstamp,
2421         .mmap = azx_pcm_mmap,
2422         .page = snd_pcm_sgbuf_ops_page,
2423 };
2424
2425 static void azx_pcm_free(struct snd_pcm *pcm)
2426 {
2427         struct azx_pcm *apcm = pcm->private_data;
2428         if (apcm) {
2429                 list_del(&apcm->list);
2430                 kfree(apcm);
2431         }
2432 }
2433
2434 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2435
2436 static int
2437 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2438                       struct hda_pcm *cpcm)
2439 {
2440         struct azx *chip = bus->private_data;
2441         struct snd_pcm *pcm;
2442         struct azx_pcm *apcm;
2443         int pcm_dev = cpcm->device;
2444         unsigned int size;
2445         int s, err;
2446
2447         list_for_each_entry(apcm, &chip->pcm_list, list) {
2448                 if (apcm->pcm->device == pcm_dev) {
2449                         snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2450                         return -EBUSY;
2451                 }
2452         }
2453         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2454                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2455                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2456                           &pcm);
2457         if (err < 0)
2458                 return err;
2459         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2460         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2461         if (apcm == NULL)
2462                 return -ENOMEM;
2463         apcm->chip = chip;
2464         apcm->pcm = pcm;
2465         apcm->codec = codec;
2466         pcm->private_data = apcm;
2467         pcm->private_free = azx_pcm_free;
2468         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2469                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2470         list_add_tail(&apcm->list, &chip->pcm_list);
2471         cpcm->pcm = pcm;
2472         for (s = 0; s < 2; s++) {
2473                 apcm->hinfo[s] = &cpcm->stream[s];
2474                 if (cpcm->stream[s].substreams)
2475                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2476         }
2477         /* buffer pre-allocation */
2478         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2479         if (size > MAX_PREALLOC_SIZE)
2480                 size = MAX_PREALLOC_SIZE;
2481         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2482                                               snd_dma_pci_data(chip->pci),
2483                                               size, MAX_PREALLOC_SIZE);
2484         return 0;
2485 }
2486
2487 /*
2488  * mixer creation - all stuff is implemented in hda module
2489  */
2490 static int __devinit azx_mixer_create(struct azx *chip)
2491 {
2492         return snd_hda_build_controls(chip->bus);
2493 }
2494
2495
2496 /*
2497  * initialize SD streams
2498  */
2499 static int __devinit azx_init_stream(struct azx *chip)
2500 {
2501         int i;
2502
2503         /* initialize each stream (aka device)
2504          * assign the starting bdl address to each stream (device)
2505          * and initialize
2506          */
2507         for (i = 0; i < chip->num_streams; i++) {
2508                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2509                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2510                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2511                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2512                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2513                 azx_dev->sd_int_sta_mask = 1 << i;
2514                 /* stream tag: must be non-zero and unique */
2515                 azx_dev->index = i;
2516                 azx_dev->stream_tag = i + 1;
2517         }
2518
2519         return 0;
2520 }
2521
2522 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2523 {
2524         if (request_irq(chip->pci->irq, azx_interrupt,
2525                         chip->msi ? 0 : IRQF_SHARED,
2526                         KBUILD_MODNAME, chip)) {
2527                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2528                        "disabling device\n", chip->pci->irq);
2529                 if (do_disconnect)
2530                         snd_card_disconnect(chip->card);
2531                 return -1;
2532         }
2533         chip->irq = chip->pci->irq;
2534         pci_intx(chip->pci, !chip->msi);
2535         return 0;
2536 }
2537
2538
2539 static void azx_stop_chip(struct azx *chip)
2540 {
2541         if (!chip->initialized)
2542                 return;
2543
2544         /* disable interrupts */
2545         azx_int_disable(chip);
2546         azx_int_clear(chip);
2547
2548         /* disable CORB/RIRB */
2549         azx_free_cmd_io(chip);
2550
2551         /* disable position buffer */
2552         azx_writel(chip, DPLBASE, 0);
2553         azx_writel(chip, DPUBASE, 0);
2554
2555         chip->initialized = 0;
2556 }
2557
2558 #ifdef CONFIG_PM
2559 /* power-up/down the controller */
2560 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2561 {
2562         struct azx *chip = bus->private_data;
2563
2564         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2565                 return;
2566
2567         if (power_up)
2568                 pm_runtime_get_sync(&chip->pci->dev);
2569         else
2570                 pm_runtime_put_sync(&chip->pci->dev);
2571 }
2572
2573 static DEFINE_MUTEX(card_list_lock);
2574 static LIST_HEAD(card_list);
2575
2576 static void azx_add_card_list(struct azx *chip)
2577 {
2578         mutex_lock(&card_list_lock);
2579         list_add(&chip->list, &card_list);
2580         mutex_unlock(&card_list_lock);
2581 }
2582
2583 static void azx_del_card_list(struct azx *chip)
2584 {
2585         mutex_lock(&card_list_lock);
2586         list_del_init(&chip->list);
2587         mutex_unlock(&card_list_lock);
2588 }
2589
2590 /* trigger power-save check at writing parameter */
2591 static int param_set_xint(const char *val, const struct kernel_param *kp)
2592 {
2593         struct azx *chip;
2594         struct hda_codec *c;
2595         int prev = power_save;
2596         int ret = param_set_int(val, kp);
2597
2598         if (ret || prev == power_save)
2599                 return ret;
2600
2601         mutex_lock(&card_list_lock);
2602         list_for_each_entry(chip, &card_list, list) {
2603                 if (!chip->bus || chip->disabled)
2604                         continue;
2605                 list_for_each_entry(c, &chip->bus->codec_list, list)
2606                         snd_hda_power_sync(c);
2607         }
2608         mutex_unlock(&card_list_lock);
2609         return 0;
2610 }
2611 #else
2612 #define azx_add_card_list(chip) /* NOP */
2613 #define azx_del_card_list(chip) /* NOP */
2614 #endif /* CONFIG_PM */
2615
2616 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2617 /*
2618  * power management
2619  */
2620 static int azx_suspend(struct device *dev)
2621 {
2622         struct pci_dev *pci = to_pci_dev(dev);
2623         struct snd_card *card = dev_get_drvdata(dev);
2624         struct azx *chip = card->private_data;
2625         struct azx_pcm *p;
2626
2627         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2628         azx_clear_irq_pending(chip);
2629         list_for_each_entry(p, &chip->pcm_list, list)
2630                 snd_pcm_suspend_all(p->pcm);
2631         if (chip->initialized)
2632                 snd_hda_suspend(chip->bus);
2633         azx_stop_chip(chip);
2634         if (chip->irq >= 0) {
2635                 free_irq(chip->irq, chip);
2636                 chip->irq = -1;
2637         }
2638         if (chip->msi)
2639                 pci_disable_msi(chip->pci);
2640         pci_disable_device(pci);
2641         pci_save_state(pci);
2642         pci_set_power_state(pci, PCI_D3hot);
2643         return 0;
2644 }
2645
2646 static int azx_resume(struct device *dev)
2647 {
2648         struct pci_dev *pci = to_pci_dev(dev);
2649         struct snd_card *card = dev_get_drvdata(dev);
2650         struct azx *chip = card->private_data;
2651
2652         pci_set_power_state(pci, PCI_D0);
2653         pci_restore_state(pci);
2654         if (pci_enable_device(pci) < 0) {
2655                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2656                        "disabling device\n");
2657                 snd_card_disconnect(card);
2658                 return -EIO;
2659         }
2660         pci_set_master(pci);
2661         if (chip->msi)
2662                 if (pci_enable_msi(pci) < 0)
2663                         chip->msi = 0;
2664         if (azx_acquire_irq(chip, 1) < 0)
2665                 return -EIO;
2666         azx_init_pci(chip);
2667
2668         azx_init_chip(chip, 1);
2669
2670         snd_hda_resume(chip->bus);
2671         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2672         return 0;
2673 }
2674 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2675
2676 #ifdef CONFIG_PM_RUNTIME
2677 static int azx_runtime_suspend(struct device *dev)
2678 {
2679         struct snd_card *card = dev_get_drvdata(dev);
2680         struct azx *chip = card->private_data;
2681
2682         if (!power_save_controller ||
2683             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2684                 return -EAGAIN;
2685
2686         azx_stop_chip(chip);
2687         azx_clear_irq_pending(chip);
2688         return 0;
2689 }
2690
2691 static int azx_runtime_resume(struct device *dev)
2692 {
2693         struct snd_card *card = dev_get_drvdata(dev);
2694         struct azx *chip = card->private_data;
2695
2696         azx_init_pci(chip);
2697         azx_init_chip(chip, 1);
2698         return 0;
2699 }
2700 #endif /* CONFIG_PM_RUNTIME */
2701
2702 #ifdef CONFIG_PM
2703 static const struct dev_pm_ops azx_pm = {
2704         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2705         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, NULL)
2706 };
2707
2708 #define AZX_PM_OPS      &azx_pm
2709 #else
2710 #define AZX_PM_OPS      NULL
2711 #endif /* CONFIG_PM */
2712
2713
2714 /*
2715  * reboot notifier for hang-up problem at power-down
2716  */
2717 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2718 {
2719         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2720         snd_hda_bus_reboot_notify(chip->bus);
2721         azx_stop_chip(chip);
2722         return NOTIFY_OK;
2723 }
2724
2725 static void azx_notifier_register(struct azx *chip)
2726 {
2727         chip->reboot_notifier.notifier_call = azx_halt;
2728         register_reboot_notifier(&chip->reboot_notifier);
2729 }
2730
2731 static void azx_notifier_unregister(struct azx *chip)
2732 {
2733         if (chip->reboot_notifier.notifier_call)
2734                 unregister_reboot_notifier(&chip->reboot_notifier);
2735 }
2736
2737 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2738 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2739
2740 #ifdef SUPPORT_VGA_SWITCHEROO
2741 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2742
2743 static void azx_vs_set_state(struct pci_dev *pci,
2744                              enum vga_switcheroo_state state)
2745 {
2746         struct snd_card *card = pci_get_drvdata(pci);
2747         struct azx *chip = card->private_data;
2748         bool disabled;
2749
2750         wait_for_completion(&chip->probe_wait);
2751         if (chip->init_failed)
2752                 return;
2753
2754         disabled = (state == VGA_SWITCHEROO_OFF);
2755         if (chip->disabled == disabled)
2756                 return;
2757
2758         if (!chip->bus) {
2759                 chip->disabled = disabled;
2760                 if (!disabled) {
2761                         snd_printk(KERN_INFO SFX
2762                                    "%s: Start delayed initialization\n",
2763                                    pci_name(chip->pci));
2764                         if (azx_first_init(chip) < 0 ||
2765                             azx_probe_continue(chip) < 0) {
2766                                 snd_printk(KERN_ERR SFX
2767                                            "%s: initialization error\n",
2768                                            pci_name(chip->pci));
2769                                 chip->init_failed = true;
2770                         }
2771                 }
2772         } else {
2773                 snd_printk(KERN_INFO SFX
2774                            "%s %s via VGA-switcheroo\n",
2775                            disabled ? "Disabling" : "Enabling",
2776                            pci_name(chip->pci));
2777                 if (disabled) {
2778                         azx_suspend(&pci->dev);
2779                         chip->disabled = true;
2780                         if (snd_hda_lock_devices(chip->bus))
2781                                 snd_printk(KERN_WARNING SFX
2782                                            "Cannot lock devices!\n");
2783                 } else {
2784                         snd_hda_unlock_devices(chip->bus);
2785                         chip->disabled = false;
2786                         azx_resume(&pci->dev);
2787                 }
2788         }
2789 }
2790
2791 static bool azx_vs_can_switch(struct pci_dev *pci)
2792 {
2793         struct snd_card *card = pci_get_drvdata(pci);
2794         struct azx *chip = card->private_data;
2795
2796         wait_for_completion(&chip->probe_wait);
2797         if (chip->init_failed)
2798                 return false;
2799         if (chip->disabled || !chip->bus)
2800                 return true;
2801         if (snd_hda_lock_devices(chip->bus))
2802                 return false;
2803         snd_hda_unlock_devices(chip->bus);
2804         return true;
2805 }
2806
2807 static void __devinit init_vga_switcheroo(struct azx *chip)
2808 {
2809         struct pci_dev *p = get_bound_vga(chip->pci);
2810         if (p) {
2811                 snd_printk(KERN_INFO SFX
2812                            "%s: Handle VGA-switcheroo audio client\n",
2813                            pci_name(chip->pci));
2814                 chip->use_vga_switcheroo = 1;
2815                 pci_dev_put(p);
2816         }
2817 }
2818
2819 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2820         .set_gpu_state = azx_vs_set_state,
2821         .can_switch = azx_vs_can_switch,
2822 };
2823
2824 static int __devinit register_vga_switcheroo(struct azx *chip)
2825 {
2826         int err;
2827
2828         if (!chip->use_vga_switcheroo)
2829                 return 0;
2830         /* FIXME: currently only handling DIS controller
2831          * is there any machine with two switchable HDMI audio controllers?
2832          */
2833         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2834                                                     VGA_SWITCHEROO_DIS,
2835                                                     chip->bus != NULL);
2836         if (err < 0)
2837                 return err;
2838         chip->vga_switcheroo_registered = 1;
2839         return 0;
2840 }
2841 #else
2842 #define init_vga_switcheroo(chip)               /* NOP */
2843 #define register_vga_switcheroo(chip)           0
2844 #define check_hdmi_disabled(pci)        false
2845 #endif /* SUPPORT_VGA_SWITCHER */
2846
2847 /*
2848  * destructor
2849  */
2850 static int azx_free(struct azx *chip)
2851 {
2852         int i;
2853
2854         azx_del_card_list(chip);
2855
2856         azx_notifier_unregister(chip);
2857
2858         chip->init_failed = 1; /* to be sure */
2859         complete(&chip->probe_wait);
2860
2861         if (use_vga_switcheroo(chip)) {
2862                 if (chip->disabled && chip->bus)
2863                         snd_hda_unlock_devices(chip->bus);
2864                 if (chip->vga_switcheroo_registered)
2865                         vga_switcheroo_unregister_client(chip->pci);
2866         }
2867
2868         if (chip->initialized) {
2869                 azx_clear_irq_pending(chip);
2870                 for (i = 0; i < chip->num_streams; i++)
2871                         azx_stream_stop(chip, &chip->azx_dev[i]);
2872                 azx_stop_chip(chip);
2873         }
2874
2875         if (chip->irq >= 0)
2876                 free_irq(chip->irq, (void*)chip);
2877         if (chip->msi)
2878                 pci_disable_msi(chip->pci);
2879         if (chip->remap_addr)
2880                 iounmap(chip->remap_addr);
2881
2882         if (chip->azx_dev) {
2883                 for (i = 0; i < chip->num_streams; i++)
2884                         if (chip->azx_dev[i].bdl.area) {
2885                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2886                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2887                         }
2888         }
2889         if (chip->rb.area) {
2890                 mark_pages_wc(chip, &chip->rb, false);
2891                 snd_dma_free_pages(&chip->rb);
2892         }
2893         if (chip->posbuf.area) {
2894                 mark_pages_wc(chip, &chip->posbuf, false);
2895                 snd_dma_free_pages(&chip->posbuf);
2896         }
2897         if (chip->region_requested)
2898                 pci_release_regions(chip->pci);
2899         pci_disable_device(chip->pci);
2900         kfree(chip->azx_dev);
2901 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2902         if (chip->fw)
2903                 release_firmware(chip->fw);
2904 #endif
2905         kfree(chip);
2906
2907         return 0;
2908 }
2909
2910 static int azx_dev_free(struct snd_device *device)
2911 {
2912         return azx_free(device->device_data);
2913 }
2914
2915 #ifdef SUPPORT_VGA_SWITCHEROO
2916 /*
2917  * Check of disabled HDMI controller by vga-switcheroo
2918  */
2919 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2920 {
2921         struct pci_dev *p;
2922
2923         /* check only discrete GPU */
2924         switch (pci->vendor) {
2925         case PCI_VENDOR_ID_ATI:
2926         case PCI_VENDOR_ID_AMD:
2927         case PCI_VENDOR_ID_NVIDIA:
2928                 if (pci->devfn == 1) {
2929                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2930                                                         pci->bus->number, 0);
2931                         if (p) {
2932                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2933                                         return p;
2934                                 pci_dev_put(p);
2935                         }
2936                 }
2937                 break;
2938         }
2939         return NULL;
2940 }
2941
2942 static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2943 {
2944         bool vga_inactive = false;
2945         struct pci_dev *p = get_bound_vga(pci);
2946
2947         if (p) {
2948                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2949                         vga_inactive = true;
2950                 pci_dev_put(p);
2951         }
2952         return vga_inactive;
2953 }
2954 #endif /* SUPPORT_VGA_SWITCHEROO */
2955
2956 /*
2957  * white/black-listing for position_fix
2958  */
2959 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2960         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2961         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2962         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2963         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2964         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2965         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2966         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2967         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2968         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2969         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2970         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2971         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2972         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2973         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2974         {}
2975 };
2976
2977 static int __devinit check_position_fix(struct azx *chip, int fix)
2978 {
2979         const struct snd_pci_quirk *q;
2980
2981         switch (fix) {
2982         case POS_FIX_AUTO:
2983         case POS_FIX_LPIB:
2984         case POS_FIX_POSBUF:
2985         case POS_FIX_VIACOMBO:
2986         case POS_FIX_COMBO:
2987                 return fix;
2988         }
2989
2990         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2991         if (q) {
2992                 printk(KERN_INFO
2993                        "hda_intel: position_fix set to %d "
2994                        "for device %04x:%04x\n",
2995                        q->value, q->subvendor, q->subdevice);
2996                 return q->value;
2997         }
2998
2999         /* Check VIA/ATI HD Audio Controller exist */
3000         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3001                 snd_printd(SFX "Using VIACOMBO position fix\n");
3002                 return POS_FIX_VIACOMBO;
3003         }
3004         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3005                 snd_printd(SFX "Using LPIB position fix\n");
3006                 return POS_FIX_LPIB;
3007         }
3008         return POS_FIX_AUTO;
3009 }
3010
3011 /*
3012  * black-lists for probe_mask
3013  */
3014 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
3015         /* Thinkpad often breaks the controller communication when accessing
3016          * to the non-working (or non-existing) modem codec slot.
3017          */
3018         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3019         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3020         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3021         /* broken BIOS */
3022         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3023         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3024         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3025         /* forced codec slots */
3026         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3027         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3028         /* WinFast VP200 H (Teradici) user reported broken communication */
3029         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3030         {}
3031 };
3032
3033 #define AZX_FORCE_CODEC_MASK    0x100
3034
3035 static void __devinit check_probe_mask(struct azx *chip, int dev)
3036 {
3037         const struct snd_pci_quirk *q;
3038
3039         chip->codec_probe_mask = probe_mask[dev];
3040         if (chip->codec_probe_mask == -1) {
3041                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3042                 if (q) {
3043                         printk(KERN_INFO
3044                                "hda_intel: probe_mask set to 0x%x "
3045                                "for device %04x:%04x\n",
3046                                q->value, q->subvendor, q->subdevice);
3047                         chip->codec_probe_mask = q->value;
3048                 }
3049         }
3050
3051         /* check forced option */
3052         if (chip->codec_probe_mask != -1 &&
3053             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3054                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3055                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3056                        chip->codec_mask);
3057         }
3058 }
3059
3060 /*
3061  * white/black-list for enable_msi
3062  */
3063 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
3064         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3065         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3066         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3067         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3068         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3069         {}
3070 };
3071
3072 static void __devinit check_msi(struct azx *chip)
3073 {
3074         const struct snd_pci_quirk *q;
3075
3076         if (enable_msi >= 0) {
3077                 chip->msi = !!enable_msi;
3078                 return;
3079         }
3080         chip->msi = 1;  /* enable MSI as default */
3081         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3082         if (q) {
3083                 printk(KERN_INFO
3084                        "hda_intel: msi for device %04x:%04x set to %d\n",
3085                        q->subvendor, q->subdevice, q->value);
3086                 chip->msi = q->value;
3087                 return;
3088         }
3089
3090         /* NVidia chipsets seem to cause troubles with MSI */
3091         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3092                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3093                 chip->msi = 0;
3094         }
3095 }
3096
3097 /* check the snoop mode availability */
3098 static void __devinit azx_check_snoop_available(struct azx *chip)
3099 {
3100         bool snoop = chip->snoop;
3101
3102         switch (chip->driver_type) {
3103         case AZX_DRIVER_VIA:
3104                 /* force to non-snoop mode for a new VIA controller
3105                  * when BIOS is set
3106                  */
3107                 if (snoop) {
3108                         u8 val;
3109                         pci_read_config_byte(chip->pci, 0x42, &val);
3110                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3111                                 snoop = false;
3112                 }
3113                 break;
3114         case AZX_DRIVER_ATIHDMI_NS:
3115                 /* new ATI HDMI requires non-snoop */
3116                 snoop = false;
3117                 break;
3118         }
3119
3120         if (snoop != chip->snoop) {
3121                 snd_printk(KERN_INFO SFX "Force to %s mode\n",
3122                            snoop ? "snoop" : "non-snoop");
3123                 chip->snoop = snoop;
3124         }
3125 }
3126
3127 /*
3128  * constructor
3129  */
3130 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
3131                                 int dev, unsigned int driver_caps,
3132                                 struct azx **rchip)
3133 {
3134         static struct snd_device_ops ops = {
3135                 .dev_free = azx_dev_free,
3136         };
3137         struct azx *chip;
3138         int err;
3139
3140         *rchip = NULL;
3141
3142         err = pci_enable_device(pci);
3143         if (err < 0)
3144                 return err;
3145
3146         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3147         if (!chip) {
3148                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
3149                 pci_disable_device(pci);
3150                 return -ENOMEM;
3151         }
3152
3153         spin_lock_init(&chip->reg_lock);
3154         mutex_init(&chip->open_mutex);
3155         chip->card = card;
3156         chip->pci = pci;
3157         chip->irq = -1;
3158         chip->driver_caps = driver_caps;
3159         chip->driver_type = driver_caps & 0xff;
3160         check_msi(chip);
3161         chip->dev_index = dev;
3162         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3163         INIT_LIST_HEAD(&chip->pcm_list);
3164         INIT_LIST_HEAD(&chip->list);
3165         init_vga_switcheroo(chip);
3166         init_completion(&chip->probe_wait);
3167
3168         chip->position_fix[0] = chip->position_fix[1] =
3169                 check_position_fix(chip, position_fix[dev]);
3170         /* combo mode uses LPIB for playback */
3171         if (chip->position_fix[0] == POS_FIX_COMBO) {
3172                 chip->position_fix[0] = POS_FIX_LPIB;
3173                 chip->position_fix[1] = POS_FIX_AUTO;
3174         }
3175
3176         check_probe_mask(chip, dev);
3177
3178         chip->single_cmd = single_cmd;
3179         chip->snoop = hda_snoop;
3180         azx_check_snoop_available(chip);
3181
3182         if (bdl_pos_adj[dev] < 0) {
3183                 switch (chip->driver_type) {
3184                 case AZX_DRIVER_ICH:
3185                 case AZX_DRIVER_PCH:
3186                         bdl_pos_adj[dev] = 1;
3187                         break;
3188                 default:
3189                         bdl_pos_adj[dev] = 32;
3190                         break;
3191                 }
3192         }
3193
3194         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3195         if (err < 0) {
3196                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3197                 azx_free(chip);
3198                 return err;
3199         }
3200
3201         *rchip = chip;
3202         return 0;
3203 }
3204
3205 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3206 {
3207         int dev = chip->dev_index;
3208         struct pci_dev *pci = chip->pci;
3209         struct snd_card *card = chip->card;
3210         int i, err;
3211         unsigned short gcap;
3212
3213 #if BITS_PER_LONG != 64
3214         /* Fix up base address on ULI M5461 */
3215         if (chip->driver_type == AZX_DRIVER_ULI) {
3216                 u16 tmp3;
3217                 pci_read_config_word(pci, 0x40, &tmp3);
3218                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3219                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3220         }
3221 #endif
3222
3223         err = pci_request_regions(pci, "ICH HD audio");
3224         if (err < 0)
3225                 return err;
3226         chip->region_requested = 1;
3227
3228         chip->addr = pci_resource_start(pci, 0);
3229         chip->remap_addr = pci_ioremap_bar(pci, 0);
3230         if (chip->remap_addr == NULL) {
3231                 snd_printk(KERN_ERR SFX "ioremap error\n");
3232                 return -ENXIO;
3233         }
3234
3235         if (chip->msi)
3236                 if (pci_enable_msi(pci) < 0)
3237                         chip->msi = 0;
3238
3239         if (azx_acquire_irq(chip, 0) < 0)
3240                 return -EBUSY;
3241
3242         pci_set_master(pci);
3243         synchronize_irq(chip->irq);
3244
3245         gcap = azx_readw(chip, GCAP);
3246         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
3247
3248         /* disable SB600 64bit support for safety */
3249         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3250                 struct pci_dev *p_smbus;
3251                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3252                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3253                                          NULL);
3254                 if (p_smbus) {
3255                         if (p_smbus->revision < 0x30)
3256                                 gcap &= ~ICH6_GCAP_64OK;
3257                         pci_dev_put(p_smbus);
3258                 }
3259         }
3260
3261         /* disable 64bit DMA address on some devices */
3262         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3263                 snd_printd(SFX "Disabling 64bit DMA\n");
3264                 gcap &= ~ICH6_GCAP_64OK;
3265         }
3266
3267         /* disable buffer size rounding to 128-byte multiples if supported */
3268         if (align_buffer_size >= 0)
3269                 chip->align_buffer_size = !!align_buffer_size;
3270         else {
3271                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3272                         chip->align_buffer_size = 0;
3273                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3274                         chip->align_buffer_size = 1;
3275                 else
3276                         chip->align_buffer_size = 1;
3277         }
3278
3279         /* allow 64bit DMA address if supported by H/W */
3280         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3281                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3282         else {
3283                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3284                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3285         }
3286
3287         /* read number of streams from GCAP register instead of using
3288          * hardcoded value
3289          */
3290         chip->capture_streams = (gcap >> 8) & 0x0f;
3291         chip->playback_streams = (gcap >> 12) & 0x0f;
3292         if (!chip->playback_streams && !chip->capture_streams) {
3293                 /* gcap didn't give any info, switching to old method */
3294
3295                 switch (chip->driver_type) {
3296                 case AZX_DRIVER_ULI:
3297                         chip->playback_streams = ULI_NUM_PLAYBACK;
3298                         chip->capture_streams = ULI_NUM_CAPTURE;
3299                         break;
3300                 case AZX_DRIVER_ATIHDMI:
3301                 case AZX_DRIVER_ATIHDMI_NS:
3302                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3303                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3304                         break;
3305                 case AZX_DRIVER_GENERIC:
3306                 default:
3307                         chip->playback_streams = ICH6_NUM_PLAYBACK;
3308                         chip->capture_streams = ICH6_NUM_CAPTURE;
3309                         break;
3310                 }
3311         }
3312         chip->capture_index_offset = 0;
3313         chip->playback_index_offset = chip->capture_streams;
3314         chip->num_streams = chip->playback_streams + chip->capture_streams;
3315         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3316                                 GFP_KERNEL);
3317         if (!chip->azx_dev) {
3318                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3319                 return -ENOMEM;
3320         }
3321
3322         for (i = 0; i < chip->num_streams; i++) {
3323                 /* allocate memory for the BDL for each stream */
3324                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3325                                           snd_dma_pci_data(chip->pci),
3326                                           BDL_SIZE, &chip->azx_dev[i].bdl);
3327                 if (err < 0) {
3328                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
3329                         return -ENOMEM;
3330                 }
3331                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3332         }
3333         /* allocate memory for the position buffer */
3334         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3335                                   snd_dma_pci_data(chip->pci),
3336                                   chip->num_streams * 8, &chip->posbuf);
3337         if (err < 0) {
3338                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
3339                 return -ENOMEM;
3340         }
3341         mark_pages_wc(chip, &chip->posbuf, true);
3342         /* allocate CORB/RIRB */
3343         err = azx_alloc_cmd_io(chip);
3344         if (err < 0)
3345                 return err;
3346
3347         /* initialize streams */
3348         azx_init_stream(chip);
3349
3350         /* initialize chip */
3351         azx_init_pci(chip);
3352         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3353
3354         /* codec detection */
3355         if (!chip->codec_mask) {
3356                 snd_printk(KERN_ERR SFX "no codecs found!\n");
3357                 return -ENODEV;
3358         }
3359
3360         strcpy(card->driver, "HDA-Intel");
3361         strlcpy(card->shortname, driver_short_names[chip->driver_type],
3362                 sizeof(card->shortname));
3363         snprintf(card->longname, sizeof(card->longname),
3364                  "%s at 0x%lx irq %i",
3365                  card->shortname, chip->addr, chip->irq);
3366
3367         return 0;
3368 }
3369
3370 static void power_down_all_codecs(struct azx *chip)
3371 {
3372 #ifdef CONFIG_PM
3373         /* The codecs were powered up in snd_hda_codec_new().
3374          * Now all initialization done, so turn them down if possible
3375          */
3376         struct hda_codec *codec;
3377         list_for_each_entry(codec, &chip->bus->codec_list, list) {
3378                 snd_hda_power_down(codec);
3379         }
3380 #endif
3381 }
3382
3383 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3384 /* callback from request_firmware_nowait() */
3385 static void azx_firmware_cb(const struct firmware *fw, void *context)
3386 {
3387         struct snd_card *card = context;
3388         struct azx *chip = card->private_data;
3389         struct pci_dev *pci = chip->pci;
3390
3391         if (!fw) {
3392                 snd_printk(KERN_ERR SFX "Cannot load firmware, aborting\n");
3393                 goto error;
3394         }
3395
3396         chip->fw = fw;
3397         if (!chip->disabled) {
3398                 /* continue probing */
3399                 if (azx_probe_continue(chip))
3400                         goto error;
3401         }
3402         return; /* OK */
3403
3404  error:
3405         snd_card_free(card);
3406         pci_set_drvdata(pci, NULL);
3407 }
3408 #endif
3409
3410 static int __devinit azx_probe(struct pci_dev *pci,
3411                                const struct pci_device_id *pci_id)
3412 {
3413         static int dev;
3414         struct snd_card *card;
3415         struct azx *chip;
3416         bool probe_now;
3417         int err;
3418
3419         if (dev >= SNDRV_CARDS)
3420                 return -ENODEV;
3421         if (!enable[dev]) {
3422                 dev++;
3423                 return -ENOENT;
3424         }
3425
3426         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3427         if (err < 0) {
3428                 snd_printk(KERN_ERR SFX "Error creating card!\n");
3429                 return err;
3430         }
3431
3432         snd_card_set_dev(card, &pci->dev);
3433
3434         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3435         if (err < 0)
3436                 goto out_free;
3437         card->private_data = chip;
3438
3439         pci_set_drvdata(pci, card);
3440
3441         err = register_vga_switcheroo(chip);
3442         if (err < 0) {
3443                 snd_printk(KERN_ERR SFX
3444                            "Error registering VGA-switcheroo client\n");
3445                 goto out_free;
3446         }
3447
3448         if (check_hdmi_disabled(pci)) {
3449                 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
3450                            pci_name(pci));
3451                 snd_printk(KERN_INFO SFX "Delaying initialization\n");
3452                 chip->disabled = true;
3453         }
3454
3455         probe_now = !chip->disabled;
3456         if (probe_now) {
3457                 err = azx_first_init(chip);
3458                 if (err < 0)
3459                         goto out_free;
3460         }
3461
3462 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3463         if (patch[dev] && *patch[dev]) {
3464                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3465                            patch[dev]);
3466                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3467                                               &pci->dev, GFP_KERNEL, card,
3468                                               azx_firmware_cb);
3469                 if (err < 0)
3470                         goto out_free;
3471                 probe_now = false; /* continued in azx_firmware_cb() */
3472         }
3473 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3474
3475         if (probe_now) {
3476                 err = azx_probe_continue(chip);
3477                 if (err < 0)
3478                         goto out_free;
3479         }
3480
3481         if (pci_dev_run_wake(pci))
3482                 pm_runtime_put_noidle(&pci->dev);
3483
3484         dev++;
3485         complete(&chip->probe_wait);
3486         return 0;
3487
3488 out_free:
3489         snd_card_free(card);
3490         pci_set_drvdata(pci, NULL);
3491         return err;
3492 }
3493
3494 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3495 {
3496         int dev = chip->dev_index;
3497         int err;
3498
3499 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3500         chip->beep_mode = beep_mode[dev];
3501 #endif
3502
3503         /* create codec instances */
3504         err = azx_codec_create(chip, model[dev]);
3505         if (err < 0)
3506                 goto out_free;
3507 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3508         if (chip->fw) {
3509                 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3510                                          chip->fw->data);
3511                 if (err < 0)
3512                         goto out_free;
3513 #ifndef CONFIG_PM
3514                 release_firmware(chip->fw); /* no longer needed */
3515                 chip->fw = NULL;
3516 #endif
3517         }
3518 #endif
3519         if ((probe_only[dev] & 1) == 0) {
3520                 err = azx_codec_configure(chip);
3521                 if (err < 0)
3522                         goto out_free;
3523         }
3524
3525         /* create PCM streams */
3526         err = snd_hda_build_pcms(chip->bus);
3527         if (err < 0)
3528                 goto out_free;
3529
3530         /* create mixer controls */
3531         err = azx_mixer_create(chip);
3532         if (err < 0)
3533                 goto out_free;
3534
3535         err = snd_card_register(chip->card);
3536         if (err < 0)
3537                 goto out_free;
3538
3539         chip->running = 1;
3540         power_down_all_codecs(chip);
3541         azx_notifier_register(chip);
3542         azx_add_card_list(chip);
3543
3544         return 0;
3545
3546 out_free:
3547         chip->init_failed = 1;
3548         return err;
3549 }
3550
3551 static void __devexit azx_remove(struct pci_dev *pci)
3552 {
3553         struct snd_card *card = pci_get_drvdata(pci);
3554
3555         if (pci_dev_run_wake(pci))
3556                 pm_runtime_get_noresume(&pci->dev);
3557
3558         if (card)
3559                 snd_card_free(card);
3560         pci_set_drvdata(pci, NULL);
3561 }
3562
3563 /* PCI IDs */
3564 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3565         /* CPT */
3566         { PCI_DEVICE(0x8086, 0x1c20),
3567           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3568         /* PBG */
3569         { PCI_DEVICE(0x8086, 0x1d20),
3570           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3571         /* Panther Point */
3572         { PCI_DEVICE(0x8086, 0x1e20),
3573           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3574         /* Lynx Point */
3575         { PCI_DEVICE(0x8086, 0x8c20),
3576           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3577         /* Lynx Point-LP */
3578         { PCI_DEVICE(0x8086, 0x9c20),
3579           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3580         /* Lynx Point-LP */
3581         { PCI_DEVICE(0x8086, 0x9c21),
3582           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3583         /* Haswell */
3584         { PCI_DEVICE(0x8086, 0x0c0c),
3585           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3586         { PCI_DEVICE(0x8086, 0x0d0c),
3587           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3588         /* 5 Series/3400 */
3589         { PCI_DEVICE(0x8086, 0x3b56),
3590           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3591         /* SCH */
3592         { PCI_DEVICE(0x8086, 0x811b),
3593           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3594           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3595         { PCI_DEVICE(0x8086, 0x080a),
3596           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3597           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3598         /* ICH */
3599         { PCI_DEVICE(0x8086, 0x2668),
3600           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3601           AZX_DCAPS_BUFSIZE },  /* ICH6 */
3602         { PCI_DEVICE(0x8086, 0x27d8),
3603           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3604           AZX_DCAPS_BUFSIZE },  /* ICH7 */
3605         { PCI_DEVICE(0x8086, 0x269a),
3606           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3607           AZX_DCAPS_BUFSIZE },  /* ESB2 */
3608         { PCI_DEVICE(0x8086, 0x284b),
3609           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3610           AZX_DCAPS_BUFSIZE },  /* ICH8 */
3611         { PCI_DEVICE(0x8086, 0x293e),
3612           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3613           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3614         { PCI_DEVICE(0x8086, 0x293f),
3615           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3616           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3617         { PCI_DEVICE(0x8086, 0x3a3e),
3618           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3619           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3620         { PCI_DEVICE(0x8086, 0x3a6e),
3621           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3622           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3623         /* Generic Intel */
3624         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3625           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3626           .class_mask = 0xffffff,
3627           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3628         /* ATI SB 450/600/700/800/900 */
3629         { PCI_DEVICE(0x1002, 0x437b),
3630           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3631         { PCI_DEVICE(0x1002, 0x4383),
3632           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3633         /* AMD Hudson */
3634         { PCI_DEVICE(0x1022, 0x780d),
3635           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3636         /* ATI HDMI */
3637         { PCI_DEVICE(0x1002, 0x793b),
3638           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3639         { PCI_DEVICE(0x1002, 0x7919),
3640           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3641         { PCI_DEVICE(0x1002, 0x960f),
3642           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3643         { PCI_DEVICE(0x1002, 0x970f),
3644           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3645         { PCI_DEVICE(0x1002, 0xaa00),
3646           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3647         { PCI_DEVICE(0x1002, 0xaa08),
3648           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3649         { PCI_DEVICE(0x1002, 0xaa10),
3650           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3651         { PCI_DEVICE(0x1002, 0xaa18),
3652           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3653         { PCI_DEVICE(0x1002, 0xaa20),
3654           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3655         { PCI_DEVICE(0x1002, 0xaa28),
3656           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3657         { PCI_DEVICE(0x1002, 0xaa30),
3658           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3659         { PCI_DEVICE(0x1002, 0xaa38),
3660           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3661         { PCI_DEVICE(0x1002, 0xaa40),
3662           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3663         { PCI_DEVICE(0x1002, 0xaa48),
3664           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3665         { PCI_DEVICE(0x1002, 0x9902),
3666           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3667         { PCI_DEVICE(0x1002, 0xaaa0),
3668           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3669         { PCI_DEVICE(0x1002, 0xaaa8),
3670           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3671         { PCI_DEVICE(0x1002, 0xaab0),
3672           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3673         /* VIA VT8251/VT8237A */
3674         { PCI_DEVICE(0x1106, 0x3288),
3675           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3676         /* VIA GFX VT7122/VX900 */
3677         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3678         /* VIA GFX VT6122/VX11 */
3679         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3680         /* SIS966 */
3681         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3682         /* ULI M5461 */
3683         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3684         /* NVIDIA MCP */
3685         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3686           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3687           .class_mask = 0xffffff,
3688           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3689         /* Teradici */
3690         { PCI_DEVICE(0x6549, 0x1200),
3691           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3692         { PCI_DEVICE(0x6549, 0x2200),
3693           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3694         /* Creative X-Fi (CA0110-IBG) */
3695         /* CTHDA chips */
3696         { PCI_DEVICE(0x1102, 0x0010),
3697           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3698         { PCI_DEVICE(0x1102, 0x0012),
3699           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3700 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3701         /* the following entry conflicts with snd-ctxfi driver,
3702          * as ctxfi driver mutates from HD-audio to native mode with
3703          * a special command sequence.
3704          */
3705         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3706           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3707           .class_mask = 0xffffff,
3708           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3709           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3710 #else
3711         /* this entry seems still valid -- i.e. without emu20kx chip */
3712         { PCI_DEVICE(0x1102, 0x0009),
3713           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3714           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3715 #endif
3716         /* Vortex86MX */
3717         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3718         /* VMware HDAudio */
3719         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3720         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3721         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3722           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3723           .class_mask = 0xffffff,
3724           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3725         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3726           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3727           .class_mask = 0xffffff,
3728           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3729         { 0, }
3730 };
3731 MODULE_DEVICE_TABLE(pci, azx_ids);
3732
3733 /* pci_driver definition */
3734 static struct pci_driver azx_driver = {
3735         .name = KBUILD_MODNAME,
3736         .id_table = azx_ids,
3737         .probe = azx_probe,
3738         .remove = __devexit_p(azx_remove),
3739         .driver = {
3740                 .pm = AZX_PM_OPS,
3741         },
3742 };
3743
3744 module_pci_driver(azx_driver);