2 * Library implementing the most common irq chip callback functions
4 * Copyright (C) 2011, Thomas Gleixner
8 #include <linux/slab.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel_stat.h>
12 #include "internals.h"
14 static inline struct irq_chip_regs *cur_regs(struct irq_data *d)
16 return &container_of(d->chip, struct irq_chip_type, chip)->regs;
20 * irq_gc_noop - NOOP function
23 void irq_gc_noop(struct irq_data *d)
28 * irq_gc_mask_disable_reg - Mask chip via disable register
31 * Chip has separate enable/disable registers instead of a single mask
34 void irq_gc_mask_disable_reg(struct irq_data *d)
36 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
37 u32 mask = 1 << (d->irq - gc->irq_base);
40 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->disable);
41 gc->mask_cache &= ~mask;
46 * irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register
49 * Chip has a single mask register. Values of this register are cached
50 * and protected by gc->lock
52 void irq_gc_mask_set_bit(struct irq_data *d)
54 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
55 u32 mask = 1 << (d->irq - gc->irq_base);
58 gc->mask_cache |= mask;
59 irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);
64 * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register
67 * Chip has a single mask register. Values of this register are cached
68 * and protected by gc->lock
70 void irq_gc_mask_clr_bit(struct irq_data *d)
72 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
73 u32 mask = 1 << (d->irq - gc->irq_base);
76 gc->mask_cache &= ~mask;
77 irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);
82 * irq_gc_unmask_enable_reg - Unmask chip via enable register
85 * Chip has separate enable/disable registers instead of a single mask
88 void irq_gc_unmask_enable_reg(struct irq_data *d)
90 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
91 u32 mask = 1 << (d->irq - gc->irq_base);
94 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->enable);
95 gc->mask_cache |= mask;
100 * irq_gc_ack - Ack pending interrupt
103 void irq_gc_ack(struct irq_data *d)
105 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
106 u32 mask = 1 << (d->irq - gc->irq_base);
109 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
114 * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
117 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
119 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
120 u32 mask = 1 << (d->irq - gc->irq_base);
123 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->mask);
124 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
129 * irq_gc_eoi - EOI interrupt
132 void irq_gc_eoi(struct irq_data *d)
134 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
135 u32 mask = 1 << (d->irq - gc->irq_base);
138 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->eoi);
143 * irq_gc_set_wake - Set/clr wake bit for an interrupt
146 * For chips where the wake from suspend functionality is not
147 * configured in a separate register and the wakeup active state is
148 * just stored in a bitmask.
150 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
152 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
153 u32 mask = 1 << (d->irq - gc->irq_base);
155 if (!(mask & gc->wake_enabled))
160 gc->wake_active |= mask;
162 gc->wake_active &= ~mask;
168 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
169 * @name: Name of the irq chip
170 * @num_ct: Number of irq_chip_type instances associated with this
171 * @irq_base: Interrupt base nr for this chip
172 * @reg_base: Register base address (virtual)
173 * @handler: Default flow handler associated with this chip
175 * Returns an initialized irq_chip_generic structure. The chip defaults
176 * to the primary (index 0) irq_chip_type and @handler
178 struct irq_chip_generic *
179 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
180 void __iomem *reg_base, irq_flow_handler_t handler)
182 struct irq_chip_generic *gc;
183 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
185 gc = kzalloc(sz, GFP_KERNEL);
187 raw_spin_lock_init(&gc->lock);
189 gc->irq_base = irq_base;
190 gc->reg_base = reg_base;
191 gc->chip_types->chip.name = name;
192 gc->chip_types->handler = handler;
198 * Separate lockdep class for interrupt chip which can nest irq_desc
201 static struct lock_class_key irq_nested_lock_class;
204 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
205 * @gc: Generic irq chip holding all data
206 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
207 * @flags: Flags for initialization
208 * @clr: IRQ_* bits to clear
209 * @set: IRQ_* bits to set
211 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
212 * initializes all interrupts to the primary irq_chip_type and its
213 * associated handler.
215 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
216 enum irq_gc_flags flags, unsigned int clr,
219 struct irq_chip_type *ct = gc->chip_types;
222 /* Init mask cache ? */
223 if (flags & IRQ_GC_INIT_MASK_CACHE)
224 gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);
226 for (i = gc->irq_base; msk; msk >>= 1, i++) {
230 if (flags & IRQ_GC_INIT_NESTED_LOCK)
231 irq_set_lockdep_class(i, &irq_nested_lock_class);
233 irq_set_chip_and_handler(i, &ct->chip, ct->handler);
234 irq_set_chip_data(i, gc);
235 irq_modify_status(i, clr, set);
237 gc->irq_cnt = i - gc->irq_base;
241 * irq_setup_alt_chip - Switch to alternative chip
242 * @d: irq_data for this interrupt
243 * @type Flow type to be initialized
245 * Only to be called from chip->irq_set_type() callbacks.
247 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
249 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
250 struct irq_chip_type *ct = gc->chip_types;
253 for (i = 0; i < gc->num_ct; i++, ct++) {
254 if (ct->type & type) {
256 irq_data_to_desc(d)->handle_irq = ct->handler;