Pileus Git - ~andy/linux/blob - include/video/omapdss.h

   1 /*
   2  * Copyright (C) 2008 Nokia Corporation
   3  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __OMAP_OMAPDSS_H
  19 #define __OMAP_OMAPDSS_H
  20
  21 #include <linux/list.h>
  22 #include <linux/kobject.h>
  23 #include <linux/device.h>
  24 #include <linux/platform_device.h>
  25 #include <asm/atomic.h>
  26
  27 #define DISPC_IRQ_FRAMEDONE             (1 << 0)
  28 #define DISPC_IRQ_VSYNC                 (1 << 1)
  29 #define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
  30 #define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
  31 #define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
  32 #define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
  33 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
  34 #define DISPC_IRQ_GFX_END_WIN           (1 << 7)
  35 #define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
  36 #define DISPC_IRQ_OCP_ERR               (1 << 9)
  37 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
  38 #define DISPC_IRQ_VID1_END_WIN          (1 << 11)
  39 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
  40 #define DISPC_IRQ_VID2_END_WIN          (1 << 13)
  41 #define DISPC_IRQ_SYNC_LOST             (1 << 14)
  42 #define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
  43 #define DISPC_IRQ_WAKEUP                (1 << 16)
  44 #define DISPC_IRQ_SYNC_LOST2            (1 << 17)
  45 #define DISPC_IRQ_VSYNC2                (1 << 18)
  46 #define DISPC_IRQ_ACBIAS_COUNT_STAT2    (1 << 21)
  47 #define DISPC_IRQ_FRAMEDONE2            (1 << 22)
  48
  49 struct omap_dss_device;
  50 struct omap_overlay_manager;
  51
  52 enum omap_display_type {
  53         OMAP_DISPLAY_TYPE_NONE          = 0,
  54         OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
  55         OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
  56         OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
  57         OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
  58         OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
  59         OMAP_DISPLAY_TYPE_HDMI          = 1 << 5,
  60 };
  61
  62 enum omap_plane {
  63         OMAP_DSS_GFX    = 0,
  64         OMAP_DSS_VIDEO1 = 1,
  65         OMAP_DSS_VIDEO2 = 2
  66 };
  67
  68 enum omap_channel {
  69         OMAP_DSS_CHANNEL_LCD    = 0,
  70         OMAP_DSS_CHANNEL_DIGIT  = 1,
  71         OMAP_DSS_CHANNEL_LCD2   = 2,
  72 };
  73
  74 enum omap_color_mode {
  75         OMAP_DSS_COLOR_CLUT1    = 1 << 0,  /* BITMAP 1 */
  76         OMAP_DSS_COLOR_CLUT2    = 1 << 1,  /* BITMAP 2 */
  77         OMAP_DSS_COLOR_CLUT4    = 1 << 2,  /* BITMAP 4 */
  78         OMAP_DSS_COLOR_CLUT8    = 1 << 3,  /* BITMAP 8 */
  79         OMAP_DSS_COLOR_RGB12U   = 1 << 4,  /* RGB12, 16-bit container */
  80         OMAP_DSS_COLOR_ARGB16   = 1 << 5,  /* ARGB16 */
  81         OMAP_DSS_COLOR_RGB16    = 1 << 6,  /* RGB16 */
  82         OMAP_DSS_COLOR_RGB24U   = 1 << 7,  /* RGB24, 32-bit container */
  83         OMAP_DSS_COLOR_RGB24P   = 1 << 8,  /* RGB24, 24-bit container */
  84         OMAP_DSS_COLOR_YUV2     = 1 << 9,  /* YUV2 4:2:2 co-sited */
  85         OMAP_DSS_COLOR_UYVY     = 1 << 10, /* UYVY 4:2:2 co-sited */
  86         OMAP_DSS_COLOR_ARGB32   = 1 << 11, /* ARGB32 */
  87         OMAP_DSS_COLOR_RGBA32   = 1 << 12, /* RGBA32 */
  88         OMAP_DSS_COLOR_RGBX32   = 1 << 13, /* RGBx32 */
  89 };
  90
  91 enum omap_lcd_display_type {
  92         OMAP_DSS_LCD_DISPLAY_STN,
  93         OMAP_DSS_LCD_DISPLAY_TFT,
  94 };
  95
  96 enum omap_dss_load_mode {
  97         OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
  98         OMAP_DSS_LOAD_CLUT_ONLY         = 1,
  99         OMAP_DSS_LOAD_FRAME_ONLY        = 2,
 100         OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
 101 };
 102
 103 enum omap_dss_trans_key_type {
 104         OMAP_DSS_COLOR_KEY_GFX_DST = 0,
 105         OMAP_DSS_COLOR_KEY_VID_SRC = 1,
 106 };
 107
 108 enum omap_rfbi_te_mode {
 109         OMAP_DSS_RFBI_TE_MODE_1 = 1,
 110         OMAP_DSS_RFBI_TE_MODE_2 = 2,
 111 };
 112
 113 enum omap_panel_config {
 114         OMAP_DSS_LCD_IVS                = 1<<0,
 115         OMAP_DSS_LCD_IHS                = 1<<1,
 116         OMAP_DSS_LCD_IPC                = 1<<2,
 117         OMAP_DSS_LCD_IEO                = 1<<3,
 118         OMAP_DSS_LCD_RF                 = 1<<4,
 119         OMAP_DSS_LCD_ONOFF              = 1<<5,
 120
 121         OMAP_DSS_LCD_TFT                = 1<<20,
 122 };
 123
 124 enum omap_dss_venc_type {
 125         OMAP_DSS_VENC_TYPE_COMPOSITE,
 126         OMAP_DSS_VENC_TYPE_SVIDEO,
 127 };
 128
 129 enum omap_display_caps {
 130         OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE      = 1 << 0,
 131         OMAP_DSS_DISPLAY_CAP_TEAR_ELIM          = 1 << 1,
 132 };
 133
 134 enum omap_dss_update_mode {
 135         OMAP_DSS_UPDATE_DISABLED = 0,
 136         OMAP_DSS_UPDATE_AUTO,
 137         OMAP_DSS_UPDATE_MANUAL,
 138 };
 139
 140 enum omap_dss_display_state {
 141         OMAP_DSS_DISPLAY_DISABLED = 0,
 142         OMAP_DSS_DISPLAY_ACTIVE,
 143         OMAP_DSS_DISPLAY_SUSPENDED,
 144 };
 145
 146 /* XXX perhaps this should be removed */
 147 enum omap_dss_overlay_managers {
 148         OMAP_DSS_OVL_MGR_LCD,
 149         OMAP_DSS_OVL_MGR_TV,
 150         OMAP_DSS_OVL_MGR_LCD2,
 151 };
 152
 153 enum omap_dss_rotation_type {
 154         OMAP_DSS_ROT_DMA = 0,
 155         OMAP_DSS_ROT_VRFB = 1,
 156 };
 157
 158 /* clockwise rotation angle */
 159 enum omap_dss_rotation_angle {
 160         OMAP_DSS_ROT_0   = 0,
 161         OMAP_DSS_ROT_90  = 1,
 162         OMAP_DSS_ROT_180 = 2,
 163         OMAP_DSS_ROT_270 = 3,
 164 };
 165
 166 enum omap_overlay_caps {
 167         OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
 168         OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
 169 };
 170
 171 enum omap_overlay_manager_caps {
 172         OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
 173 };
 174
 175 enum omap_dss_clk_source {
 176         OMAP_DSS_CLK_SRC_FCK = 0,               /* OMAP2/3: DSS1_ALWON_FCLK
 177                                                  * OMAP4: DSS_FCLK */
 178         OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,   /* OMAP3: DSI1_PLL_FCLK
 179                                                  * OMAP4: PLL1_CLK1 */
 180         OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,     /* OMAP3: DSI2_PLL_FCLK
 181                                                  * OMAP4: PLL1_CLK2 */
 182 };
 183
 184 /* RFBI */
 185
 186 struct rfbi_timings {
 187         int cs_on_time;
 188         int cs_off_time;
 189         int we_on_time;
 190         int we_off_time;
 191         int re_on_time;
 192         int re_off_time;
 193         int we_cycle_time;
 194         int re_cycle_time;
 195         int cs_pulse_width;
 196         int access_time;
 197
 198         int clk_div;
 199
 200         u32 tim[5];             /* set by rfbi_convert_timings() */
 201
 202         int converted;
 203 };
 204
 205 void omap_rfbi_write_command(const void *buf, u32 len);
 206 void omap_rfbi_read_data(void *buf, u32 len);
 207 void omap_rfbi_write_data(const void *buf, u32 len);
 208 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
 209                 u16 x, u16 y,
 210                 u16 w, u16 h);
 211 int omap_rfbi_enable_te(bool enable, unsigned line);
 212 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
 213                              unsigned hs_pulse_time, unsigned vs_pulse_time,
 214                              int hs_pol_inv, int vs_pol_inv, int extif_div);
 215
 216 /* DSI */
 217 void dsi_bus_lock(struct omap_dss_device *dssdev);
 218 void dsi_bus_unlock(struct omap_dss_device *dssdev);
 219 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
 220                 int len);
 221 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel,
 222                 u8 dcs_cmd);
 223 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 224                 u8 param);
 225 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
 226                 u8 *data, int len);
 227 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 228                 u8 *buf, int buflen);
 229 int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 230                 u8 *data);
 231 int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 232                 u8 *data1, u8 *data2);
 233 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
 234                 u16 len);
 235 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
 236 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
 237
 238 /* Board specific data */
 239 struct omap_dss_board_info {
 240         int (*get_last_off_on_transaction_id)(struct device *dev);
 241         int num_devices;
 242         struct omap_dss_device **devices;
 243         struct omap_dss_device *default_device;
 244         void (*dsi_mux_pads)(bool enable);
 245 };
 246
 247 #if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
 248 /* Init with the board info */
 249 extern int omap_display_init(struct omap_dss_board_info *board_data);
 250 #else
 251 static inline int omap_display_init(struct omap_dss_board_info *board_data)
 252 {
 253         return 0;
 254 }
 255 #endif
 256
 257 struct omap_display_platform_data {
 258         struct omap_dss_board_info *board_data;
 259         /* TODO: Additional members to be added when PM is considered */
 260
 261         bool (*opt_clock_available)(const char *clk_role);
 262 };
 263
 264 struct omap_video_timings {
 265         /* Unit: pixels */
 266         u16 x_res;
 267         /* Unit: pixels */
 268         u16 y_res;
 269         /* Unit: KHz */
 270         u32 pixel_clock;
 271         /* Unit: pixel clocks */
 272         u16 hsw;        /* Horizontal synchronization pulse width */
 273         /* Unit: pixel clocks */
 274         u16 hfp;        /* Horizontal front porch */
 275         /* Unit: pixel clocks */
 276         u16 hbp;        /* Horizontal back porch */
 277         /* Unit: line clocks */
 278         u16 vsw;        /* Vertical synchronization pulse width */
 279         /* Unit: line clocks */
 280         u16 vfp;        /* Vertical front porch */
 281         /* Unit: line clocks */
 282         u16 vbp;        /* Vertical back porch */
 283 };
 284
 285 #ifdef CONFIG_OMAP2_DSS_VENC
 286 /* Hardcoded timings for tv modes. Venc only uses these to
 287  * identify the mode, and does not actually use the configs
 288  * itself. However, the configs should be something that
 289  * a normal monitor can also show */
 290 extern const struct omap_video_timings omap_dss_pal_timings;
 291 extern const struct omap_video_timings omap_dss_ntsc_timings;
 292 #endif
 293
 294 struct omap_overlay_info {
 295         bool enabled;
 296
 297         u32 paddr;
 298         void __iomem *vaddr;
 299         u16 screen_width;
 300         u16 width;
 301         u16 height;
 302         enum omap_color_mode color_mode;
 303         u8 rotation;
 304         enum omap_dss_rotation_type rotation_type;
 305         bool mirror;
 306
 307         u16 pos_x;
 308         u16 pos_y;
 309         u16 out_width;  /* if 0, out_width == width */
 310         u16 out_height; /* if 0, out_height == height */
 311         u8 global_alpha;
 312         u8 pre_mult_alpha;
 313 };
 314
 315 struct omap_overlay {
 316         struct kobject kobj;
 317         struct list_head list;
 318
 319         /* static fields */
 320         const char *name;
 321         int id;
 322         enum omap_color_mode supported_modes;
 323         enum omap_overlay_caps caps;
 324
 325         /* dynamic fields */
 326         struct omap_overlay_manager *manager;
 327         struct omap_overlay_info info;
 328
 329         /* if true, info has been changed, but not applied() yet */
 330         bool info_dirty;
 331
 332         int (*set_manager)(struct omap_overlay *ovl,
 333                 struct omap_overlay_manager *mgr);
 334         int (*unset_manager)(struct omap_overlay *ovl);
 335
 336         int (*set_overlay_info)(struct omap_overlay *ovl,
 337                         struct omap_overlay_info *info);
 338         void (*get_overlay_info)(struct omap_overlay *ovl,
 339                         struct omap_overlay_info *info);
 340
 341         int (*wait_for_go)(struct omap_overlay *ovl);
 342 };
 343
 344 struct omap_overlay_manager_info {
 345         u32 default_color;
 346
 347         enum omap_dss_trans_key_type trans_key_type;
 348         u32 trans_key;
 349         bool trans_enabled;
 350
 351         bool alpha_enabled;
 352 };
 353
 354 struct omap_overlay_manager {
 355         struct kobject kobj;
 356         struct list_head list;
 357
 358         /* static fields */
 359         const char *name;
 360         int id;
 361         enum omap_overlay_manager_caps caps;
 362         int num_overlays;
 363         struct omap_overlay **overlays;
 364         enum omap_display_type supported_displays;
 365
 366         /* dynamic fields */
 367         struct omap_dss_device *device;
 368         struct omap_overlay_manager_info info;
 369
 370         bool device_changed;
 371         /* if true, info has been changed but not applied() yet */
 372         bool info_dirty;
 373
 374         int (*set_device)(struct omap_overlay_manager *mgr,
 375                 struct omap_dss_device *dssdev);
 376         int (*unset_device)(struct omap_overlay_manager *mgr);
 377
 378         int (*set_manager_info)(struct omap_overlay_manager *mgr,
 379                         struct omap_overlay_manager_info *info);
 380         void (*get_manager_info)(struct omap_overlay_manager *mgr,
 381                         struct omap_overlay_manager_info *info);
 382
 383         int (*apply)(struct omap_overlay_manager *mgr);
 384         int (*wait_for_go)(struct omap_overlay_manager *mgr);
 385         int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
 386
 387         int (*enable)(struct omap_overlay_manager *mgr);
 388         int (*disable)(struct omap_overlay_manager *mgr);
 389 };
 390
 391 struct omap_dss_device {
 392         struct device dev;
 393
 394         enum omap_display_type type;
 395
 396         enum omap_channel channel;
 397
 398         union {
 399                 struct {
 400                         u8 data_lines;
 401                 } dpi;
 402
 403                 struct {
 404                         u8 channel;
 405                         u8 data_lines;
 406                 } rfbi;
 407
 408                 struct {
 409                         u8 datapairs;
 410                 } sdi;
 411
 412                 struct {
 413                         u8 clk_lane;
 414                         u8 clk_pol;
 415                         u8 data1_lane;
 416                         u8 data1_pol;
 417                         u8 data2_lane;
 418                         u8 data2_pol;
 419
 420                         bool ext_te;
 421                         u8 ext_te_gpio;
 422                 } dsi;
 423
 424                 struct {
 425                         enum omap_dss_venc_type type;
 426                         bool invert_polarity;
 427                 } venc;
 428         } phy;
 429
 430         struct {
 431                 struct {
 432                         struct {
 433                                 u16 lck_div;
 434                                 u16 pck_div;
 435                                 enum omap_dss_clk_source lcd_clk_src;
 436                         } channel;
 437
 438                         enum omap_dss_clk_source dispc_fclk_src;
 439                 } dispc;
 440
 441                 struct {
 442                         u16 regn;
 443                         u16 regm;
 444                         u16 regm_dispc;
 445                         u16 regm_dsi;
 446
 447                         u16 lp_clk_div;
 448                         enum omap_dss_clk_source dsi_fclk_src;
 449                 } dsi;
 450
 451                 struct {
 452                         u16 regn;
 453                         u16 regm2;
 454                 } hdmi;
 455         } clocks;
 456
 457         struct {
 458                 struct omap_video_timings timings;
 459
 460                 int acbi;       /* ac-bias pin transitions per interrupt */
 461                 /* Unit: line clocks */
 462                 int acb;        /* ac-bias pin frequency */
 463
 464                 enum omap_panel_config config;
 465         } panel;
 466
 467         struct {
 468                 u8 pixel_size;
 469                 struct rfbi_timings rfbi_timings;
 470         } ctrl;
 471
 472         int reset_gpio;
 473
 474         int max_backlight_level;
 475
 476         const char *name;
 477
 478         /* used to match device to driver */
 479         const char *driver_name;
 480
 481         void *data;
 482
 483         struct omap_dss_driver *driver;
 484
 485         /* helper variable for driver suspend/resume */
 486         bool activate_after_resume;
 487
 488         enum omap_display_caps caps;
 489
 490         struct omap_overlay_manager *manager;
 491
 492         enum omap_dss_display_state state;
 493
 494         /* platform specific  */
 495         int (*platform_enable)(struct omap_dss_device *dssdev);
 496         void (*platform_disable)(struct omap_dss_device *dssdev);
 497         int (*set_backlight)(struct omap_dss_device *dssdev, int level);
 498         int (*get_backlight)(struct omap_dss_device *dssdev);
 499 };
 500
 501 struct omap_dss_driver {
 502         struct device_driver driver;
 503
 504         int (*probe)(struct omap_dss_device *);
 505         void (*remove)(struct omap_dss_device *);
 506
 507         int (*enable)(struct omap_dss_device *display);
 508         void (*disable)(struct omap_dss_device *display);
 509         int (*suspend)(struct omap_dss_device *display);
 510         int (*resume)(struct omap_dss_device *display);
 511         int (*run_test)(struct omap_dss_device *display, int test);
 512
 513         int (*set_update_mode)(struct omap_dss_device *dssdev,
 514                         enum omap_dss_update_mode);
 515         enum omap_dss_update_mode (*get_update_mode)(
 516                         struct omap_dss_device *dssdev);
 517
 518         int (*update)(struct omap_dss_device *dssdev,
 519                                u16 x, u16 y, u16 w, u16 h);
 520         int (*sync)(struct omap_dss_device *dssdev);
 521
 522         int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
 523         int (*get_te)(struct omap_dss_device *dssdev);
 524
 525         u8 (*get_rotate)(struct omap_dss_device *dssdev);
 526         int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
 527
 528         bool (*get_mirror)(struct omap_dss_device *dssdev);
 529         int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
 530
 531         int (*memory_read)(struct omap_dss_device *dssdev,
 532                         void *buf, size_t size,
 533                         u16 x, u16 y, u16 w, u16 h);
 534
 535         void (*get_resolution)(struct omap_dss_device *dssdev,
 536                         u16 *xres, u16 *yres);
 537         void (*get_dimensions)(struct omap_dss_device *dssdev,
 538                         u32 *width, u32 *height);
 539         int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
 540
 541         int (*check_timings)(struct omap_dss_device *dssdev,
 542                         struct omap_video_timings *timings);
 543         void (*set_timings)(struct omap_dss_device *dssdev,
 544                         struct omap_video_timings *timings);
 545         void (*get_timings)(struct omap_dss_device *dssdev,
 546                         struct omap_video_timings *timings);
 547
 548         int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
 549         u32 (*get_wss)(struct omap_dss_device *dssdev);
 550 };
 551
 552 int omap_dss_register_driver(struct omap_dss_driver *);
 553 void omap_dss_unregister_driver(struct omap_dss_driver *);
 554
 555 void omap_dss_get_device(struct omap_dss_device *dssdev);
 556 void omap_dss_put_device(struct omap_dss_device *dssdev);
 557 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
 558 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
 559 struct omap_dss_device *omap_dss_find_device(void *data,
 560                 int (*match)(struct omap_dss_device *dssdev, void *data));
 561
 562 int omap_dss_start_device(struct omap_dss_device *dssdev);
 563 void omap_dss_stop_device(struct omap_dss_device *dssdev);
 564
 565 int omap_dss_get_num_overlay_managers(void);
 566 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
 567
 568 int omap_dss_get_num_overlays(void);
 569 struct omap_overlay *omap_dss_get_overlay(int num);
 570
 571 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
 572                 u16 *xres, u16 *yres);
 573 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
 574
 575 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
 576 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 577 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 578
 579 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
 580 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
 581                 unsigned long timeout);
 582
 583 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
 584 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
 585
 586 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
 587                 bool enable);
 588 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
 589
 590 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
 591                                     u16 *x, u16 *y, u16 *w, u16 *h,
 592                                     bool enlarge_update_area);
 593 int omap_dsi_update(struct omap_dss_device *dssdev,
 594                 int channel,
 595                 u16 x, u16 y, u16 w, u16 h,
 596                 void (*callback)(int, void *), void *data);
 597 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
 598 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
 599 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
 600
 601 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
 602 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
 603                 bool disconnect_lanes, bool enter_ulps);
 604
 605 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
 606 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
 607 void dpi_set_timings(struct omap_dss_device *dssdev,
 608                         struct omap_video_timings *timings);
 609 int dpi_check_timings(struct omap_dss_device *dssdev,
 610                         struct omap_video_timings *timings);
 611
 612 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
 613 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
 614
 615 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
 616 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
 617 int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
 618                 u16 *x, u16 *y, u16 *w, u16 *h);
 619 int omap_rfbi_update(struct omap_dss_device *dssdev,
 620                 u16 x, u16 y, u16 w, u16 h,
 621                 void (*callback)(void *), void *data);
 622
 623 #endif