3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 * Seung-Woo Kim <sw0312.kim@samsung.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
26 * OTHER DEALINGS IN THE SOFTWARE.
29 #ifndef _UAPI_EXYNOS_DRM_H_
30 #define _UAPI_EXYNOS_DRM_H_
35 * User-desired buffer creation information structure.
37 * @size: user-desired memory allocation size.
38 * - this size value would be page-aligned internally.
39 * @flags: user request for setting memory type or cache attributes.
40 * @handle: returned a handle to created gem object.
41 * - this handle will be set by gem module of kernel side.
43 struct drm_exynos_gem_create {
50 * A structure for getting buffer offset.
52 * @handle: a pointer to gem object created.
53 * @pad: just padding to be 64-bit aligned.
54 * @offset: relatived offset value of the memory region allocated.
55 * - this value should be set by user.
57 struct drm_exynos_gem_map_off {
64 * A structure for mapping buffer.
66 * @handle: a handle to gem object created.
67 * @pad: just padding to be 64-bit aligned.
68 * @size: memory size to be mapped.
69 * @mapped: having user virtual address mmaped.
70 * - this variable would be filled by exynos gem module
71 * of kernel side with user virtual address which is allocated
74 struct drm_exynos_gem_mmap {
82 * A structure to gem information.
84 * @handle: a handle to gem object created.
85 * @flags: flag value including memory type and cache attribute and
86 * this value would be set by driver.
87 * @size: size to memory region allocated by gem and this size would
90 struct drm_exynos_gem_info {
97 * A structure for user connection request of virtual display.
99 * @connection: indicate whether doing connetion or not by user.
100 * @extensions: if this value is 1 then the vidi driver would need additional
101 * 128bytes edid data.
102 * @edid: the edid data pointer from user side.
104 struct drm_exynos_vidi_connection {
105 unsigned int connection;
106 unsigned int extensions;
110 /* memory type definitions. */
111 enum e_drm_exynos_gem_mem_type {
112 /* Physically Continuous memory and used as default. */
113 EXYNOS_BO_CONTIG = 0 << 0,
114 /* Physically Non-Continuous memory. */
115 EXYNOS_BO_NONCONTIG = 1 << 0,
116 /* non-cachable mapping and used as default. */
117 EXYNOS_BO_NONCACHABLE = 0 << 1,
118 /* cachable mapping. */
119 EXYNOS_BO_CACHABLE = 1 << 1,
120 /* write-combine mapping. */
121 EXYNOS_BO_WC = 1 << 2,
122 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
126 struct drm_exynos_g2d_get_ver {
131 struct drm_exynos_g2d_cmd {
136 enum drm_exynos_g2d_buf_type {
137 G2D_BUF_USERPTR = 1 << 31,
140 enum drm_exynos_g2d_event_type {
143 G2D_EVENT_STOP, /* not yet */
146 struct drm_exynos_g2d_userptr {
147 unsigned long userptr;
151 struct drm_exynos_g2d_set_cmdlist {
162 struct drm_exynos_g2d_exec {
166 enum drm_exynos_ops_id {
172 struct drm_exynos_sz {
177 struct drm_exynos_pos {
184 enum drm_exynos_flip {
185 EXYNOS_DRM_FLIP_NONE = (0 << 0),
186 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
187 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
190 enum drm_exynos_degree {
192 EXYNOS_DRM_DEGREE_90,
193 EXYNOS_DRM_DEGREE_180,
194 EXYNOS_DRM_DEGREE_270,
197 enum drm_exynos_planer {
199 EXYNOS_DRM_PLANAR_CB,
200 EXYNOS_DRM_PLANAR_CR,
201 EXYNOS_DRM_PLANAR_MAX,
205 * A structure for ipp supported property list.
207 * @version: version of this structure.
208 * @ipp_id: id of ipp driver.
209 * @count: count of ipp driver.
210 * @writeback: flag of writeback supporting.
211 * @flip: flag of flip supporting.
212 * @degree: flag of degree information.
213 * @csc: flag of csc supporting.
214 * @crop: flag of crop supporting.
215 * @scale: flag of scale supporting.
216 * @refresh_min: min hz of refresh.
217 * @refresh_max: max hz of refresh.
218 * @crop_min: crop min resolution.
219 * @crop_max: crop max resolution.
220 * @scale_min: scale min resolution.
221 * @scale_max: scale max resolution.
223 struct drm_exynos_ipp_prop_list {
236 struct drm_exynos_sz crop_min;
237 struct drm_exynos_sz crop_max;
238 struct drm_exynos_sz scale_min;
239 struct drm_exynos_sz scale_max;
243 * A structure for ipp config.
245 * @ops_id: property of operation directions.
246 * @flip: property of mirror, flip.
247 * @degree: property of rotation degree.
248 * @fmt: property of image format.
249 * @sz: property of image size.
250 * @pos: property of image position(src-cropped,dst-scaler).
252 struct drm_exynos_ipp_config {
253 enum drm_exynos_ops_id ops_id;
254 enum drm_exynos_flip flip;
255 enum drm_exynos_degree degree;
257 struct drm_exynos_sz sz;
258 struct drm_exynos_pos pos;
261 enum drm_exynos_ipp_cmd {
270 * A structure for ipp property.
272 * @config: source, destination config.
273 * @cmd: definition of command.
274 * @ipp_id: id of ipp driver.
275 * @prop_id: id of property.
276 * @refresh_rate: refresh rate.
278 struct drm_exynos_ipp_property {
279 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
280 enum drm_exynos_ipp_cmd cmd;
286 enum drm_exynos_ipp_buf_type {
292 * A structure for ipp buffer operations.
294 * @ops_id: operation directions.
295 * @buf_type: definition of buffer.
296 * @prop_id: id of property.
297 * @buf_id: id of buffer.
298 * @handle: Y, Cb, Cr each planar handle.
299 * @user_data: user data.
301 struct drm_exynos_ipp_queue_buf {
302 enum drm_exynos_ops_id ops_id;
303 enum drm_exynos_ipp_buf_type buf_type;
306 __u32 handle[EXYNOS_DRM_PLANAR_MAX];
311 enum drm_exynos_ipp_ctrl {
320 * A structure for ipp start/stop operations.
322 * @prop_id: id of property.
323 * @ctrl: definition of control.
325 struct drm_exynos_ipp_cmd_ctrl {
327 enum drm_exynos_ipp_ctrl ctrl;
330 #define DRM_EXYNOS_GEM_CREATE 0x00
331 #define DRM_EXYNOS_GEM_MAP_OFFSET 0x01
332 #define DRM_EXYNOS_GEM_MMAP 0x02
333 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
334 #define DRM_EXYNOS_GEM_GET 0x04
335 #define DRM_EXYNOS_VIDI_CONNECTION 0x07
338 #define DRM_EXYNOS_G2D_GET_VER 0x20
339 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
340 #define DRM_EXYNOS_G2D_EXEC 0x22
342 /* IPP - Image Post Processing */
343 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
344 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
345 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
346 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33
348 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
349 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
351 #define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
352 DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off)
354 #define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \
355 DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap)
357 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
358 DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
360 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
361 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
363 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
364 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
365 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
366 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
367 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
368 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
370 #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
371 DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
372 #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
373 DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
374 #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \
375 DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
376 #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \
377 DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
379 /* EXYNOS specific events */
380 #define DRM_EXYNOS_G2D_EVENT 0x80000000
381 #define DRM_EXYNOS_IPP_EVENT 0x80000001
383 struct drm_exynos_g2d_event {
384 struct drm_event base;
392 struct drm_exynos_ipp_event {
393 struct drm_event base;
399 __u32 buf_id[EXYNOS_DRM_OPS_MAX];
402 #endif /* _UAPI_EXYNOS_DRM_H_ */