4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/irqreturn.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn)
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot *slot)
64 return kobject_name(&slot->kobj);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
73 /* This defines the direction arg to the DMA mapping routines. */
74 #define PCI_DMA_BIDIRECTIONAL 0
75 #define PCI_DMA_TODEVICE 1
76 #define PCI_DMA_FROMDEVICE 2
77 #define PCI_DMA_NONE 3
80 * For PCI devices, the region numbers are assigned this way:
83 /* #0-5: standard PCI resources */
85 PCI_STD_RESOURCE_END = 5,
87 /* #6: expansion ROM resource */
90 /* device specific resources */
93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
96 /* resources assigned to buses behind the bridge */
97 #define PCI_BRIDGE_RESOURCE_NUM 4
100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101 PCI_BRIDGE_RESOURCE_NUM - 1,
103 /* total resources associated with a PCI device */
106 /* preserve this for compatibility */
107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
110 typedef int __bitwise pci_power_t;
112 #define PCI_D0 ((pci_power_t __force) 0)
113 #define PCI_D1 ((pci_power_t __force) 1)
114 #define PCI_D2 ((pci_power_t __force) 2)
115 #define PCI_D3hot ((pci_power_t __force) 3)
116 #define PCI_D3cold ((pci_power_t __force) 4)
117 #define PCI_UNKNOWN ((pci_power_t __force) 5)
118 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
120 /* Remember to update this when the list above changes! */
121 extern const char *pci_power_names[];
123 static inline const char *pci_power_name(pci_power_t state)
125 return pci_power_names[1 + (int) state];
128 #define PCI_PM_D2_DELAY 200
129 #define PCI_PM_D3_WAIT 10
130 #define PCI_PM_D3COLD_WAIT 100
131 #define PCI_PM_BUS_WAIT 50
133 /** The pci_channel state describes connectivity between the CPU and
134 * the pci device. If some PCI bus between here and the pci device
135 * has crashed or locked up, this info is reflected here.
137 typedef unsigned int __bitwise pci_channel_state_t;
139 enum pci_channel_state {
140 /* I/O channel is in normal state */
141 pci_channel_io_normal = (__force pci_channel_state_t) 1,
143 /* I/O to channel is blocked */
144 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
146 /* PCI card is dead */
147 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
150 typedef unsigned int __bitwise pcie_reset_state_t;
152 enum pcie_reset_state {
153 /* Reset is NOT asserted (Use to deassert reset) */
154 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
156 /* Use #PERST to reset PCIe device */
157 pcie_warm_reset = (__force pcie_reset_state_t) 2,
159 /* Use PCIe Hot Reset to reset device */
160 pcie_hot_reset = (__force pcie_reset_state_t) 3
163 typedef unsigned short __bitwise pci_dev_flags_t;
165 /* INTX_DISABLE in PCI_COMMAND register disables MSI
168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
169 /* Device configuration is irrevocably lost if disabled into D3 */
170 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
171 /* Provide indication device is assigned by a Virtual Machine Manager */
172 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
175 enum pci_irq_reroute_variant {
176 INTEL_IRQ_REROUTE_VARIANT = 1,
177 MAX_IRQ_REROUTE_VARIANTS = 3
180 typedef unsigned short __bitwise pci_bus_flags_t;
182 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
183 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
186 /* These values come from the PCI Express Spec */
187 enum pcie_link_width {
188 PCIE_LNK_WIDTH_RESRV = 0x00,
196 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
199 /* Based on the PCI Hotplug Spec, but some values are made up by us */
201 PCI_SPEED_33MHz = 0x00,
202 PCI_SPEED_66MHz = 0x01,
203 PCI_SPEED_66MHz_PCIX = 0x02,
204 PCI_SPEED_100MHz_PCIX = 0x03,
205 PCI_SPEED_133MHz_PCIX = 0x04,
206 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
207 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
208 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
209 PCI_SPEED_66MHz_PCIX_266 = 0x09,
210 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
211 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
217 PCI_SPEED_66MHz_PCIX_533 = 0x11,
218 PCI_SPEED_100MHz_PCIX_533 = 0x12,
219 PCI_SPEED_133MHz_PCIX_533 = 0x13,
220 PCIE_SPEED_2_5GT = 0x14,
221 PCIE_SPEED_5_0GT = 0x15,
222 PCIE_SPEED_8_0GT = 0x16,
223 PCI_SPEED_UNKNOWN = 0xff,
226 struct pci_cap_saved_data {
232 struct pci_cap_saved_state {
233 struct hlist_node next;
234 struct pci_cap_saved_data cap;
237 struct pcie_link_state;
243 * The pci_dev structure is used to describe PCI devices.
246 struct list_head bus_list; /* node in per-bus list */
247 struct pci_bus *bus; /* bus this device is on */
248 struct pci_bus *subordinate; /* bus this device bridges to */
250 void *sysdata; /* hook for sys-specific extension */
251 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
252 struct pci_slot *slot; /* Physical slot this device is in */
254 unsigned int devfn; /* encoded device & function index */
255 unsigned short vendor;
256 unsigned short device;
257 unsigned short subsystem_vendor;
258 unsigned short subsystem_device;
259 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
260 u8 revision; /* PCI revision, low byte of class word */
261 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
262 u8 pcie_cap; /* PCIe capability offset */
263 u8 msi_cap; /* MSI capability offset */
264 u8 msix_cap; /* MSI-X capability offset */
265 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
266 u8 rom_base_reg; /* which config register controls the ROM */
267 u8 pin; /* which interrupt pin this device uses */
268 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
270 struct pci_driver *driver; /* which driver has allocated this device */
271 u64 dma_mask; /* Mask of the bits of bus address this
272 device implements. Normally this is
273 0xffffffff. You only need to change
274 this if your device has broken DMA
275 or supports 64-bit transfers. */
277 struct device_dma_parameters dma_parms;
279 pci_power_t current_state; /* Current operating state. In ACPI-speak,
280 this is D0-D3, D0 being fully functional,
282 u8 pm_cap; /* PM capability offset */
283 unsigned int pme_support:5; /* Bitmask of states from which PME#
285 unsigned int pme_interrupt:1;
286 unsigned int pme_poll:1; /* Poll device's PME status bit */
287 unsigned int d1_support:1; /* Low power state D1 is supported */
288 unsigned int d2_support:1; /* Low power state D2 is supported */
289 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
290 unsigned int no_d3cold:1; /* D3cold is forbidden */
291 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
292 unsigned int mmio_always_on:1; /* disallow turning off io/mem
293 decoding during bar sizing */
294 unsigned int wakeup_prepared:1;
295 unsigned int runtime_d3cold:1; /* whether go through runtime
296 D3cold, not set for devices
297 powered on/off by the
298 corresponding bridge */
299 unsigned int d3_delay; /* D3->D0 transition time in ms */
300 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
302 #ifdef CONFIG_PCIEASPM
303 struct pcie_link_state *link_state; /* ASPM link state */
306 pci_channel_state_t error_state; /* current connectivity state */
307 struct device dev; /* Generic device interface */
309 int cfg_size; /* Size of configuration space */
312 * Instead of touching interrupt line and base address registers
313 * directly, use the values stored here. They might be different!
316 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
318 bool match_driver; /* Skip attaching driver */
319 /* These fields are used by common fixups */
320 unsigned int transparent:1; /* Subtractive decode PCI bridge */
321 unsigned int multifunction:1;/* Part of multi-function device */
322 /* keep track of device state */
323 unsigned int is_added:1;
324 unsigned int is_busmaster:1; /* device is busmaster */
325 unsigned int no_msi:1; /* device may not use msi */
326 unsigned int block_cfg_access:1; /* config space access is blocked */
327 unsigned int broken_parity_status:1; /* Device generates false positive parity */
328 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
329 unsigned int msi_enabled:1;
330 unsigned int msix_enabled:1;
331 unsigned int ari_enabled:1; /* ARI forwarding */
332 unsigned int is_managed:1;
333 unsigned int needs_freset:1; /* Dev requires fundamental reset */
334 unsigned int state_saved:1;
335 unsigned int is_physfn:1;
336 unsigned int is_virtfn:1;
337 unsigned int reset_fn:1;
338 unsigned int is_hotplug_bridge:1;
339 unsigned int __aer_firmware_first_valid:1;
340 unsigned int __aer_firmware_first:1;
341 unsigned int broken_intx_masking:1;
342 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
343 pci_dev_flags_t dev_flags;
344 atomic_t enable_cnt; /* pci_enable_device has been called */
346 u32 saved_config_space[16]; /* config space saved at suspend time */
347 struct hlist_head saved_cap_space;
348 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
349 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
350 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
351 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
352 #ifdef CONFIG_PCI_MSI
353 struct list_head msi_list;
354 struct kset *msi_kset;
357 #ifdef CONFIG_PCI_ATS
359 struct pci_sriov *sriov; /* SR-IOV capability related */
360 struct pci_dev *physfn; /* the PF this VF is associated with */
362 struct pci_ats *ats; /* Address Translation Service */
364 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
365 size_t romlen; /* Length of ROM if it's not from the BAR */
368 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
370 #ifdef CONFIG_PCI_IOV
377 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
378 struct pci_dev * __deprecated alloc_pci_dev(void);
380 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
381 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
383 static inline int pci_channel_offline(struct pci_dev *pdev)
385 return (pdev->error_state != pci_channel_io_normal);
388 extern struct resource busn_resource;
390 struct pci_host_bridge_window {
391 struct list_head list;
392 struct resource *res; /* host bridge aperture (CPU address) */
393 resource_size_t offset; /* bus address + offset = CPU address */
396 struct pci_host_bridge {
398 struct pci_bus *bus; /* root bus */
399 struct list_head windows; /* pci_host_bridge_windows */
400 void (*release_fn)(struct pci_host_bridge *);
404 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
405 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
406 void (*release_fn)(struct pci_host_bridge *),
409 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
412 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
413 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
414 * buses below host bridges or subtractive decode bridges) go in the list.
415 * Use pci_bus_for_each_resource() to iterate through all the resources.
419 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
420 * and there's no way to program the bridge with the details of the window.
421 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
422 * decode bit set, because they are explicit and can be programmed with _SRS.
424 #define PCI_SUBTRACTIVE_DECODE 0x1
426 struct pci_bus_resource {
427 struct list_head list;
428 struct resource *res;
432 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
435 struct list_head node; /* node in list of buses */
436 struct pci_bus *parent; /* parent bus this bridge is on */
437 struct list_head children; /* list of child buses */
438 struct list_head devices; /* list of devices on this bus */
439 struct pci_dev *self; /* bridge device as seen by parent */
440 struct list_head slots; /* list of slots on this bus */
441 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
442 struct list_head resources; /* address space routed to this bus */
443 struct resource busn_res; /* bus numbers routed to this bus */
445 struct pci_ops *ops; /* configuration access functions */
446 struct msi_chip *msi; /* MSI controller */
447 void *sysdata; /* hook for sys-specific extension */
448 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
450 unsigned char number; /* bus number */
451 unsigned char primary; /* number of primary bridge */
452 unsigned char max_bus_speed; /* enum pci_bus_speed */
453 unsigned char cur_bus_speed; /* enum pci_bus_speed */
457 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
458 pci_bus_flags_t bus_flags; /* inherited by child buses */
459 struct device *bridge;
461 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
462 struct bin_attribute *legacy_mem; /* legacy mem */
463 unsigned int is_added:1;
466 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
467 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
470 * Returns true if the PCI bus is root (behind host-PCI bridge),
473 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
474 * This is incorrect because "virtual" buses added for SR-IOV (via
475 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
477 static inline bool pci_is_root_bus(struct pci_bus *pbus)
479 return !(pbus->parent);
482 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
484 dev = pci_physfn(dev);
485 if (pci_is_root_bus(dev->bus))
488 return dev->bus->self;
491 #ifdef CONFIG_PCI_MSI
492 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
494 return pci_dev->msi_enabled || pci_dev->msix_enabled;
497 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
501 * Error values that may be returned by PCI functions.
503 #define PCIBIOS_SUCCESSFUL 0x00
504 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
505 #define PCIBIOS_BAD_VENDOR_ID 0x83
506 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
507 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
508 #define PCIBIOS_SET_FAILED 0x88
509 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
512 * Translate above to generic errno for passing back through non-PCI code.
514 static inline int pcibios_err_to_errno(int err)
516 if (err <= PCIBIOS_SUCCESSFUL)
517 return err; /* Assume already errno */
520 case PCIBIOS_FUNC_NOT_SUPPORTED:
522 case PCIBIOS_BAD_VENDOR_ID:
524 case PCIBIOS_DEVICE_NOT_FOUND:
526 case PCIBIOS_BAD_REGISTER_NUMBER:
528 case PCIBIOS_SET_FAILED:
530 case PCIBIOS_BUFFER_TOO_SMALL:
537 /* Low-level architecture-dependent routines */
540 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
541 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
545 * ACPI needs to be able to access PCI config space before we've done a
546 * PCI bus scan and created pci_bus structures.
548 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
549 int reg, int len, u32 *val);
550 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
551 int reg, int len, u32 val);
553 struct pci_bus_region {
554 resource_size_t start;
559 spinlock_t lock; /* protects list, index */
560 struct list_head list; /* for IDs added at runtime */
565 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
566 * a set of callbacks in struct pci_error_handlers, that device driver
567 * will be notified of PCI bus errors, and will be driven to recovery
568 * when an error occurs.
571 typedef unsigned int __bitwise pci_ers_result_t;
573 enum pci_ers_result {
574 /* no result/none/not supported in device driver */
575 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
577 /* Device driver can recover without slot reset */
578 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
580 /* Device driver wants slot to be reset. */
581 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
583 /* Device has completely failed, is unrecoverable */
584 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
586 /* Device driver is fully recovered and operational */
587 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
589 /* No AER capabilities registered for the driver */
590 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
593 /* PCI bus error event callbacks */
594 struct pci_error_handlers {
595 /* PCI bus error detected on this device */
596 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
597 enum pci_channel_state error);
599 /* MMIO has been re-enabled, but not DMA */
600 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
602 /* PCI Express link has been reset */
603 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
605 /* PCI slot has been reset */
606 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
608 /* Device driver may resume normal operations */
609 void (*resume)(struct pci_dev *dev);
615 struct list_head node;
617 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
618 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
619 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
620 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
621 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
622 int (*resume_early) (struct pci_dev *dev);
623 int (*resume) (struct pci_dev *dev); /* Device woken up */
624 void (*shutdown) (struct pci_dev *dev);
625 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
626 const struct pci_error_handlers *err_handler;
627 struct device_driver driver;
628 struct pci_dynids dynids;
631 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
634 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
635 * @_table: device table name
637 * This macro is used to create a struct pci_device_id array (a device table)
638 * in a generic manner.
640 #define DEFINE_PCI_DEVICE_TABLE(_table) \
641 const struct pci_device_id _table[]
644 * PCI_DEVICE - macro used to describe a specific pci device
645 * @vend: the 16 bit PCI Vendor ID
646 * @dev: the 16 bit PCI Device ID
648 * This macro is used to create a struct pci_device_id that matches a
649 * specific device. The subvendor and subdevice fields will be set to
652 #define PCI_DEVICE(vend,dev) \
653 .vendor = (vend), .device = (dev), \
654 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
657 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
658 * @vend: the 16 bit PCI Vendor ID
659 * @dev: the 16 bit PCI Device ID
660 * @subvend: the 16 bit PCI Subvendor ID
661 * @subdev: the 16 bit PCI Subdevice ID
663 * This macro is used to create a struct pci_device_id that matches a
664 * specific device with subsystem information.
666 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
667 .vendor = (vend), .device = (dev), \
668 .subvendor = (subvend), .subdevice = (subdev)
671 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
672 * @dev_class: the class, subclass, prog-if triple for this device
673 * @dev_class_mask: the class mask for this device
675 * This macro is used to create a struct pci_device_id that matches a
676 * specific PCI class. The vendor, device, subvendor, and subdevice
677 * fields will be set to PCI_ANY_ID.
679 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
680 .class = (dev_class), .class_mask = (dev_class_mask), \
681 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
682 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
685 * PCI_VDEVICE - macro used to describe a specific pci device in short form
686 * @vendor: the vendor name
687 * @device: the 16 bit PCI Device ID
689 * This macro is used to create a struct pci_device_id that matches a
690 * specific PCI device. The subvendor, and subdevice fields will be set
691 * to PCI_ANY_ID. The macro allows the next field to follow as the device
695 #define PCI_VDEVICE(vendor, device) \
696 PCI_VENDOR_ID_##vendor, (device), \
697 PCI_ANY_ID, PCI_ANY_ID, 0, 0
699 /* these external functions are only available when PCI support is enabled */
702 void pcie_bus_configure_settings(struct pci_bus *bus);
704 enum pcie_bus_config_types {
707 PCIE_BUS_PERFORMANCE,
711 extern enum pcie_bus_config_types pcie_bus_config;
713 extern struct bus_type pci_bus_type;
715 /* Do NOT directly access these two variables, unless you are arch-specific PCI
716 * code, or PCI core code. */
717 extern struct list_head pci_root_buses; /* list of all known PCI buses */
718 /* Some device drivers need know if PCI is initiated */
719 int no_pci_devices(void);
721 void pcibios_resource_survey_bus(struct pci_bus *bus);
722 void pcibios_add_bus(struct pci_bus *bus);
723 void pcibios_remove_bus(struct pci_bus *bus);
724 void pcibios_fixup_bus(struct pci_bus *);
725 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
726 /* Architecture-specific versions may override this (weak) */
727 char *pcibios_setup(char *str);
729 /* Used only when drivers/pci/setup.c is used */
730 resource_size_t pcibios_align_resource(void *, const struct resource *,
733 void pcibios_update_irq(struct pci_dev *, int irq);
735 /* Weak but can be overriden by arch */
736 void pci_fixup_cardbus(struct pci_bus *);
738 /* Generic PCI functions used internally */
740 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
741 struct resource *res);
742 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
743 struct pci_bus_region *region);
744 void pcibios_scan_specific_bus(int busn);
745 struct pci_bus *pci_find_bus(int domain, int busnr);
746 void pci_bus_add_devices(const struct pci_bus *bus);
747 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
748 struct pci_ops *ops, void *sysdata);
749 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
750 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
751 struct pci_ops *ops, void *sysdata,
752 struct list_head *resources);
753 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
754 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
755 void pci_bus_release_busn_res(struct pci_bus *b);
756 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
757 struct pci_ops *ops, void *sysdata,
758 struct list_head *resources);
759 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
761 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
762 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
764 struct hotplug_slot *hotplug);
765 void pci_destroy_slot(struct pci_slot *slot);
766 int pci_scan_slot(struct pci_bus *bus, int devfn);
767 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
768 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
769 unsigned int pci_scan_child_bus(struct pci_bus *bus);
770 int __must_check pci_bus_add_device(struct pci_dev *dev);
771 void pci_read_bridge_bases(struct pci_bus *child);
772 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
773 struct resource *res);
774 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
775 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
776 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
777 struct pci_dev *pci_dev_get(struct pci_dev *dev);
778 void pci_dev_put(struct pci_dev *dev);
779 void pci_remove_bus(struct pci_bus *b);
780 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
781 void pci_stop_root_bus(struct pci_bus *bus);
782 void pci_remove_root_bus(struct pci_bus *bus);
783 void pci_setup_cardbus(struct pci_bus *bus);
784 void pci_sort_breadthfirst(void);
785 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
786 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
787 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
789 /* Generic PCI functions exported to card drivers */
791 enum pci_lost_interrupt_reason {
792 PCI_LOST_IRQ_NO_INFORMATION = 0,
793 PCI_LOST_IRQ_DISABLE_MSI,
794 PCI_LOST_IRQ_DISABLE_MSIX,
795 PCI_LOST_IRQ_DISABLE_ACPI,
797 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
798 int pci_find_capability(struct pci_dev *dev, int cap);
799 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
800 int pci_find_ext_capability(struct pci_dev *dev, int cap);
801 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
802 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
803 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
804 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
806 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
807 struct pci_dev *from);
808 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
809 unsigned int ss_vendor, unsigned int ss_device,
810 struct pci_dev *from);
811 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
812 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
814 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
817 return pci_get_domain_bus_and_slot(0, bus, devfn);
819 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
820 int pci_dev_present(const struct pci_device_id *ids);
822 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
824 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
825 int where, u16 *val);
826 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
827 int where, u32 *val);
828 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
830 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
832 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
834 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
836 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
838 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
840 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
842 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
844 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
847 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
849 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
851 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
853 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
855 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
857 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
860 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
863 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
864 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
865 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
866 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
867 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
869 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
872 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
875 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
878 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
881 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
884 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
887 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
890 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
893 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
896 /* user-space driven config access */
897 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
898 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
899 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
900 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
901 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
902 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
904 int __must_check pci_enable_device(struct pci_dev *dev);
905 int __must_check pci_enable_device_io(struct pci_dev *dev);
906 int __must_check pci_enable_device_mem(struct pci_dev *dev);
907 int __must_check pci_reenable_device(struct pci_dev *);
908 int __must_check pcim_enable_device(struct pci_dev *pdev);
909 void pcim_pin_device(struct pci_dev *pdev);
911 static inline int pci_is_enabled(struct pci_dev *pdev)
913 return (atomic_read(&pdev->enable_cnt) > 0);
916 static inline int pci_is_managed(struct pci_dev *pdev)
918 return pdev->is_managed;
921 void pci_disable_device(struct pci_dev *dev);
923 extern unsigned int pcibios_max_latency;
924 void pci_set_master(struct pci_dev *dev);
925 void pci_clear_master(struct pci_dev *dev);
927 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
928 int pci_set_cacheline_size(struct pci_dev *dev);
929 #define HAVE_PCI_SET_MWI
930 int __must_check pci_set_mwi(struct pci_dev *dev);
931 int pci_try_set_mwi(struct pci_dev *dev);
932 void pci_clear_mwi(struct pci_dev *dev);
933 void pci_intx(struct pci_dev *dev, int enable);
934 bool pci_intx_mask_supported(struct pci_dev *dev);
935 bool pci_check_and_mask_intx(struct pci_dev *dev);
936 bool pci_check_and_unmask_intx(struct pci_dev *dev);
937 void pci_msi_off(struct pci_dev *dev);
938 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
939 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
940 int pci_wait_for_pending_transaction(struct pci_dev *dev);
941 int pcix_get_max_mmrbc(struct pci_dev *dev);
942 int pcix_get_mmrbc(struct pci_dev *dev);
943 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
944 int pcie_get_readrq(struct pci_dev *dev);
945 int pcie_set_readrq(struct pci_dev *dev, int rq);
946 int pcie_get_mps(struct pci_dev *dev);
947 int pcie_set_mps(struct pci_dev *dev, int mps);
948 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
949 enum pcie_link_width *width);
950 int __pci_reset_function(struct pci_dev *dev);
951 int __pci_reset_function_locked(struct pci_dev *dev);
952 int pci_reset_function(struct pci_dev *dev);
953 int pci_probe_reset_slot(struct pci_slot *slot);
954 int pci_reset_slot(struct pci_slot *slot);
955 int pci_probe_reset_bus(struct pci_bus *bus);
956 int pci_reset_bus(struct pci_bus *bus);
957 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
958 void pci_update_resource(struct pci_dev *dev, int resno);
959 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
960 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
961 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
963 /* ROM control related routines */
964 int pci_enable_rom(struct pci_dev *pdev);
965 void pci_disable_rom(struct pci_dev *pdev);
966 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
967 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
968 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
969 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
971 /* Power management related routines */
972 int pci_save_state(struct pci_dev *dev);
973 void pci_restore_state(struct pci_dev *dev);
974 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
975 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
976 int pci_load_and_free_saved_state(struct pci_dev *dev,
977 struct pci_saved_state **state);
978 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
979 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
980 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
981 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
982 void pci_pme_active(struct pci_dev *dev, bool enable);
983 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
984 bool runtime, bool enable);
985 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
986 pci_power_t pci_target_state(struct pci_dev *dev);
987 int pci_prepare_to_sleep(struct pci_dev *dev);
988 int pci_back_from_sleep(struct pci_dev *dev);
989 bool pci_dev_run_wake(struct pci_dev *dev);
990 bool pci_check_pme_status(struct pci_dev *dev);
991 void pci_pme_wakeup_bus(struct pci_bus *bus);
993 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
996 return __pci_enable_wake(dev, state, false, enable);
999 /* For use by arch with custom probe code */
1000 void set_pcie_port_type(struct pci_dev *pdev);
1001 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1003 /* Functions for PCI Hotplug drivers to use */
1004 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1005 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1006 unsigned int pci_rescan_bus(struct pci_bus *bus);
1008 /* Vital product data routines */
1009 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1010 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1012 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1013 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1014 void pci_bus_assign_resources(const struct pci_bus *bus);
1015 void pci_bus_size_bridges(struct pci_bus *bus);
1016 int pci_claim_resource(struct pci_dev *, int);
1017 void pci_assign_unassigned_resources(void);
1018 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1019 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1020 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1021 void pdev_enable_device(struct pci_dev *);
1022 int pci_enable_resources(struct pci_dev *, int mask);
1023 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1024 int (*)(const struct pci_dev *, u8, u8));
1025 #define HAVE_PCI_REQ_REGIONS 2
1026 int __must_check pci_request_regions(struct pci_dev *, const char *);
1027 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1028 void pci_release_regions(struct pci_dev *);
1029 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1030 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1031 void pci_release_region(struct pci_dev *, int);
1032 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1033 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1034 void pci_release_selected_regions(struct pci_dev *, int);
1036 /* drivers/pci/bus.c */
1037 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1038 void pci_bus_put(struct pci_bus *bus);
1039 void pci_add_resource(struct list_head *resources, struct resource *res);
1040 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1041 resource_size_t offset);
1042 void pci_free_resource_list(struct list_head *resources);
1043 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1044 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1045 void pci_bus_remove_resources(struct pci_bus *bus);
1047 #define pci_bus_for_each_resource(bus, res, i) \
1049 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1052 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1053 struct resource *res, resource_size_t size,
1054 resource_size_t align, resource_size_t min,
1055 unsigned int type_mask,
1056 resource_size_t (*alignf)(void *,
1057 const struct resource *,
1062 /* Proper probing supporting hot-pluggable devices */
1063 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1064 const char *mod_name);
1067 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1069 #define pci_register_driver(driver) \
1070 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1072 void pci_unregister_driver(struct pci_driver *dev);
1075 * module_pci_driver() - Helper macro for registering a PCI driver
1076 * @__pci_driver: pci_driver struct
1078 * Helper macro for PCI drivers which do not do anything special in module
1079 * init/exit. This eliminates a lot of boilerplate. Each module may only
1080 * use this macro once, and calling it replaces module_init() and module_exit()
1082 #define module_pci_driver(__pci_driver) \
1083 module_driver(__pci_driver, pci_register_driver, \
1084 pci_unregister_driver)
1086 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1087 int pci_add_dynid(struct pci_driver *drv,
1088 unsigned int vendor, unsigned int device,
1089 unsigned int subvendor, unsigned int subdevice,
1090 unsigned int class, unsigned int class_mask,
1091 unsigned long driver_data);
1092 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1093 struct pci_dev *dev);
1094 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1097 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1099 int pci_cfg_space_size_ext(struct pci_dev *dev);
1100 int pci_cfg_space_size(struct pci_dev *dev);
1101 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1102 void pci_setup_bridge(struct pci_bus *bus);
1103 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1104 unsigned long type);
1106 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1107 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1109 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1110 unsigned int command_bits, u32 flags);
1111 /* kmem_cache style wrapper around pci_alloc_consistent() */
1113 #include <linux/pci-dma.h>
1114 #include <linux/dmapool.h>
1116 #define pci_pool dma_pool
1117 #define pci_pool_create(name, pdev, size, align, allocation) \
1118 dma_pool_create(name, &pdev->dev, size, align, allocation)
1119 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1120 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1121 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1123 enum pci_dma_burst_strategy {
1124 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1125 strategy_parameter is N/A */
1126 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1128 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1129 strategy_parameter byte boundaries */
1133 u32 vector; /* kernel uses to write allocated vector */
1134 u16 entry; /* driver uses to specify entry, OS writes */
1138 #ifndef CONFIG_PCI_MSI
1139 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1145 pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
1150 static inline void pci_msi_shutdown(struct pci_dev *dev)
1152 static inline void pci_disable_msi(struct pci_dev *dev)
1155 static inline int pci_msix_table_size(struct pci_dev *dev)
1159 static inline int pci_enable_msix(struct pci_dev *dev,
1160 struct msix_entry *entries, int nvec)
1165 static inline void pci_msix_shutdown(struct pci_dev *dev)
1167 static inline void pci_disable_msix(struct pci_dev *dev)
1170 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1173 static inline void pci_restore_msi_state(struct pci_dev *dev)
1175 static inline int pci_msi_enabled(void)
1180 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1181 int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec);
1182 void pci_msi_shutdown(struct pci_dev *dev);
1183 void pci_disable_msi(struct pci_dev *dev);
1184 int pci_msix_table_size(struct pci_dev *dev);
1185 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1186 void pci_msix_shutdown(struct pci_dev *dev);
1187 void pci_disable_msix(struct pci_dev *dev);
1188 void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1189 void pci_restore_msi_state(struct pci_dev *dev);
1190 int pci_msi_enabled(void);
1193 #ifdef CONFIG_PCIEPORTBUS
1194 extern bool pcie_ports_disabled;
1195 extern bool pcie_ports_auto;
1197 #define pcie_ports_disabled true
1198 #define pcie_ports_auto false
1201 #ifndef CONFIG_PCIEASPM
1202 static inline bool pcie_aspm_support_enabled(void) { return false; }
1204 bool pcie_aspm_support_enabled(void);
1207 #ifdef CONFIG_PCIEAER
1208 void pci_no_aer(void);
1209 bool pci_aer_available(void);
1211 static inline void pci_no_aer(void) { }
1212 static inline bool pci_aer_available(void) { return false; }
1215 #ifndef CONFIG_PCIE_ECRC
1216 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1220 static inline void pcie_ecrc_get_policy(char *str) {};
1222 void pcie_set_ecrc_checking(struct pci_dev *dev);
1223 void pcie_ecrc_get_policy(char *str);
1226 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1228 #ifdef CONFIG_HT_IRQ
1229 /* The functions a driver should call */
1230 int ht_create_irq(struct pci_dev *dev, int idx);
1231 void ht_destroy_irq(unsigned int irq);
1232 #endif /* CONFIG_HT_IRQ */
1234 void pci_cfg_access_lock(struct pci_dev *dev);
1235 bool pci_cfg_access_trylock(struct pci_dev *dev);
1236 void pci_cfg_access_unlock(struct pci_dev *dev);
1239 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1240 * a PCI domain is defined to be a set of PCI buses which share
1241 * configuration space.
1243 #ifdef CONFIG_PCI_DOMAINS
1244 extern int pci_domains_supported;
1246 enum { pci_domains_supported = 0 };
1247 static inline int pci_domain_nr(struct pci_bus *bus)
1252 static inline int pci_proc_domain(struct pci_bus *bus)
1256 #endif /* CONFIG_PCI_DOMAINS */
1258 /* some architectures require additional setup to direct VGA traffic */
1259 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1260 unsigned int command_bits, u32 flags);
1261 void pci_register_set_vga_state(arch_set_vga_state_t func);
1263 #else /* CONFIG_PCI is not enabled */
1266 * If the system does not have PCI, clearly these return errors. Define
1267 * these as simple inline functions to avoid hair in drivers.
1270 #define _PCI_NOP(o, s, t) \
1271 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1273 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1275 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1276 _PCI_NOP(o, word, u16 x) \
1277 _PCI_NOP(o, dword, u32 x)
1278 _PCI_NOP_ALL(read, *)
1279 _PCI_NOP_ALL(write,)
1281 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1282 unsigned int device,
1283 struct pci_dev *from)
1288 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1289 unsigned int device,
1290 unsigned int ss_vendor,
1291 unsigned int ss_device,
1292 struct pci_dev *from)
1297 static inline struct pci_dev *pci_get_class(unsigned int class,
1298 struct pci_dev *from)
1303 #define pci_dev_present(ids) (0)
1304 #define no_pci_devices() (1)
1305 #define pci_dev_put(dev) do { } while (0)
1307 static inline void pci_set_master(struct pci_dev *dev)
1310 static inline int pci_enable_device(struct pci_dev *dev)
1315 static inline void pci_disable_device(struct pci_dev *dev)
1318 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1323 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1328 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1334 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1340 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1345 static inline int __pci_register_driver(struct pci_driver *drv,
1346 struct module *owner)
1351 static inline int pci_register_driver(struct pci_driver *drv)
1356 static inline void pci_unregister_driver(struct pci_driver *drv)
1359 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1364 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1370 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1375 /* Power management related routines */
1376 static inline int pci_save_state(struct pci_dev *dev)
1381 static inline void pci_restore_state(struct pci_dev *dev)
1384 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1389 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1394 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1400 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1406 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1411 static inline void pci_release_regions(struct pci_dev *dev)
1414 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1416 static inline void pci_block_cfg_access(struct pci_dev *dev)
1419 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1422 static inline void pci_unblock_cfg_access(struct pci_dev *dev)
1425 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1428 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1432 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1436 static inline int pci_domain_nr(struct pci_bus *bus)
1439 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
1442 #define dev_is_pci(d) (false)
1443 #define dev_is_pf(d) (false)
1444 #define dev_num_vf(d) (0)
1445 #endif /* CONFIG_PCI */
1447 /* Include architecture-dependent settings and functions */
1449 #include <asm/pci.h>
1451 #ifndef PCIBIOS_MAX_MEM_32
1452 #define PCIBIOS_MAX_MEM_32 (-1)
1455 /* these helpers provide future and backwards compatibility
1456 * for accessing popular PCI BAR info */
1457 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1458 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1459 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1460 #define pci_resource_len(dev,bar) \
1461 ((pci_resource_start((dev), (bar)) == 0 && \
1462 pci_resource_end((dev), (bar)) == \
1463 pci_resource_start((dev), (bar))) ? 0 : \
1465 (pci_resource_end((dev), (bar)) - \
1466 pci_resource_start((dev), (bar)) + 1))
1468 /* Similar to the helpers above, these manipulate per-pci_dev
1469 * driver-specific data. They are really just a wrapper around
1470 * the generic device structure functions of these calls.
1472 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1474 return dev_get_drvdata(&pdev->dev);
1477 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1479 dev_set_drvdata(&pdev->dev, data);
1482 /* If you want to know what to call your pci_dev, ask this function.
1483 * Again, it's a wrapper around the generic device.
1485 static inline const char *pci_name(const struct pci_dev *pdev)
1487 return dev_name(&pdev->dev);
1491 /* Some archs don't want to expose struct resource to userland as-is
1492 * in sysfs and /proc
1494 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1495 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1496 const struct resource *rsrc, resource_size_t *start,
1497 resource_size_t *end)
1499 *start = rsrc->start;
1502 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1506 * The world is not perfect and supplies us with broken PCI devices.
1507 * For at least a part of these bugs we need a work-around, so both
1508 * generic (drivers/pci/quirks.c) and per-architecture code can define
1509 * fixup hooks to be called for particular buggy devices.
1513 u16 vendor; /* You can use PCI_ANY_ID here of course */
1514 u16 device; /* You can use PCI_ANY_ID here of course */
1515 u32 class; /* You can use PCI_ANY_ID here too */
1516 unsigned int class_shift; /* should be 0, 8, 16 */
1517 void (*hook)(struct pci_dev *dev);
1520 enum pci_fixup_pass {
1521 pci_fixup_early, /* Before probing BARs */
1522 pci_fixup_header, /* After reading configuration header */
1523 pci_fixup_final, /* Final phase of device fixups */
1524 pci_fixup_enable, /* pci_enable_device() time */
1525 pci_fixup_resume, /* pci_device_resume() */
1526 pci_fixup_suspend, /* pci_device_suspend */
1527 pci_fixup_resume_early, /* pci_device_resume_early() */
1530 /* Anonymous variables would be nice... */
1531 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1532 class_shift, hook) \
1533 static const struct pci_fixup __pci_fixup_##name __used \
1534 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1535 = { vendor, device, class, class_shift, hook };
1537 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1538 class_shift, hook) \
1539 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1540 vendor##device##hook, vendor, device, class, class_shift, hook)
1541 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1542 class_shift, hook) \
1543 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1544 vendor##device##hook, vendor, device, class, class_shift, hook)
1545 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1546 class_shift, hook) \
1547 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1548 vendor##device##hook, vendor, device, class, class_shift, hook)
1549 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1550 class_shift, hook) \
1551 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1552 vendor##device##hook, vendor, device, class, class_shift, hook)
1553 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1554 class_shift, hook) \
1555 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1556 resume##vendor##device##hook, vendor, device, class, \
1558 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1559 class_shift, hook) \
1560 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1561 resume_early##vendor##device##hook, vendor, device, \
1562 class, class_shift, hook)
1563 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1564 class_shift, hook) \
1565 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1566 suspend##vendor##device##hook, vendor, device, class, \
1569 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1570 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1571 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1572 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1573 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1574 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1575 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1576 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1577 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1578 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1579 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1580 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1581 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1582 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1583 resume##vendor##device##hook, vendor, device, \
1584 PCI_ANY_ID, 0, hook)
1585 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1586 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1587 resume_early##vendor##device##hook, vendor, device, \
1588 PCI_ANY_ID, 0, hook)
1589 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1590 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1591 suspend##vendor##device##hook, vendor, device, \
1592 PCI_ANY_ID, 0, hook)
1594 #ifdef CONFIG_PCI_QUIRKS
1595 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1596 struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1597 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1599 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1600 struct pci_dev *dev) {}
1601 static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1603 return pci_dev_get(dev);
1605 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1612 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1613 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1614 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1615 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1616 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1618 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1620 extern int pci_pci_problems;
1621 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1622 #define PCIPCI_TRITON 2
1623 #define PCIPCI_NATOMA 4
1624 #define PCIPCI_VIAETBF 8
1625 #define PCIPCI_VSFX 16
1626 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1627 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1629 extern unsigned long pci_cardbus_io_size;
1630 extern unsigned long pci_cardbus_mem_size;
1631 extern u8 pci_dfl_cache_line_size;
1632 extern u8 pci_cache_line_size;
1634 extern unsigned long pci_hotplug_io_size;
1635 extern unsigned long pci_hotplug_mem_size;
1637 /* Architecture-specific versions may override these (weak) */
1638 int pcibios_add_platform_entries(struct pci_dev *dev);
1639 void pcibios_disable_device(struct pci_dev *dev);
1640 void pcibios_set_master(struct pci_dev *dev);
1641 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1642 enum pcie_reset_state state);
1643 int pcibios_add_device(struct pci_dev *dev);
1644 void pcibios_release_device(struct pci_dev *dev);
1646 #ifdef CONFIG_HIBERNATE_CALLBACKS
1647 extern struct dev_pm_ops pcibios_pm_ops;
1650 #ifdef CONFIG_PCI_MMCONFIG
1651 void __init pci_mmcfg_early_init(void);
1652 void __init pci_mmcfg_late_init(void);
1654 static inline void pci_mmcfg_early_init(void) { }
1655 static inline void pci_mmcfg_late_init(void) { }
1658 int pci_ext_cfg_avail(void);
1660 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1662 #ifdef CONFIG_PCI_IOV
1663 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1664 void pci_disable_sriov(struct pci_dev *dev);
1665 irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1666 int pci_num_vf(struct pci_dev *dev);
1667 int pci_vfs_assigned(struct pci_dev *dev);
1668 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1669 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1671 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1675 static inline void pci_disable_sriov(struct pci_dev *dev)
1678 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1682 static inline int pci_num_vf(struct pci_dev *dev)
1686 static inline int pci_vfs_assigned(struct pci_dev *dev)
1690 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1694 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1700 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1701 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1702 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1706 * pci_pcie_cap - get the saved PCIe capability offset
1709 * PCIe capability offset is calculated at PCI device initialization
1710 * time and saved in the data structure. This function returns saved
1711 * PCIe capability offset. Using this instead of pci_find_capability()
1712 * reduces unnecessary search in the PCI configuration space. If you
1713 * need to calculate PCIe capability offset from raw device for some
1714 * reasons, please use pci_find_capability() instead.
1716 static inline int pci_pcie_cap(struct pci_dev *dev)
1718 return dev->pcie_cap;
1722 * pci_is_pcie - check if the PCI device is PCI Express capable
1725 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1727 static inline bool pci_is_pcie(struct pci_dev *dev)
1729 return pci_pcie_cap(dev);
1733 * pcie_caps_reg - get the PCIe Capabilities Register
1736 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1738 return dev->pcie_flags_reg;
1742 * pci_pcie_type - get the PCIe device/port type
1745 static inline int pci_pcie_type(const struct pci_dev *dev)
1747 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1750 void pci_request_acs(void);
1751 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1752 bool pci_acs_path_enabled(struct pci_dev *start,
1753 struct pci_dev *end, u16 acs_flags);
1755 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1756 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1758 /* Large Resource Data Type Tag Item Names */
1759 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1760 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1761 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1763 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1764 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1765 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1767 /* Small Resource Data Type Tag Item Names */
1768 #define PCI_VPD_STIN_END 0x78 /* End */
1770 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1772 #define PCI_VPD_SRDT_TIN_MASK 0x78
1773 #define PCI_VPD_SRDT_LEN_MASK 0x07
1775 #define PCI_VPD_LRDT_TAG_SIZE 3
1776 #define PCI_VPD_SRDT_TAG_SIZE 1
1778 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1780 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1781 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1782 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1783 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1786 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1787 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1789 * Returns the extracted Large Resource Data Type length.
1791 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1793 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1797 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1798 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1800 * Returns the extracted Small Resource Data Type length.
1802 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1804 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1808 * pci_vpd_info_field_size - Extracts the information field length
1809 * @lrdt: Pointer to the beginning of an information field header
1811 * Returns the extracted information field length.
1813 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1815 return info_field[2];
1819 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1820 * @buf: Pointer to buffered vpd data
1821 * @off: The offset into the buffer at which to begin the search
1822 * @len: The length of the vpd buffer
1823 * @rdt: The Resource Data Type to search for
1825 * Returns the index where the Resource Data Type was found or
1826 * -ENOENT otherwise.
1828 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1831 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1832 * @buf: Pointer to buffered vpd data
1833 * @off: The offset into the buffer at which to begin the search
1834 * @len: The length of the buffer area, relative to off, in which to search
1835 * @kw: The keyword to search for
1837 * Returns the index where the information field keyword was found or
1838 * -ENOENT otherwise.
1840 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1841 unsigned int len, const char *kw);
1843 /* PCI <-> OF binding helpers */
1846 void pci_set_of_node(struct pci_dev *dev);
1847 void pci_release_of_node(struct pci_dev *dev);
1848 void pci_set_bus_of_node(struct pci_bus *bus);
1849 void pci_release_bus_of_node(struct pci_bus *bus);
1851 /* Arch may override this (weak) */
1852 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1854 static inline struct device_node *
1855 pci_device_to_OF_node(const struct pci_dev *pdev)
1857 return pdev ? pdev->dev.of_node : NULL;
1860 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1862 return bus ? bus->dev.of_node : NULL;
1865 #else /* CONFIG_OF */
1866 static inline void pci_set_of_node(struct pci_dev *dev) { }
1867 static inline void pci_release_of_node(struct pci_dev *dev) { }
1868 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1869 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1870 #endif /* CONFIG_OF */
1873 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1875 return pdev->dev.archdata.edev;
1880 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1881 * @pdev: the PCI device
1883 * if the device is PCIE, return NULL
1884 * if the device isn't connected to a PCIe bridge (that is its parent is a
1885 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1888 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1890 #endif /* LINUX_PCI_H */