2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
39 #include <linux/cpu_rmap.h>
41 #include <linux/atomic.h>
43 #include <linux/clocksource.h>
45 #define MAX_MSIX_P_PORT 17
47 #define MSIX_LEGACY_SZ 4
48 #define MIN_MSIX_P_PORT 5
51 MLX4_FLAG_MSI_X = 1 << 0,
52 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
53 MLX4_FLAG_MASTER = 1 << 2,
54 MLX4_FLAG_SLAVE = 1 << 3,
55 MLX4_FLAG_SRIOV = 1 << 4,
59 MLX4_PORT_CAP_IS_SM = 1 << 1,
60 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
65 MLX4_MAX_PORT_PKEYS = 128
68 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
69 * These qkeys must not be allowed for general use. This is a 64k range,
70 * and to test for violation, we use the mask (protect against future chg).
72 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
73 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
76 MLX4_BOARD_ID_LEN = 64
83 MLX4_MAX_EQ_NUM = 1024,
84 MLX4_MFUNC_EQ_NUM = 4,
85 MLX4_MFUNC_MAX_EQES = 8,
86 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
89 /* Driver supports 3 diffrent device methods to manage traffic steering:
90 * -device managed - High level API for ib and eth flow steering. FW is
91 * managing flow steering tables.
92 * - B0 steering mode - Common low level API for ib and (if supported) eth.
93 * - A0 steering mode - Limited low level API for eth. In case of IB,
97 MLX4_STEERING_MODE_A0,
98 MLX4_STEERING_MODE_B0,
99 MLX4_STEERING_MODE_DEVICE_MANAGED
102 static inline const char *mlx4_steering_mode_str(int steering_mode)
104 switch (steering_mode) {
105 case MLX4_STEERING_MODE_A0:
106 return "A0 steering";
108 case MLX4_STEERING_MODE_B0:
109 return "B0 steering";
111 case MLX4_STEERING_MODE_DEVICE_MANAGED:
112 return "Device managed flow steering";
115 return "Unrecognize steering mode";
120 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
121 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
122 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
123 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
124 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
125 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
126 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
127 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
128 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
129 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
130 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
131 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
132 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
133 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
134 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
135 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
136 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
137 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
138 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
139 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
140 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
141 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
142 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
143 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
144 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
145 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
146 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
147 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
148 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
149 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
153 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
154 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
155 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
156 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
157 MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN = 1LL << 4,
158 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5
162 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
163 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
167 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
171 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
175 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
178 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
179 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
180 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
181 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
182 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
183 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
187 MLX4_EVENT_TYPE_COMP = 0x00,
188 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
189 MLX4_EVENT_TYPE_COMM_EST = 0x02,
190 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
191 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
192 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
193 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
194 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
195 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
196 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
197 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
198 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
199 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
200 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
201 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
202 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
203 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
204 MLX4_EVENT_TYPE_CMD = 0x0a,
205 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
206 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
207 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
208 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
209 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
210 MLX4_EVENT_TYPE_NONE = 0xff,
214 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
215 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
219 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
222 enum slave_port_state {
228 enum slave_port_gen_event {
229 SLAVE_PORT_GEN_EVENT_DOWN = 0,
230 SLAVE_PORT_GEN_EVENT_UP,
231 SLAVE_PORT_GEN_EVENT_NONE,
234 enum slave_port_state_event {
235 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
236 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
237 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
238 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
242 MLX4_PERM_LOCAL_READ = 1 << 10,
243 MLX4_PERM_LOCAL_WRITE = 1 << 11,
244 MLX4_PERM_REMOTE_READ = 1 << 12,
245 MLX4_PERM_REMOTE_WRITE = 1 << 13,
246 MLX4_PERM_ATOMIC = 1 << 14,
247 MLX4_PERM_BIND_MW = 1 << 15,
251 MLX4_OPCODE_NOP = 0x00,
252 MLX4_OPCODE_SEND_INVAL = 0x01,
253 MLX4_OPCODE_RDMA_WRITE = 0x08,
254 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
255 MLX4_OPCODE_SEND = 0x0a,
256 MLX4_OPCODE_SEND_IMM = 0x0b,
257 MLX4_OPCODE_LSO = 0x0e,
258 MLX4_OPCODE_RDMA_READ = 0x10,
259 MLX4_OPCODE_ATOMIC_CS = 0x11,
260 MLX4_OPCODE_ATOMIC_FA = 0x12,
261 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
262 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
263 MLX4_OPCODE_BIND_MW = 0x18,
264 MLX4_OPCODE_FMR = 0x19,
265 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
266 MLX4_OPCODE_CONFIG_CMD = 0x1f,
268 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
269 MLX4_RECV_OPCODE_SEND = 0x01,
270 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
271 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
273 MLX4_CQE_OPCODE_ERROR = 0x1e,
274 MLX4_CQE_OPCODE_RESIZE = 0x16,
278 MLX4_STAT_RATE_OFFSET = 5
282 MLX4_PROT_IB_IPV6 = 0,
289 MLX4_MTT_FLAG_PRESENT = 1
292 enum mlx4_qp_region {
293 MLX4_QP_REGION_FW = 0,
294 MLX4_QP_REGION_ETH_ADDR,
295 MLX4_QP_REGION_FC_ADDR,
296 MLX4_QP_REGION_FC_EXCH,
300 enum mlx4_port_type {
301 MLX4_PORT_TYPE_NONE = 0,
302 MLX4_PORT_TYPE_IB = 1,
303 MLX4_PORT_TYPE_ETH = 2,
304 MLX4_PORT_TYPE_AUTO = 3
307 enum mlx4_special_vlan_idx {
308 MLX4_NO_VLAN_IDX = 0,
313 enum mlx4_steer_type {
320 MLX4_NUM_FEXCH = 64 * 1024,
324 MLX4_MAX_FAST_REG_PAGES = 511,
328 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
329 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
330 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
333 /* Port mgmt change event handling */
335 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
336 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
337 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
338 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
339 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
342 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
343 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
345 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
347 return (major << 32) | (minor << 16) | subminor;
350 struct mlx4_phys_caps {
351 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
352 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
356 u32 base_tunnel_sqpn;
363 int vl_cap[MLX4_MAX_PORTS + 1];
364 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
365 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
366 u64 def_mac[MLX4_MAX_PORTS + 1];
367 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
368 int gid_table_len[MLX4_MAX_PORTS + 1];
369 int pkey_table_len[MLX4_MAX_PORTS + 1];
370 int trans_type[MLX4_MAX_PORTS + 1];
371 int vendor_oui[MLX4_MAX_PORTS + 1];
372 int wavelength[MLX4_MAX_PORTS + 1];
373 u64 trans_code[MLX4_MAX_PORTS + 1];
374 int local_ca_ack_delay;
378 int bf_regs_per_page;
385 int max_qp_init_rdma;
386 int max_qp_dest_rdma;
400 int num_comp_vectors;
405 int fmr_reserved_mtts;
414 int fs_log_max_ucast_qp_range_size;
426 u16 stat_rate_support;
427 u8 port_width_cap[MLX4_MAX_PORTS + 1];
430 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
432 int reserved_qps_base[MLX4_NUM_QP_REGION];
436 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
437 u8 supported_type[MLX4_MAX_PORTS + 1];
438 u8 suggested_type[MLX4_MAX_PORTS + 1];
439 u8 default_sense[MLX4_MAX_PORTS + 1];
440 u32 port_mask[MLX4_MAX_PORTS + 1];
441 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
443 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
448 u32 userspace_caps; /* userspace must be aware of these */
449 u32 function_caps; /* VFs must be aware of these */
453 struct mlx4_buf_list {
459 struct mlx4_buf_list direct;
460 struct mlx4_buf_list *page_list;
473 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
476 struct mlx4_db_pgdir {
477 struct list_head list;
478 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
479 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
480 unsigned long *bits[2];
485 struct mlx4_ib_user_db_page;
490 struct mlx4_db_pgdir *pgdir;
491 struct mlx4_ib_user_db_page *user_page;
498 struct mlx4_hwq_resources {
522 enum mlx4_mw_type type;
528 struct mlx4_mpt_entry *mpt;
530 dma_addr_t dma_handle;
540 struct list_head bf_list;
541 unsigned free_bf_bmap;
543 void __iomem *bf_map;
547 unsigned long offset;
549 struct mlx4_uar *uar;
554 void (*comp) (struct mlx4_cq *);
555 void (*event) (struct mlx4_cq *, enum mlx4_event);
557 struct mlx4_uar *uar;
569 struct completion free;
573 void (*event) (struct mlx4_qp *, enum mlx4_event);
578 struct completion free;
582 void (*event) (struct mlx4_srq *, enum mlx4_event);
590 struct completion free;
602 __be32 sl_tclass_flowlabel;
615 __be32 sl_tclass_flowlabel;
624 struct mlx4_eth_av eth;
627 struct mlx4_counter {
639 struct pci_dev *pdev;
641 unsigned long num_slaves;
642 struct mlx4_caps caps;
643 struct mlx4_phys_caps phys_caps;
644 struct radix_tree_root qp_table_tree;
646 char board_id[MLX4_BOARD_ID_LEN];
648 int oper_log_mgm_entry_size;
649 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
650 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
686 } __packed port_change;
688 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
690 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
691 } __packed comm_channel_arm;
696 } __packed mac_update;
699 } __packed flr_event;
701 __be16 current_temperature;
702 __be16 warning_threshold;
715 } __packed port_info;
718 __be32 tbl_entries_mask;
719 } __packed tbl_change_info;
721 } __packed port_mgmt_change;
728 struct mlx4_init_port_param {
742 #define mlx4_foreach_port(port, dev, type) \
743 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
744 if ((type) == (dev)->caps.port_mask[(port)])
746 #define mlx4_foreach_non_ib_transport_port(port, dev) \
747 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
748 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
750 #define mlx4_foreach_ib_transport_port(port, dev) \
751 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
752 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
753 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
755 #define MLX4_INVALID_SLAVE_ID 0xFF
757 void handle_port_mgmt_change_event(struct work_struct *work);
759 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
761 return dev->caps.function;
764 static inline int mlx4_is_master(struct mlx4_dev *dev)
766 return dev->flags & MLX4_FLAG_MASTER;
769 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
771 return (qpn < dev->phys_caps.base_sqpn + 8 +
772 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
775 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
777 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
779 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
785 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
787 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
790 static inline int mlx4_is_slave(struct mlx4_dev *dev)
792 return dev->flags & MLX4_FLAG_SLAVE;
795 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
796 struct mlx4_buf *buf);
797 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
798 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
800 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
801 return buf->direct.buf + offset;
803 return buf->page_list[offset >> PAGE_SHIFT].buf +
804 (offset & (PAGE_SIZE - 1));
807 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
808 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
809 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
810 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
812 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
813 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
814 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
815 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
817 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
818 struct mlx4_mtt *mtt);
819 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
820 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
822 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
823 int npages, int page_shift, struct mlx4_mr *mr);
824 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
825 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
826 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
828 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
829 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
830 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
831 int start_index, int npages, u64 *page_list);
832 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
833 struct mlx4_buf *buf);
835 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
836 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
838 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
839 int size, int max_direct);
840 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
843 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
844 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
845 unsigned vector, int collapsed, int timestamp_en);
846 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
848 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
849 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
851 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
852 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
854 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
855 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
856 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
857 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
858 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
860 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
861 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
863 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
864 int block_mcast_loopback, enum mlx4_protocol prot);
865 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
866 enum mlx4_protocol prot);
867 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
868 u8 port, int block_mcast_loopback,
869 enum mlx4_protocol protocol, u64 *reg_id);
870 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
871 enum mlx4_protocol protocol, u64 reg_id);
874 MLX4_DOMAIN_UVERBS = 0x1000,
875 MLX4_DOMAIN_ETHTOOL = 0x2000,
876 MLX4_DOMAIN_RFS = 0x3000,
877 MLX4_DOMAIN_NIC = 0x5000,
880 enum mlx4_net_trans_rule_id {
881 MLX4_NET_TRANS_RULE_ID_ETH = 0,
882 MLX4_NET_TRANS_RULE_ID_IB,
883 MLX4_NET_TRANS_RULE_ID_IPV6,
884 MLX4_NET_TRANS_RULE_ID_IPV4,
885 MLX4_NET_TRANS_RULE_ID_TCP,
886 MLX4_NET_TRANS_RULE_ID_UDP,
887 MLX4_NET_TRANS_RULE_NUM, /* should be last */
890 extern const u16 __sw_id_hw[];
892 static inline int map_hw_to_sw_id(u16 header_id)
896 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
897 if (header_id == __sw_id_hw[i])
903 enum mlx4_net_trans_promisc_mode {
904 MLX4_FS_PROMISC_NONE = 0,
905 MLX4_FS_PROMISC_UPLINK,
906 /* For future use. Not implemented yet */
907 MLX4_FS_PROMISC_FUNCTION_PORT,
908 MLX4_FS_PROMISC_ALL_MULTI,
911 struct mlx4_spec_eth {
916 u8 ether_type_enable;
922 struct mlx4_spec_tcp_udp {
929 struct mlx4_spec_ipv4 {
936 struct mlx4_spec_ib {
943 struct mlx4_spec_list {
944 struct list_head list;
945 enum mlx4_net_trans_rule_id id;
947 struct mlx4_spec_eth eth;
948 struct mlx4_spec_ib ib;
949 struct mlx4_spec_ipv4 ipv4;
950 struct mlx4_spec_tcp_udp tcp_udp;
954 enum mlx4_net_trans_hw_rule_queue {
955 MLX4_NET_TRANS_Q_FIFO,
956 MLX4_NET_TRANS_Q_LIFO,
959 struct mlx4_net_trans_rule {
960 struct list_head list;
961 enum mlx4_net_trans_hw_rule_queue queue_mode;
964 enum mlx4_net_trans_promisc_mode promisc_mode;
970 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
971 enum mlx4_net_trans_promisc_mode mode);
972 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
973 enum mlx4_net_trans_promisc_mode mode);
974 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
975 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
976 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
977 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
978 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
980 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
981 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
982 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
983 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
984 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
985 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
986 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
987 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
989 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
990 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
991 u8 *pg, u16 *ratelimit);
992 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
993 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
994 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
996 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
997 int npages, u64 iova, u32 *lkey, u32 *rkey);
998 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
999 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1000 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1001 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1002 u32 *lkey, u32 *rkey);
1003 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1004 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1005 int mlx4_test_interrupts(struct mlx4_dev *dev);
1006 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1008 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1010 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1011 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1013 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1014 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1016 int mlx4_flow_attach(struct mlx4_dev *dev,
1017 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1018 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1020 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1023 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1025 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1026 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1027 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1028 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1029 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1030 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1031 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1033 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1034 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1036 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1038 #endif /* MLX4_DEVICE_H */