Pileus Git - ~andy/linux/blob - include/linux/mlx4/cq.h

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX4_CQ_H
  34 #define MLX4_CQ_H
  35
  36 #include <linux/types.h>
  37
  38 #include <linux/mlx4/device.h>
  39 #include <linux/mlx4/doorbell.h>
  40
  41 struct mlx4_cqe {
  42         __be32                  vlan_my_qpn;
  43         __be32                  immed_rss_invalid;
  44         __be32                  g_mlpath_rqpn;
  45         __be16                  sl_vid;
  46         __be16                  rlid;
  47         __be16                  status;
  48         u8                      ipv6_ext_mask;
  49         u8                      badfcs_enc;
  50         __be32                  byte_cnt;
  51         __be16                  wqe_index;
  52         __be16                  checksum;
  53         u8                      reserved[3];
  54         u8                      owner_sr_opcode;
  55 };
  56
  57 struct mlx4_err_cqe {
  58         __be32                  my_qpn;
  59         u32                     reserved1[5];
  60         __be16                  wqe_index;
  61         u8                      vendor_err_syndrome;
  62         u8                      syndrome;
  63         u8                      reserved2[3];
  64         u8                      owner_sr_opcode;
  65 };
  66
  67 struct mlx4_ts_cqe {
  68         __be32                  vlan_my_qpn;
  69         __be32                  immed_rss_invalid;
  70         __be32                  g_mlpath_rqpn;
  71         __be32                  timestamp_hi;
  72         __be16                  status;
  73         u8                      ipv6_ext_mask;
  74         u8                      badfcs_enc;
  75         __be32                  byte_cnt;
  76         __be16                  wqe_index;
  77         __be16                  checksum;
  78         u8                      reserved;
  79         __be16                  timestamp_lo;
  80         u8                      owner_sr_opcode;
  81 } __packed;
  82
  83 enum {
  84         MLX4_CQE_L2_TUNNEL_IPOK         = 1 << 31,
  85         MLX4_CQE_VLAN_PRESENT_MASK      = 1 << 29,
  86         MLX4_CQE_L2_TUNNEL              = 1 << 27,
  87         MLX4_CQE_L2_TUNNEL_CSUM         = 1 << 26,
  88         MLX4_CQE_L2_TUNNEL_IPV4         = 1 << 25,
  89
  90         MLX4_CQE_QPN_MASK               = 0xffffff,
  91 };
  92
  93 enum {
  94         MLX4_CQE_OWNER_MASK     = 0x80,
  95         MLX4_CQE_IS_SEND_MASK   = 0x40,
  96         MLX4_CQE_OPCODE_MASK    = 0x1f
  97 };
  98
  99 enum {
 100         MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR              = 0x01,
 101         MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR               = 0x02,
 102         MLX4_CQE_SYNDROME_LOCAL_PROT_ERR                = 0x04,
 103         MLX4_CQE_SYNDROME_WR_FLUSH_ERR                  = 0x05,
 104         MLX4_CQE_SYNDROME_MW_BIND_ERR                   = 0x06,
 105         MLX4_CQE_SYNDROME_BAD_RESP_ERR                  = 0x10,
 106         MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR              = 0x11,
 107         MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR          = 0x12,
 108         MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR             = 0x13,
 109         MLX4_CQE_SYNDROME_REMOTE_OP_ERR                 = 0x14,
 110         MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR       = 0x15,
 111         MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR             = 0x16,
 112         MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR            = 0x22,
 113 };
 114
 115 enum {
 116         MLX4_CQE_STATUS_IPV4            = 1 << 6,
 117         MLX4_CQE_STATUS_IPV4F           = 1 << 7,
 118         MLX4_CQE_STATUS_IPV6            = 1 << 8,
 119         MLX4_CQE_STATUS_IPV4OPT         = 1 << 9,
 120         MLX4_CQE_STATUS_TCP             = 1 << 10,
 121         MLX4_CQE_STATUS_UDP             = 1 << 11,
 122         MLX4_CQE_STATUS_IPOK            = 1 << 12,
 123 };
 124
 125 enum {
 126         MLX4_CQE_LLC                     = 1,
 127         MLX4_CQE_SNAP                    = 1 << 1,
 128         MLX4_CQE_BAD_FCS                 = 1 << 4,
 129 };
 130
 131 static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,
 132                                void __iomem *uar_page,
 133                                spinlock_t *doorbell_lock)
 134 {
 135         __be32 doorbell[2];
 136         u32 sn;
 137         u32 ci;
 138
 139         sn = cq->arm_sn & 3;
 140         ci = cq->cons_index & 0xffffff;
 141
 142         *cq->arm_db = cpu_to_be32(sn << 28 | cmd | ci);
 143
 144         /*
 145          * Make sure that the doorbell record in host memory is
 146          * written before ringing the doorbell via PCI MMIO.
 147          */
 148         wmb();
 149
 150         doorbell[0] = cpu_to_be32(sn << 28 | cmd | cq->cqn);
 151         doorbell[1] = cpu_to_be32(ci);
 152
 153         mlx4_write64(doorbell, uar_page + MLX4_CQ_DOORBELL, doorbell_lock);
 154 }
 155
 156 static inline void mlx4_cq_set_ci(struct mlx4_cq *cq)
 157 {
 158         *cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff);
 159 }
 160
 161 enum {
 162         MLX4_CQ_DB_REQ_NOT_SOL          = 1 << 24,
 163         MLX4_CQ_DB_REQ_NOT              = 2 << 24
 164 };
 165
 166 int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
 167                    u16 count, u16 period);
 168 int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq,
 169                    int entries, struct mlx4_mtt *mtt);
 170
 171 #endif /* MLX4_CQ_H */